TWI311705B - Peripheral component interconnect express and changing method of link power states thereof - Google Patents

Peripheral component interconnect express and changing method of link power states thereof Download PDF

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TWI311705B
TWI311705B TW094138229A TW94138229A TWI311705B TW I311705 B TWI311705 B TW I311705B TW 094138229 A TW094138229 A TW 094138229A TW 94138229 A TW94138229 A TW 94138229A TW I311705 B TWI311705 B TW I311705B
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link
component
upstream
power state
data transmission
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TW094138229A
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TW200641595A (en
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Wen-Yu Tseng
Jin-Liang Mao
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Via Tech Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/10—Current supply arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/12—Arrangements for remote connection or disconnection of substations or of equipment thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/14—Multichannel or multilink protocols
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Power Sources (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Supply And Distribution Of Alternating Current (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Electrotherapy Devices (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Description

1311705
三達編號：TW2353PA 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種資 周邊裝置互連高速資料傳輪系、构系統，且特別是有關於—種 Ί、、，光及其鏈結電源狀態改變方法。 【先前技術】 隨著時間的巨輪不斷向 邊零件連接介面（Peripheral C ，在個人電腦原為主流的周 土十 C〇mp〇nent hterconnect，ΡΓΤ、，卢 未來的處理器與輸出/輸入 ）在 出… 吊要更南的傳輸頻寬’已漸漸超 .來各』推出新—代的pcie—以做為未 末各種運异平台的標準區域輪 效能的提升，單向傳輸速率即 排宙、最大特色係為 ί P 了達2.5GHz ’更可藉擴增通道 U傳輸柄，例如❹4通道料㈣輪速度提升4倍。 厂級配置與電源介面㈤以一 c。啦_丨。“ =一υ’係定義元件於各個情況 ： 兀件電源狀態（device power states 〜％為 更進-步 )。而 PCI ExPfess =/〜義兀件間之鏈結之電源狀態，稱為鏈結電源狀態
States ’ L_states)。且各個鏈結電源狀態與元 狀恶亦有相對應之關係。 元件電源狀態、D0㈣-0n)係表示元件係於正常工作的狀 也、下。兀件於元件電源狀態DG _，此時元件 於鏈結電源狀態L0、L0s或L1。 鍵、“糸處 元件電源狀態m及D 2並未明顯地定義出，但概括而士， 兀件電源狀態D 2較D 〇與D i節省電力，但保持較少元件的。狀 怨。兀件電源狀態D1較D2節省電力，但可保持更多元件的狀 6 1311705
三達編號：TW2353PA 態 -件電源狀悲D1及D2係對應至鏈結電源狀態l工 兀件電源狀態D3(0ff)表示關機狀態，包括有斑 二狀：。當元件於肢。ld狀態時，表示主電源未提供至； 。虽疋件於D3h〇t狀態時，表示主電源提供至元件。當元件 ，電源狀態係於D3cold狀態’若有輔助電源（咖㈣p〇叫 提（兀件則兀件之間之鏈結係對應至鏈結電源狀態L2 ;若 無3電源：：給元：，則元件之間之鏈結係對應至鏈結電源狀態 兀“源狀恶D3hot係對應至鏈結電源狀態L1或l2/L3 ready ° 、、鏈結電源狀態L0係、元件之間之鏈結於正常卫作狀態 鏈結電源狀態L〇s係於元件之間的鏈結傳輸資料時， :有=的貢料傳輸的閒置時段，可進入鏈結電源狀態 減少功率的耗損。 元件之間之鏈結於鏈結電源狀態u日夺，元件 工作要求的狀態下’而會減低元件之間之鏈結電力的需求。丁此 日、亚無時脈訊號之觸發，及鎖相迴路電路㈣咖 Loop ’ PLL)亦暫停使用。 鏈結電源狀態L2與鏈結電源狀1L3係為 =鍵結電源狀態L2有輔助電源的存在，而鏈結;f 無辅助電源。 τ l 【發明内容】 有鑑於此，本發明提供一種周邊裝置互連高速資 統及其電源鏈結狀態改變方法。藉由於上游元 ^ 預疋8寸間’當上游兀件未於两述之預定時間内接 .1311705
' 二逹編號：TW2353PA " 收下游元件所產生之確認信號時，上游元件將鏈結自第一電源 鏈結狀態改變至第二鏈結電源狀態，以移除鏈結之電源。 本發明提出一種周邊裝置互連高速資料傳輸系統。周邊裝 置互連高速（Peripheral Component Interc〇nnect Express，pciE) 資料傳輸系統包括上游元件、下游元件及鏈結。當鏈結於第一 .鏈結電源狀態時，下游元件與上游元件係透過鏈結正常傳輸資 .=。上游元件於產生關閉信號後，開始計時一預定時間。而下 .% 70件於接收關閉信號後，輪出確認信號至上游元件。若上游 φ 元件未於預定時間内接收確認信號，上游元件於預定時間後， 使鏈結自第-鏈結電源狀態改變至第二鏈結電源狀態，以 鏈結之電源。 本發明提出-種周邊裝置互連高速資料傳輸系統之鍵社 電源狀態改變方法。周邊裝置互連高速資料傳輸系統包括上游 =件、下游元件及鏈結，下游元件與上游元件係透過鏈結傳輸 貝料。鏈結電源狀態改變方法包括如下步驟：首先，上游元 發出關閉信號至下游元件，並開始計時一可調整預定時間，而 4時鍵結係於—第—鏈結電源狀態。接著， 信號後’輪出確認信號至上游元件。最後，若上游元== 接收確認信號’上游元件使鏈結自第-鏈結電 '、〜、—吏至第一鏈結電源狀態，以移除鏈結之電源。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下 '牛車乂佳貫施例，並配合所附圖式，作詳細說明如下： 【實施方式] 其繪示係於PCI Exp 請參照第1圖 級（layer)架構圖。 ress之鏈結（link)與層 8

Claims (1)

1311705 •三達編號：TW2353PA - 十、申請專利範圍： 1. 一種資料傳輸系統，包括： 一上游元件； 至少一下游元件；以及 一鏈結’用以連接該上游元件以及該下游元件，其中該鏈 結係於一第一鏈結電源狀態； 其中，當該上游元件輸出一關閉訊號至該下游元件並開始 - j時一預定時間，若該上游元件未於該預定時間内接收由該下 .游元件輸出之一確認信號，則該上游元件使該鏈結自該第一鏈 結電源狀態改變至一第二鏈結電源狀態。 2·如申凊專利範圍第1項所述之資料傳輸系統，其中當 該上游=件於該預定時間内接收該確認信號，該上游元i根據 該確認信號使該鏈結自該第一鏈結電源狀態改變成該第二鍵結 1如甲請專利範圍第 於該第一鏠結電源狀態時， 鏈結正常傳輸資料。 4·如申請專利範圍第 1玄下游元件於該預定時間内 第一鏈結電源狀態改變成該 5.如申請專利範圍第 鏈結由該第—鏈結電源狀態 除該鏈結之電源。 6·如申請專利範圍第 第一鏈結電源狀態係為鏈結 7.如申請專利範圍第 1項所述之資料傳輸系統，其中當 該上游元件與該下游元件係透過^ 1項所述之資料傳輪系統，其中若 純到該關閉訊號，則該鏈結自該 第二鏈結電源狀態。 '人 1項所述之資料傳輸系統，Α 改變成該第二鏈結電源狀態用” 1項所述之資料傳輸系統，其中該 電源狀態L0。 15 1 項所述之資料傳輪系統，其中該 1311705 .三達編號：TW2353PA •第二鏈結電源狀態為鏈結電源狀態L2或鍵結電匕 8. 如申請專利範圍…所述之資料傳輪系：、二 上游凡件係為一根聯合體（R⑽t c〇mplex，Rc) ’該 ，、中遠 周邊裝置（End P〇int，Ep>。 4元件為— 9, 如申請專利範圍第1項所述之資料傳輪 預定時間可調整。 、死其中该 :上二範圍第8項所述之資料傳輪系統，… 上游兀件包括—暫存器，用以儲存至少一個該預定時間j ,二：：：專利範圍第1項所述之資料傳輪系統，其中該 β兀h 3有-㈣器’用以計時該預定時間。 ’ Μ請專利範圍第i項所述之資料傳輸㈣， 貝；:；傳輸系統為-周邊裝置互連高速（PCIE)資料傳輸系統。·^ 13. —種貧料傳輸系統鏈結電源狀態改 輸系統包括-上游元件、一下游…Μ去°玄貝枓傳 干 下办70件及一鏈結，該下游元件鱼 "3兀件係透過該鏈結傳輪資料，該鏈結電源狀態改變方法 包括.
S亥上游凡件發出一關閉信號至寧下游元件，並開始計時一 可調整預定時間； 一忒下游元件接收到該關閉信號後，輸出—確認信號至兮 游元件；以及 w 〇 1若該上游元件未於該可調整預定時間内接收該確認信 〇 Λ上游元件使6亥鏈結自一第一鏈結電源狀態改變至—第二 鏈結電源狀態，用以移除該鏈結之電源。 一丨4.如申4專利範圍第13項所述之方法，其中當該上游 兀件於4可㈣預定時間内接收該4認信號，則根據該確句产 號使該鏈結自該第一鏈結電源狀態改變至該第二鏈結電源： 16
TW094138229A 2005-05-23 2005-11-01 Peripheral component interconnect express and changing method of link power states thereof TWI311705B (en)

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US11/429,941 US7849340B2 (en) 2005-05-23 2006-05-09 Data transmission system and link state managing method thereof using turn-off acknowledgement and electrical idle waiting timeouts

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TW094138229A TWI311705B (en) 2005-05-23 2005-11-01 Peripheral component interconnect express and changing method of link power states thereof
TW094138424A TWI298839B (en) 2005-05-23 2005-11-02 Pci express transitioning link power state system and method thereof
TW094139010A TWI295769B (en) 2005-05-23 2005-11-07 Pci express system and method of transitioning link power state thereof
TW095102706A TWI325536B (en) 2005-05-23 2006-01-24 Pci express transitioning link power state system and mehtod thereof
TW095107634A TWI308695B (en) 2005-05-23 2006-03-07 Data transition system and method of transitioning link power state thereof

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TW095102706A TWI325536B (en) 2005-05-23 2006-01-24 Pci express transitioning link power state system and mehtod thereof
TW095107634A TWI308695B (en) 2005-05-23 2006-03-07 Data transition system and method of transitioning link power state thereof

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