US20060265611A1 - PCI Express system and method of transitioning link state thereof - Google Patents
PCI Express system and method of transitioning link state thereof Download PDFInfo
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- US20060265611A1 US20060265611A1 US11/386,754 US38675406A US2006265611A1 US 20060265611 A1 US20060265611 A1 US 20060265611A1 US 38675406 A US38675406 A US 38675406A US 2006265611 A1 US2006265611 A1 US 2006265611A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/10—Current supply arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/02—Details
- H04L12/12—Arrangements for remote connection or disconnection of substations or of equipment thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/14—Multichannel or multilink protocols
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Definitions
- This invention relates to an apparatus and a method of transitioning state, more specifically to an apparatus and a method of transitioning link state for PCI Express.
- PCI Peripheral Device Interconnect
- Single direction transmission rate can reach up to 2.5 GHz.
- the transmission rate can be increased by expanding the number of lanes. For example, using 4 lanes can speed up the transmission rate to 4 times.
- ACPI Advanced Configuration and Power Interface
- Device state D 0 (Full-On) represents that the device is under normal operation.
- the link between devices could be in the link states L 0 , L 0 s , or L 1 .
- Device states D 1 and D 2 are not specifically defined in APCI. In general, device state D 2 is more power saving than device state D 0 and D 1 when the number of devices is few. Device state D 1 is more power saving than device state D 2 when the number of devices is relative large. Device states D 1 and D 2 could be corresponding to the link state L 1 .
- Device state D 3 (Off), including D 3 cold and D 3 hot states, represents the shut-down state.
- the main power does not supply to the device.
- the device is in D 3 hot state, the main power is supplied to the device.
- the link between the devices could be under the link state L 2 if there has an auxiliary power to supply power. If there is no auxiliary power, the link could be under the link power state L 3 .
- Device state D 3 hot corresponds to the link state L 1 .
- Link state L 0 is the state when the link between devices is in normal operation. Link state L 0 s can decrease the power consumption when the link has short idle periods during data transmission.
- the devices When the link is in the link state L 1 , the devices are in pause state with no request. This will decrease the demand of link power between devices. At the time there is no trigger of time pulse signal, and the Phase Lock Loop (PPL) will pause for any function.
- PPL Phase Lock Loop
- Link state L 2 and L 3 are shut-down states.
- the difference between L 2 and L 3 is that the link state L 2 is supplied by an auxiliary power, but the link state L 3 has no auxiliary power.
- the link when the link is in a power saving link state, such as the link state L 1 , the link has to transit to a normal link state so that data packet can be transmitted by the upstream device to the downstream device. After the transmission ends, the link will transit back to power saving link state L 1 .
- transmission error of data packet easily causes the link states transitioning repeatedly. More seriously it may cause the system to shut down.
- the present invention provides an apparatus of PCI Express system and a method of transitioning link state thereof that avoids the transmission error of data packet.
- the present invention provides a method of PCI Express transitioning link state for a link between an upstream device and a downstream device.
- the upstream device and the downstream device transmit data to both through the link. Data transmission is forbidden when the link is in a first link state, and the downstream device is in the abnormal operation state.
- the method includes: transiting the link to a second link state in which data packet transmission is normal. Then the upstream device transmits a data packet to the downstream device through the link. Later, a time period is counted when the downstream device receives the data packet. Then the downstream device asserts an acknowledge packet to the upstream device for responding the data packet. When the time period is expired, and the downstream device asserts a power entry packet PM_Enter_L 1 to the upstream device, and the link is then transited back to the first link state.
- the present invention also provides a PCI Express system including an upstream device, a downstream device, and a link.
- the downstream device is in a first device state.
- the upstream device and the downstream device transmit data packets to both through the link.
- the link transits to a second link state to normally transmit data packets.
- the upstream device transmits a data packet to the downstream device through the link.
- a time period is counted when the data packet is received, and the downstream device asserts an acknowledge packet to the upstream device for responding the data packet.
- the downstream device asserts a power entry packet PM_Enter_L 1 to the upstream device, and the link is transited back to the first link state.
- FIG. 1 is a schematic diagram of PCI Express link and layers.
- FIG. 2 is a flowchart of the method of PCI Express transitioning link state
- FIG. 3 is a relative waveform of the link transition between first link state and second link state.
- the PCIE system 100 of the present invention includes an upstream device 110 , a downstream device 120 , and a link 130 connected between the upstream device 110 and the downstream device 120 .
- the upstream device 110 includes: a Transaction Layer (TL) 111 , a Data Link Layer (DLL) 112 , and a Physical Layer (PHY) 113 .
- the downstream device 120 also includes: a Transaction Layer 121 , a Data Link Layer 122 , and a Physical Layer 123 .
- the upstream device can be, for example, a Root Complex (RC), and the downstream device as well can be an End Point (EP).
- RC Root Complex
- EP End Point
- the Transaction Layers 111 and 121 respectively generate data packets to the Data Link Layers 112 and 122 .
- the Transaction Layers 111 and 121 also respectively receive data packets from the Data Link Layers 112 and 122 . Meanwhile the Transaction Layers 111 and 112 also manage the flow control between devices. Data packets generated by or received from the Transaction Layers 111 and 121 are regarded as Transaction Layer Packets (TLPs).
- TLPs Transaction Layer Packets
- the Data Link Layers 112 is in charge of data packets transmission between the Physical Layers 113 and the Transaction Layer 111 ; similarly the Data Link Layers 122 is in charge of data packets transmission between the Physical Layers 123 and the Transaction Layer 121 .
- the Data Link Layers 112 and 122 After receiving data packets, the Data Link Layers 112 and 122 respectively transmit TLPs to the corresponding Transaction Layers 112 and 121 .
- the Data Link Layers 112 and 122 also respectively receive TLPs from the corresponding Transaction Layers 111 and 121 , and then respectively output the data packets to the corresponding Physical Layer 113 and 123 .
- error detection is performed for stably transmit the data packs
- Data packets transmitted between the Data Link Layer 112 and the Physical layer 113 are or between the Data Link Layer 122 and the Physical layer 123 are regarded as Data Link Layer Packets (DLLPs).
- DLLPs Data Link Layer Packets
- the Physical Layers 113 and 123 are in charge of data packet transmission via the link 130 between the upstream devices 110 and the downstream device 120 .
- the data packets from the downstream device 120 and received by Physical Layer 113 are transformed into DLLPs format and then transmitted to the Data Link Layer 112 .
- the DLLPs from the Data Link Layer 112 are received by the Physical layer 113 and then transmitted to the downstream device 120 through the link 130 .
- the data packets from the upstream device 110 and received by the Physical Layer 113 are transformed DLLPs format and then transmitted to the Data Link Layer 122 .
- the DLLPs from the Data Link Layer 122 are received by the Physical Layer 123 and then transmitted to the upstream device 110 through the link 130 .
- FIG. 2 a flowchart of PCI Express transitioning state is shown. The method is applied to the link 130 between the upstream device 110 and the downstream device 120 .
- the present invention provides an apparatus and a method for transiting link state and transmitting data when under abnormal working state. That is to say, the downstream device 120 is in a non-first device state (the first device state for example is D 0 state). Assume the initial link state of the link 130 is in a first link state (ex. L 1 state), data transmission is forbidden.
- the Data packets can not be transmitted through the link 130 in the first link state.
- the link state of the link 130 has to transit to a second link state (ex. L 0 state) so that data transmission can be normal (step 21 ).
- the upstream device 110 asserts a data packet (ex. TLP) to the downstream device 120 through the link 130 .
- the data packet is a command for changing or reading the device state of the downstream device 120 .
- a time period is counted when the downstream device 220 receives the data packet.
- the downstream device 120 asserts an acknowledge packet to the upstream device 10 for responding the data packet.
- step 25 when the time period is expired, the downstream device 120 asserts a power entry packet, PM_Enter_L 1 (ex. DLLP), to the upstream device 110 .
- step 26 the upstream device 110 asserts a power request acknowledge packet, PM_Request_Ack, to the downstream device 120 .
- step 27 after receiving the PM_Request_Ack, the link 130 is transited to the first link state (ex. L 0 state).
- the time period could be: immediate time-out, (1 CfgW+10 cycles), (32 QW TLP+1 CfgW+10 cycles), or (2*32 QW TLP+1 CfgW+10 cycles).
- the CfgW is one data packet transmission period.
- the CfgW is, for example a transmission period of a TLP transmitted from the Transaction Layer 111 of the upstream device 110 to the Transaction Layer 121 of the downstream device 120 .
- 10 cycles represents a time period for the downstream device to process a TLP.
- QW TLP represents the QW length of a TLP (ex: 1 QW TLP means that the TLP length is 1 QW, and 1 QW is 8 bytes. Consequently 32 QW TLP is a TLP of 256 Bytes).
- the time period counted to allow the acknowledge packet is received earlier than the power entry packet, PM_Enter_L 1 . This ensures that the acknowledge packet is received and the link 130 is later transited to the first link state (ex. L 1 state) by receiving the power entry packet, PM_Enter_L 1 .
- FIG. 3 is the relative waveform of the link 130 transitioning between the first link state (ex. L 1 state) and the second link state (ex. L 0 state).
- the downstream device 120 Assume that the initial state of the downstream device 120 is in the first device state (ex. D 0 state), and the link state is in L 0 state. After idle for a while, the downstream device 120 is transited to a second device state (ex. D 1 state), which is the non-first device state, at time point t 1 . At t 1 , the downstream device 120 also asserts a power entry packet PM_Enter_L 1 to the upstream device 110 . At time point t 2 , the downstream device 220 receives the PM_Request_Ack and then the link 130 is transited to the link state L 1 .
- the process described below is referred to the flowchart in FIG. 2 .
- the downstream device 120 maintains in the second device state D 1
- the link 130 is in the link state L 1 in which data packet transmission is forbidden.
- the link 130 is transited from link state L 1 to the link state L 0 to allow data packet transmission.
- the data packet is transmitted.
- a time period ia counted and an acknowledge packet is asserted after processing the data packet.
- the downstream device 120 asserts a power entry packet PM_Enter_L 1 data packet.
- PM_Request_Ack the link 130 is transited to the link state L 1 .
- the PCI Express system and method of transitioning link state thereof revealed in the present invention has the advantage of transitioning the link state from which data packet transmission is forbidden to which is allowed. And data transmission error during the transition of the link state can be avoided. Furthermore, the present invention avoids system shut-down causing by repeated link state transitioning, and satisfies the power saving purpose of the prior art.
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Abstract
A PCI Express system and a method of transitioning link state thereof are provided. The PCI Express system has an upstream device, a downstream device and a link. The upstream device and the downstream device transmit data packets to both via the link, but when the link is in a first link state, data packet transmission is forbidden. In the beginning, the link is in a second link state and data packet transmission is normal. The upstream device transmits a data packet via the link to the downstream device. A time period is counted when receiving the data packet. The downstream device asserts an acknowledge packet to the upstream device to response the data pocket. After the timer is expired, the link is transited to the first link state.
Description
- This application claims the benefit of U.S. provisional application Ser. No. 60/683,313, filed May 23, 2005, and the benefit of Taiwan application Serial No. 95107634, filed Mar. 7, 2006, the subject matters of which are incorporated herein by reference.
- 1. Field of the Invention
- This invention relates to an apparatus and a method of transitioning state, more specifically to an apparatus and a method of transitioning link state for PCI Express.
- 2. Description of the Related Art
- As the wheel of time moves on endlessly, the Peripheral Device Interconnect (PCI) mainly for the use of Personal Computers faces a problem that the processors and input/output devices in the future generation need higher transmission bandwidth. Such transmission bandwidth gradually exceeds the working range of PCI. The industry thus develops a new generation PCI Express to be the standard regional input/output bus for all kinds of future processing platforms. The most significant feature is the improvement of transmission efficiency. Single direction transmission rate can reach up to 2.5 GHz. Furthermore, the transmission rate can be increased by expanding the number of lanes. For example, using 4 lanes can speed up the transmission rate to 4 times.
- Advanced Configuration and Power Interface (ACPI) defines the device states (D-states) under every situation. And PCI Express further defines the link states (L-states) between devices. Each link state has a corresponding relation to a device state.
- Device state D0 (Full-On) represents that the device is under normal operation. When the device is in the device state D0, the link between devices could be in the link states L0, L0 s, or L1.
- Device states D1 and D2 are not specifically defined in APCI. In general, device state D2 is more power saving than device state D0 and D1 when the number of devices is few. Device state D1 is more power saving than device state D2 when the number of devices is relative large. Device states D1 and D2 could be corresponding to the link state L1.
- Device state D3 (Off), including D3cold and D3hot states, represents the shut-down state. When the device is in D3cold state, the main power does not supply to the device. When the device is in D3hot state, the main power is supplied to the device. When the device is in D3cold state, the link between the devices could be under the link state L2 if there has an auxiliary power to supply power. If there is no auxiliary power, the link could be under the link power state L3. Device state D3hot corresponds to the link state L1.
- Link state L0 is the state when the link between devices is in normal operation. Link state L0 s can decrease the power consumption when the link has short idle periods during data transmission.
- When the link is in the link state L1, the devices are in pause state with no request. This will decrease the demand of link power between devices. At the time there is no trigger of time pulse signal, and the Phase Lock Loop (PPL) will pause for any function.
- Link state L2 and L3 are shut-down states. The difference between L2 and L3 is that the link state L2 is supplied by an auxiliary power, but the link state L3 has no auxiliary power.
- However, when the link is in a power saving link state, such as the link state L1, the link has to transit to a normal link state so that data packet can be transmitted by the upstream device to the downstream device. After the transmission ends, the link will transit back to power saving link state L1. During the process, transmission error of data packet easily causes the link states transitioning repeatedly. More seriously it may cause the system to shut down.
- To address the above-detailed deficiencies, the present invention provides an apparatus of PCI Express system and a method of transitioning link state thereof that avoids the transmission error of data packet.
- The present invention provides a method of PCI Express transitioning link state for a link between an upstream device and a downstream device. The upstream device and the downstream device transmit data to both through the link. Data transmission is forbidden when the link is in a first link state, and the downstream device is in the abnormal operation state. The method includes: transiting the link to a second link state in which data packet transmission is normal. Then the upstream device transmits a data packet to the downstream device through the link. Later, a time period is counted when the downstream device receives the data packet. Then the downstream device asserts an acknowledge packet to the upstream device for responding the data packet. When the time period is expired, and the downstream device asserts a power entry packet PM_Enter_L1 to the upstream device, and the link is then transited back to the first link state.
- The present invention also provides a PCI Express system including an upstream device, a downstream device, and a link. The downstream device is in a first device state. The upstream device and the downstream device transmit data packets to both through the link. When the link is in a first link state, data transmission is forbidden. Thus the link transits to a second link state to normally transmit data packets. The upstream device transmits a data packet to the downstream device through the link. Then a time period is counted when the data packet is received, and the downstream device asserts an acknowledge packet to the upstream device for responding the data packet. When the time period is expired, the downstream device asserts a power entry packet PM_Enter_L1 to the upstream device, and the link is transited back to the first link state.
- These and other objects, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:
-
FIG. 1 is a schematic diagram of PCI Express link and layers. -
FIG. 2 is a flowchart of the method of PCI Express transitioning link state -
FIG. 3 is a relative waveform of the link transition between first link state and second link state. - Referring to
FIG. 1 , a schematic diagram of PCIE system 100 is shown. The PCIE system 100 of the present invention includes anupstream device 110, adownstream device 120, and alink 130 connected between theupstream device 110 and thedownstream device 120. - The
upstream device 110 includes: a Transaction Layer (TL) 111, a Data Link Layer (DLL) 112, and a Physical Layer (PHY) 113. And thedownstream device 120 also includes: aTransaction Layer 121, aData Link Layer 122, and aPhysical Layer 123. - The upstream device can be, for example, a Root Complex (RC), and the downstream device as well can be an End Point (EP).
- The Transaction Layers 111 and 121 respectively generate data packets to the Data Link Layers 112 and 122. The Transaction Layers 111 and 121 also respectively receive data packets from the Data Link Layers 112 and 122. Meanwhile the Transaction Layers 111 and 112 also manage the flow control between devices. Data packets generated by or received from the Transaction Layers 111 and 121 are regarded as Transaction Layer Packets (TLPs).
- The Data Link Layers 112 is in charge of data packets transmission between the
Physical Layers 113 and theTransaction Layer 111; similarly the Data Link Layers 122 is in charge of data packets transmission between thePhysical Layers 123 and theTransaction Layer 121. - After receiving data packets, the Data Link Layers 112 and 122 respectively transmit TLPs to the corresponding Transaction Layers 112 and 121. The Data Link Layers 112 and 122 also respectively receive TLPs from the corresponding Transaction Layers 111 and 121, and then respectively output the data packets to the
corresponding Physical Layer - Data packets transmitted between the
Data Link Layer 112 and thePhysical layer 113 are or between theData Link Layer 122 and thePhysical layer 123 are regarded as Data Link Layer Packets (DLLPs). - The Physical Layers 113 and 123 are in charge of data packet transmission via the
link 130 between theupstream devices 110 and thedownstream device 120. - The data packets from the
downstream device 120 and received byPhysical Layer 113 are transformed into DLLPs format and then transmitted to theData Link Layer 112. The DLLPs from theData Link Layer 112 are received by thePhysical layer 113 and then transmitted to thedownstream device 120 through thelink 130. In the same manner, the data packets from theupstream device 110 and received by thePhysical Layer 113 are transformed DLLPs format and then transmitted to theData Link Layer 122. The DLLPs from theData Link Layer 122 are received by thePhysical Layer 123 and then transmitted to theupstream device 110 through thelink 130. - Referring to
FIG. 2 , a flowchart of PCI Express transitioning state is shown. The method is applied to thelink 130 between theupstream device 110 and thedownstream device 120. - The present invention provides an apparatus and a method for transiting link state and transmitting data when under abnormal working state. That is to say, the
downstream device 120 is in a non-first device state (the first device state for example is D0 state). Assume the initial link state of thelink 130 is in a first link state (ex. L1 state), data transmission is forbidden. - The Data packets can not be transmitted through the
link 130 in the first link state. As a result the link state of thelink 130 has to transit to a second link state (ex. L0 state) so that data transmission can be normal (step 21). Later as shown instep 22, theupstream device 110 asserts a data packet (ex. TLP) to thedownstream device 120 through thelink 130. The data packet is a command for changing or reading the device state of thedownstream device 120. Instep 23, a time period is counted when the downstream device 220 receives the data packet. Instep 24, thedownstream device 120 asserts an acknowledge packet to the upstream device 10 for responding the data packet. Instep 25, when the time period is expired, thedownstream device 120 asserts a power entry packet, PM_Enter_L1 (ex. DLLP), to theupstream device 110. Instep 26, theupstream device 110 asserts a power request acknowledge packet, PM_Request_Ack, to thedownstream device 120. Instep 27, after receiving the PM_Request_Ack, thelink 130 is transited to the first link state (ex. L0 state). - In
step 23 to step 25, the time period could be: immediate time-out, (1 CfgW+10 cycles), (32 QW TLP+1 CfgW+10 cycles), or (2*32 QW TLP+1 CfgW+10 cycles). - Wherein, the CfgW is one data packet transmission period.
- The CfgW is, for example a transmission period of a TLP transmitted from the
Transaction Layer 111 of theupstream device 110 to theTransaction Layer 121 of thedownstream device 120. 10 cycles represents a time period for the downstream device to process a TLP. QW TLP represents the QW length of a TLP (ex: 1 QW TLP means that the TLP length is 1 QW, and 1 QW is 8 bytes. Consequently 32 QW TLP is a TLP of 256 Bytes). - The time period counted to allow the acknowledge packet is received earlier than the power entry packet, PM_Enter_L1. This ensures that the acknowledge packet is received and the
link 130 is later transited to the first link state (ex. L1 state) by receiving the power entry packet, PM_Enter_L1. -
FIG. 3 is the relative waveform of thelink 130 transitioning between the first link state (ex. L1 state) and the second link state (ex. L0 state). - Assume that the initial state of the
downstream device 120 is in the first device state (ex. D0 state), and the link state is in L0 state. After idle for a while, thedownstream device 120 is transited to a second device state (ex. D1 state), which is the non-first device state, at time point t1. At t1, thedownstream device 120 also asserts a power entry packet PM_Enter_L1 to theupstream device 110. At time point t2, the downstream device 220 receives the PM_Request_Ack and then thelink 130 is transited to the link state L1. - In the following paragraphs, the process described below is referred to the flowchart in
FIG. 2 . After time point t2, thedownstream device 120 maintains in the second device state D1, thelink 130 is in the link state L1 in which data packet transmission is forbidden. - If a data packet transmission is needed, the
link 130 is transited from link state L1 to the link state L0 to allow data packet transmission. At time point t3, the data packet is transmitted. When thedownstream device 120 receives the data packet, a time period ia counted and an acknowledge packet is asserted after processing the data packet. Later at time point t4, when the time period is expired, thedownstream device 120 asserts a power entry packet PM_Enter_L1 data packet. At time point t5, after thedownstream device 120 receives a power request acknowledge packet, PM_Request_Ack, thelink 130 is transited to the link state L1. - The PCI Express system and method of transitioning link state thereof revealed in the present invention has the advantage of transitioning the link state from which data packet transmission is forbidden to which is allowed. And data transmission error during the transition of the link state can be avoided. Furthermore, the present invention avoids system shut-down causing by repeated link state transitioning, and satisfies the power saving purpose of the prior art.
- Although the present invention has been described in considerable detail. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (24)
1. A method of transitioning link state, for a link connected between an upstream device and a downstream device, wherein an initial link state of the link is in a first link state, and the downstream device is in an abnormal operation state, the method comprising:
transitioning the link state from the first link state to a second link state;
asserting a data packet by the upstream device;
counting a time period when the downstream device receives the data packet;
asserting an acknowledge packet by the downstream device to the upstream device as a response to the data packet;
asserting a power entering packet by the downstream device to the upstream device when the time period is expired; and
asserting a power request acknowledge packet by the upstream device to respond to the power entering packet so as to transit the link from the second link state to the first link state.
2. The method of claim 1 wherein the data packet is a Transaction Layer Packet (TLP); the power entering packet and the power request acknowledge packet are respectively Data Link Layer Packets (DLLPs).
3. The method of claim 1 wherein the time period is not less than one data packet transmission period plus 10 cycles.
4. The method of claim 3 wherein the time period further comprises 32 QW TLPs transmission period.
5. The method of claim 1 wherein the time period ensures the upstream device receives the acknowledge packet earlier than the power entering packet
6. The method of claim 1 wherein the first link state is the link state L0.
7. The method of claim 1 wherein the second link state is the link state L1.
8. The method of claim 1 wherein the upstream device is a Root Complex and the downstream device is an End Point.
9. The method of claim 1 wherein the method is applied to a PCI Express link.
10. A data transmission system comprising:
an upstream device, for asserting a data packet;
a downstream device, a time period is counted when the downstream device receives the data packet from the upstream device, at the same time, the downstream device asserts an acknowledge packet to the upstream device; and
a link, connected between the upstream device and the downstream device for data transmission;
wherein the downstream device asserts a power entering packet to the upstream device when the time period is expired and the time period ensures the acknowledge packet is received earlier than power entering packet.
11. The system of claim 10 wherein an initial link state of the link is at L1 state.
12. The system of claim 11 wherein the link is transited to the link state L0 before transmitting the data packet.
13. The system of claim 12 wherein the upstream device asserts a power request acknowledge packet to the downstream device as a response to the power entering packet, and the link is transited to L1 state.
14. The system of claim 10 wherein the initial link state of the downstream device is in an abnormal operation state.
15. The system of claim 10 wherein the data packet is utilized to change or read the state of the downstream device.
16. The system of claim 10 wherein the time period is not less than one data packet transmission period plus 10 cycles.
17. The system of claim 16 wherein the time period further comprises 32 QW TLPs transmission period.
18. The system of claim 10 wherein the data transmission system is a PCI Express system.
19. A method of link data transmission, for a link connected between an upstream device and a downstream device; wherein a initial link state of the link is unable to transmit data packets; the downstream device is in an abnormal operation state, the method comprising:
asserting a data packet by the upstream device;
counting a time period when the downstream device receives the data packet;
asserting an acknowledge packet by the downstream device to the upstream device as a response to the data packet; and
asserting a power entry packet by the downstream device to the upstream device when the time period is expired;
wherein the time period ensures the acknowledge packet is received earlier than the power entry packet
20. The method of claim 19 wherein the method further comprising:
transiting the link state to a state able to transmit data packet.
21. The method of claim 20 wherein the method further comprising:
asserting a power request acknowledge packet responding to the power entering packet by the upstream device so as to transit the link state to a state unable to transmit data packet.
22. The method of claim 19 wherein the time period is not less than one data packet transmission period plus 10 cycles.
23. The method of claim 22 wherein the time period further comprises 32 QW TLPs transmission period.
24. The method of claim 19 wherein the method is applied to a PCI Express system.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100330927A1 (en) * | 2009-06-30 | 2010-12-30 | Naveen Cherukuri | Link power savings with state retention |
US20120005506A1 (en) * | 2010-06-30 | 2012-01-05 | Jim Walsh | Systems and methods for implementing reduced power states |
US20130117492A1 (en) * | 2008-09-30 | 2013-05-09 | Seh W. Kwa | Platform communication protocol |
US9423864B2 (en) | 2011-07-27 | 2016-08-23 | Huawei Technologies Co., Ltd. | PCI express device and link energy management method and device |
US10216814B2 (en) | 2013-05-17 | 2019-02-26 | Oracle International Corporation | Supporting combination of flow based ETL and entity relationship based ETL |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10069711B2 (en) * | 2006-06-30 | 2018-09-04 | Intel Corporation | System and method for link based computing system having automatically adjustable bandwidth and corresponding power consumption |
KR100954819B1 (en) * | 2007-01-22 | 2010-04-28 | 이노베이티브 소닉 리미티드 | Method and related apparatus for improving MIMO procedure in a wireless communications system |
KR20080074754A (en) * | 2007-02-08 | 2008-08-13 | 이노베이티브 소닉 리미티드 | Method and related apparatus for stopping multi-input multi-output operation in a wireless communications system |
CN101123511B (en) * | 2007-09-21 | 2010-06-02 | 杭州华三通信技术有限公司 | A pci quick bus system and its energy management method |
US9146892B2 (en) * | 2007-10-11 | 2015-09-29 | Broadcom Corporation | Method and system for improving PCI-E L1 ASPM exit latency |
KR101464741B1 (en) * | 2007-12-12 | 2014-11-24 | 엘지전자 주식회사 | Apparatus and Method for controlling Power Management |
JP5096905B2 (en) * | 2007-12-20 | 2012-12-12 | 株式会社日立製作所 | Server apparatus and link recovery processing method thereof |
US8706924B2 (en) * | 2008-08-14 | 2014-04-22 | Via Technologies, Inc. | PCI-express data link transmitter employing a plurality of dynamically selectable data transmission priority rules |
US8971241B2 (en) * | 2008-09-30 | 2015-03-03 | Qualcolmm Incorporated | Techniques for supporting relay operation in wireless communication systems |
US9203564B2 (en) * | 2008-10-20 | 2015-12-01 | Qualcomm Incorporated | Data transmission via a relay station in a wireless communication system |
JP5272704B2 (en) * | 2008-12-17 | 2013-08-28 | 富士ゼロックス株式会社 | Information transmission system, information transmission device, and information reception device |
US8601296B2 (en) * | 2008-12-31 | 2013-12-03 | Intel Corporation | Downstream device service latency reporting for power management |
CN101526846B (en) * | 2009-04-29 | 2011-12-07 | 成都市华为赛门铁克科技有限公司 | Pcie system and control method thereof |
US8312187B2 (en) * | 2009-09-18 | 2012-11-13 | Oracle America, Inc. | Input/output device including a mechanism for transaction layer packet processing in multiple processor systems |
CN102075342A (en) * | 2009-11-23 | 2011-05-25 | 智微科技股份有限公司 | Network device and control method thereof |
CN102082671A (en) * | 2009-11-30 | 2011-06-01 | 智微科技股份有限公司 | Network device and control method thereof |
US20110145655A1 (en) * | 2009-12-11 | 2011-06-16 | Mike Erickson | Input/output hub to input/output device communication |
EP2729863B1 (en) * | 2011-07-06 | 2017-09-06 | Telefonaktiebolaget LM Ericsson (publ) | A method for controlling transaction exchanges between two integrated circuits |
CN102662458B (en) * | 2012-04-18 | 2015-07-08 | 华为技术有限公司 | Dynamic energy-saving method and device for PCIE equipment and communication system of PCIE equipment |
US9256268B2 (en) * | 2012-04-24 | 2016-02-09 | Intel Corporation | Adaptive low-power link-state entry policy for active interconnect link power management |
US9117036B2 (en) | 2012-09-26 | 2015-08-25 | Ati Technologies Ulc | Fast exit from low-power state for bus protocol compatible device |
CN103076868B (en) | 2013-01-06 | 2015-08-26 | 威盛电子股份有限公司 | The electronic system of method for managing power supply and application the method |
US9507838B2 (en) * | 2013-05-17 | 2016-11-29 | Oracle International Corporation | Use of projector and selector component types for ETL map design |
GB201309336D0 (en) | 2013-05-23 | 2013-07-10 | Protia As | Proton conducing ceramic membrage |
USRE49652E1 (en) | 2013-12-16 | 2023-09-12 | Qualcomm Incorporated | Power saving techniques in computing devices |
US9535490B2 (en) | 2013-12-16 | 2017-01-03 | Qualcomm Incorporated | Power saving techniques in computing devices |
KR102149679B1 (en) | 2014-02-13 | 2020-08-31 | 삼성전자주식회사 | Data storage device, method thereof, and data processing system including same |
US9880601B2 (en) | 2014-12-24 | 2018-01-30 | Intel Corporation | Method and apparatus to control a link power state |
KR20180049340A (en) * | 2016-10-31 | 2018-05-11 | 삼성전자주식회사 | Storage device and link state control method thereof |
US11054887B2 (en) * | 2017-12-28 | 2021-07-06 | Advanced Micro Devices, Inc. | System-wide low power management |
US20190250930A1 (en) * | 2018-02-12 | 2019-08-15 | Western Digital Technologies, Inc. | Method and apparatus for configuring a serial data link |
CN108924008A (en) * | 2018-07-10 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of dual controller data communications method, device, equipment and readable storage medium storing program for executing |
US11435813B2 (en) | 2018-08-29 | 2022-09-06 | Advanced Micro Devices, Inc. | Neural network power management in a multi-GPU system |
US10855600B2 (en) * | 2018-11-13 | 2020-12-01 | Intel Corporation | System, apparatus and method for traffic shaping of data communication via an interconnect |
US11073894B2 (en) * | 2019-05-24 | 2021-07-27 | Qualcomm Incorporated | System power management for peripheral component interconnect express (PCIE)-based devices |
US11836101B2 (en) * | 2019-11-27 | 2023-12-05 | Intel Corporation | Partial link width states for bidirectional multilane links |
TWI751501B (en) * | 2020-02-25 | 2022-01-01 | 宏碁股份有限公司 | Control setting method for link state transition and electronic device using the same |
US20220066531A1 (en) * | 2020-08-27 | 2022-03-03 | Realtek Semiconductor Corp. | Docking station for power management |
US11763040B2 (en) * | 2021-04-07 | 2023-09-19 | Western Digital Technologies, Inc. | Enhanced D3-cold and faster recovery |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4763296A (en) * | 1985-07-05 | 1988-08-09 | Motorola, Inc. | Watchdog timer |
US4872110A (en) * | 1987-09-03 | 1989-10-03 | Bull Hn Information Systems Inc. | Storage of input/output command timeout and acknowledge responses |
US6122690A (en) * | 1997-06-05 | 2000-09-19 | Mentor Graphics Corporation | On-chip bus architecture that is both processor independent and scalable |
US20030123486A1 (en) * | 2001-12-31 | 2003-07-03 | Globespanvirata Incorporated | System and method for utilizing power management functionality between DSL peers |
US20040128576A1 (en) * | 2002-12-31 | 2004-07-01 | Michael Gutman | Active state link power management |
US20040268169A1 (en) * | 2003-06-25 | 2004-12-30 | Bashford Patrick R. | Method and apparatus of automatic power management control for native command queuing Serial ATA device |
US20050086549A1 (en) * | 2003-10-15 | 2005-04-21 | Solomon Gary A. | Power management over switching fabrics |
US20050097378A1 (en) * | 2003-07-29 | 2005-05-05 | Hwang Andrew S. | Method and system for power management in a gigabit Ethernet chip |
US7188263B1 (en) * | 2003-05-07 | 2007-03-06 | Nvidia Corporation | Method and apparatus for controlling power state of a multi-lane serial bus link having a plurality of state transition detectors wherein powering down all the state transition detectors except one |
US7287096B2 (en) * | 2001-05-19 | 2007-10-23 | Texas Instruments Incorporated | Method for robust, flexible reconfiguration of transceive parameters for communication systems |
US7383457B1 (en) * | 2005-03-23 | 2008-06-03 | Apple Inc. | Adaptive power-reduction mode |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5410711A (en) * | 1991-02-14 | 1995-04-25 | Dell Usa, L.P. | Portable computer with BIOS-independent power management |
EP0676696B1 (en) * | 1994-04-06 | 1999-01-20 | Advanced Micro Devices, Inc. | Parallel port circuits in computer systems |
US5974558A (en) * | 1994-09-02 | 1999-10-26 | Packard Bell Nec | Resume on pen contact |
US5740454A (en) * | 1995-12-20 | 1998-04-14 | Compaq Computer Corporation | Circuit for setting computer system bus signals to predetermined states in low power mode |
US6131167A (en) * | 1997-12-31 | 2000-10-10 | Intel Corporation | Method and apparatus to reduce power consumption on a bus |
US6076128A (en) * | 1998-01-28 | 2000-06-13 | International Business Machines Corp. | Data transfer method between buses, bridge devices for interconnecting buses, and data processing system including multiple buses |
GB2369717B (en) * | 1999-08-25 | 2003-10-15 | Seagate Technology Llc | Intelligent power management of disc drives |
US6694390B1 (en) * | 2000-09-11 | 2004-02-17 | Intel Corporation | Managing bus transaction dependencies |
US7047428B2 (en) * | 2002-01-03 | 2006-05-16 | Broadcom Corporation | Method and apparatus for performing wake on LAN power management |
US6959395B2 (en) * | 2002-06-26 | 2005-10-25 | Broadcom Corporation | Method and apparatus for the conditional enablement of PCI power management |
US7350087B2 (en) * | 2003-03-31 | 2008-03-25 | Intel Corporation | System and method of message-based power management |
US7185212B2 (en) * | 2003-07-21 | 2007-02-27 | Silicon Integrated Systems Corp. | Method for PCI express power management using a PCI PM mechanism in a computer system |
TWI307008B (en) * | 2003-08-14 | 2009-03-01 | Via Tech Inc | Computer system with power management and the method thereof |
CN1246751C (en) * | 2003-09-09 | 2006-03-22 | 威盛电子股份有限公司 | Computer system with power management and its method |
US7337338B2 (en) * | 2004-01-16 | 2008-02-26 | Dell Products L.P. | Information handling system capable of operation in reduced power states |
CN100527725C (en) * | 2004-03-05 | 2009-08-12 | 威盛电子股份有限公司 | Method for regulating power consuming of network interface |
US7469366B1 (en) * | 2005-12-13 | 2008-12-23 | Nvidia Corporation | Measurement of health statistics for a high-speed interface |
-
2005
- 2005-11-01 TW TW094138229A patent/TWI311705B/en active
- 2005-11-02 TW TW094138424A patent/TWI298839B/en active
- 2005-11-07 TW TW094139010A patent/TWI295769B/en active
- 2005-11-17 CN CNB2005101254383A patent/CN100373297C/en active Active
- 2005-11-21 CN CNB200510126728XA patent/CN100353285C/en active Active
- 2005-11-22 CN CNB2005101268117A patent/CN100373298C/en active Active
-
2006
- 2006-01-24 TW TW095102706A patent/TWI325536B/en active
- 2006-03-01 CN CNB2006100198696A patent/CN100390707C/en active Active
- 2006-03-07 TW TW095107634A patent/TWI308695B/en active
- 2006-03-23 US US11/386,754 patent/US20060265611A1/en not_active Abandoned
- 2006-04-14 US US11/403,853 patent/US7647517B2/en active Active
- 2006-04-27 CN CN2006100771141A patent/CN100407107C/en active Active
- 2006-05-09 US US11/429,941 patent/US7849340B2/en active Active
- 2006-05-09 US US11/430,122 patent/US7607029B2/en active Active
- 2006-05-12 US US11/432,356 patent/US7721031B2/en active Active
-
2010
- 2010-01-11 US US12/685,126 patent/US20100115311A1/en not_active Abandoned
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4763296A (en) * | 1985-07-05 | 1988-08-09 | Motorola, Inc. | Watchdog timer |
US4872110A (en) * | 1987-09-03 | 1989-10-03 | Bull Hn Information Systems Inc. | Storage of input/output command timeout and acknowledge responses |
US6122690A (en) * | 1997-06-05 | 2000-09-19 | Mentor Graphics Corporation | On-chip bus architecture that is both processor independent and scalable |
US7287096B2 (en) * | 2001-05-19 | 2007-10-23 | Texas Instruments Incorporated | Method for robust, flexible reconfiguration of transceive parameters for communication systems |
US20030123486A1 (en) * | 2001-12-31 | 2003-07-03 | Globespanvirata Incorporated | System and method for utilizing power management functionality between DSL peers |
US20040128576A1 (en) * | 2002-12-31 | 2004-07-01 | Michael Gutman | Active state link power management |
US7188263B1 (en) * | 2003-05-07 | 2007-03-06 | Nvidia Corporation | Method and apparatus for controlling power state of a multi-lane serial bus link having a plurality of state transition detectors wherein powering down all the state transition detectors except one |
US20040268169A1 (en) * | 2003-06-25 | 2004-12-30 | Bashford Patrick R. | Method and apparatus of automatic power management control for native command queuing Serial ATA device |
US20050097378A1 (en) * | 2003-07-29 | 2005-05-05 | Hwang Andrew S. | Method and system for power management in a gigabit Ethernet chip |
US20050086549A1 (en) * | 2003-10-15 | 2005-04-21 | Solomon Gary A. | Power management over switching fabrics |
US7320080B2 (en) * | 2003-10-15 | 2008-01-15 | Intel Corporation | Power management over switching fabrics |
US7383457B1 (en) * | 2005-03-23 | 2008-06-03 | Apple Inc. | Adaptive power-reduction mode |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9715269B2 (en) * | 2008-09-30 | 2017-07-25 | Intel Corporation | Platform communication protocol |
US20130117492A1 (en) * | 2008-09-30 | 2013-05-09 | Seh W. Kwa | Platform communication protocol |
US20150127874A1 (en) * | 2008-09-30 | 2015-05-07 | Intel Corporation | Platform communication protocol |
US8831666B2 (en) | 2009-06-30 | 2014-09-09 | Intel Corporation | Link power savings with state retention |
US9588575B2 (en) | 2009-06-30 | 2017-03-07 | Intel Corporation | Link power savings with state retention |
US20100330927A1 (en) * | 2009-06-30 | 2010-12-30 | Naveen Cherukuri | Link power savings with state retention |
US10175744B2 (en) | 2009-06-30 | 2019-01-08 | Intel Corporation | Link power savings with state retention |
US10712809B2 (en) | 2009-06-30 | 2020-07-14 | Intel Corporation | Link power savings with state retention |
US20120005506A1 (en) * | 2010-06-30 | 2012-01-05 | Jim Walsh | Systems and methods for implementing reduced power states |
US8407504B2 (en) * | 2010-06-30 | 2013-03-26 | Intel Corporation | Systems and methods for implementing reduced power states |
US9501125B2 (en) | 2010-06-30 | 2016-11-22 | Intel Corporation | Systems and methods for implementing reduced power states |
US9423864B2 (en) | 2011-07-27 | 2016-08-23 | Huawei Technologies Co., Ltd. | PCI express device and link energy management method and device |
US10216814B2 (en) | 2013-05-17 | 2019-02-26 | Oracle International Corporation | Supporting combination of flow based ETL and entity relationship based ETL |
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US20060262839A1 (en) | 2006-11-23 |
TWI308695B (en) | 2009-04-11 |
US20060265612A1 (en) | 2006-11-23 |
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