TWI284925B - High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source - Google Patents

High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source Download PDF

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TWI284925B
TWI284925B TW091137180A TW91137180A TWI284925B TW I284925 B TWI284925 B TW I284925B TW 091137180 A TW091137180 A TW 091137180A TW 91137180 A TW91137180 A TW 91137180A TW I284925 B TWI284925 B TW I284925B
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trench
dopant
region
conductivity type
epitaxial layer
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TW200304170A (en
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Richard A Blanchard
Fwu-Iuan Hshieh
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Gen Semiconductor Inc
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Description

1284925 Α7 Β7 五、發明説明（1 ) 發明所屬技術領域 本發明係相關於半導體裝置，尤其是電力MOSFET (金 氧半導體場效電晶體）裝置。 先前技術 電力MOSFET裝置被使用於諸如自動電力系統、電力 供應、及電力管理應用等應用上。此類裝置在具有低壓降 及高電流爲接通狀態的同時，應維持高電壓爲斷開狀態。 圖1圖解N通道電力MOSFET的典型結構。形成於N + 矽基體2正上方之N外延矽層1包含在裝置中兩MOSFET 胞專用的p本體區5a及6a，與N +源極區7及8。p本體區 5a及6a亦包括深p本體區5b及6b。源極本體電極12延伸 橫過某些外延層1的表面部位以接觸源極及本體區。由延 伸到圖1的上半導體表面之部分N外延矽層1形成兩胞的 N型吸極。吸極電極設置於N +矽基體2的底部。典型爲多 晶矽的絕緣閘電極1 8主要位於裝置本體及部分吸極正上 方’由通常是二氧化矽的電介質薄層與本體及吸極隔開。 當適當正電壓施加於與源極及本體電極相關的閘時，通道 形成在本體區表面的源極及吸極間。 圖示於圖1之習知MOSFET的接通電阻主要由外延層1 的漂移區電阻決定。漂移區電阻依次由外延層1的摻雜及 層厚度決定。但是，爲了增加裝置的破壞電壓，在層厚度 增加的同時必須減少外延層1的摻雜濃度。圖2的曲線20 表示每一單位面積的接通電阻作爲習知Μ0SFET破壞電壓 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） VI.--I -n I--I - (請先閱讀背面之注意事項再填寫本頁)
、1T Φ 經濟部智慧財產局員工消費合作社印製 1284925 A7 B7 五、發明説明（2 ) 的函數。不幸地是，如曲線20所示，當破壞電壓增加4時 ，裝置的接通電阻快速增加。此電阻的快速增加顯示 MOSFET將在較高電壓，尤其是在電壓大於幾百volt時操 作的問題。 圖3圖示設計用於在減低接通電阻的較高電壓中操作 之MOSFET。此MOSFET揭示於1998年IEDM會議記錄第 6 83頁中的第26.2號論文。此MOSFET除了包括自本體區5 及6下方延伸到裝置的漂移區中之p型摻雜區40及42外 •，其他類似圖示於圖1的習知MOSFET。p型摻雜區40及 42界定由η型摻雜柱隔開之漂移區中的柱，而η型摻雜柱 由相鄰Ρ型摻雜區40及42之部分外延層1界定。間隔的 相反摻雜型柱使反向電壓不僅如習知MOSFET般在垂直方 向增強，並且在水平方向亦增強。結果，此裝置可利用減 少外延層1的層厚度及利用增加漂移區的摻雜濃度，達成 如習知裝置中相同反向電壓。圖2的曲線25表示每一單位 面積的接通電阻作爲圖示於圖3之MOSFET破壞電壓的函 數。淸楚地，在較高操作電壓時，此裝置的接通電阻與圖 示於圖1的裝置比較明顯減少，並實質上隨破壞電壓成直 線增加。 圖示於圖3之裝置的操作特性改良係根據電晶體的漂 移區之電荷補償。即漂移區的摻雜明顯增加，如增加一或 多階數値，並由增加相反的摻雜型柱加以平衡額外電荷。 電晶體的閉塞電壓因此保持不變。當裝置在接通狀態時， 電荷補償柱不會促成電流傳導。這些理想的電晶體特性極 — 0 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^^^1 Hal ϋ·— —ij^s It— ml» 士ϋ_ϋ in (請先聞讀背面之注意事項再填寫本頁)
、1T 經濟部智慧財產局員工消費合作社印製 1284925 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（3 ) 依賴在相鄰的相反摻雜型柱間所達成之電荷補償的程度。 不幸地是，由於在製造柱的期間處理參數的控制限制，難 以避免不統一的柱之摻雜劑梯度。例如，遍及柱及基體間 的界面與柱及P本體區間的界面各處之擴散將引起接近那 些界面的柱部位之摻雜劑濃度的改變。 圖示於圖3的結構可由包括多重外延澱積步驟，每一 步驟皆跟著引用適當摻雜劑之處理順序製造。不幸地是， 實施外延澱積步驟非常昂貴，因此製造此結構亦非常昂貴 。另一製造這些裝置的技術圖示於共同審查中的U. S. Appl.期刊號碼09/970,972中，其中溝槽被連續蝕刻成不同 深度。在每一鈾刻步驟後，摻雜劑材料經由溝槽底部被植 入及擴散以形成全體共同作用成類似圖3所見的p型摻雜 區40及42之一連串摻雜區（所謂的”浮動島”）。但是，使 用浮動島技術之裝置的接通電阻無法如使用連續柱之相同 裝置般地低。 因此，最理想地應是提供圖示於圖3之MOSFET結構 的製造方法，此方法在有足夠的處理參數控制使得在裝置 的漂移區之相鄰的相反摻雜型柱中達成高程度的電荷補償 同時，亦只需最少數目的外延澱積步驟使得可較便宜地生 產此結構。 發明內容 根據本發明，提供形成電力半導體裝置的方法。方法 開始於設置第一導電型的基體，然後在基體上形成電壓維 (請先閲讀背面之注意事 J0 項再填‘ 裝-- :寫本頁)
、1T 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1284925 A7 ____B7__ 五、發明説明（4 ) 持區。藉由在基體上澱積第一導電型的外延層形成電壓維 持區。至少一具有第二導電型的摻雜劑之摻雜柱位於外延 層’相鄰溝槽的側牆。使用亦爲摻雜劑源之蝕刻氣體蝕刻 溝槽用以形成摻雜柱。例如，若想要如硼等P型摻雜劑， 可使用BCh當作蝕刻氣體。另外，若需要如磷等η型摻雜 劑’可使用ΡΗ3當作蝕刻氣體。存在於氣體中的摻雜劑與 界定溝槽表面的矽混合。此摻雜劑接著擴散形成圍繞溝槽 的摻雜柱。溝槽充滿如二氧化矽、氮化矽、聚矽、或此類 材料的化合物等絕緣材料。可於摻雜劑擴散形成摻雜柱之 前或之後實施塡滿溝槽的步驟。最後，至少一第二導電型 區形成於電壓維持區正上方以界定其間的接合。 由本發明的方法所形成的電力半導體裝置可從由垂直 DM〇S，V 溝 DMOS，及溝槽 DM〇S MOSFET，IGBT，雙極 電晶體，及二極體所組成的群組中選擇。 根據本發明的另一觀點，設置電力半導體裝置。裝置 包括第一導電型的基體及澱積於基體上的電壓維持區。電 壓維持區包括具有第一導電型及至少一位於外延層的溝槽 之外延層。至少一具有第二導電型的摻雜劑之摻雜柱位於 外延層，相鄰溝槽的側牆。自藉由用於蝕刻溝槽之氣體所 引入溝槽表面的摻雜劑，接著摻雜劑擴散到外延層中以形 成柱。亦設置大體上塡充溝槽之塡充材料。至少一第二導 電區澱積於電壓維持區正上方以界定其間的接合。 •圖示簡單說明 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) •裝· 訂 經濟部智慧財產局員工消費合作社印製 % 1284925 A7 B7 五、發明説明（5 ) 圖1圖示習知電力MOSFET結構的剖面圖。 圖2圖示每一單位面積的接通電阻作爲習知電力 MOSFET破壞電壓的函數。 圖3圖示包括具有位於本體區下方之P型摻雜劑的柱 之電壓維持區，並設計用於藉由比圖1所描晝的結構在相 同電壓中較低之每一單位面積的接通電阻加以操作的 MOSFET 結構。 圖4(a)-4(b)圖示用於製造根據本發明所構造的電壓維 持區之示範性處理步驟的順序。 圖5圖示根據本發明所構造的MOSFET之剖面圖。 主要元件對照表 1 : N外延矽層 2 : N +矽基體 5 :本體區 6 ··本體區 5a : p本體區 ' 5b ··深p本體區 6 a : ρ本體區 6b :深p本體區 7 : N +源極區 8 : N +源極區 12 :源極本體電極 1 8 :絕緣閘電極 ____—-9--- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） mi —^ϋ HB^l -麵 _ —fan mj n^i ϋ (請先閲讀背面之注意事項再填寫本頁) 、1Τ 經濟部智慧財產局員工消費合作社印製 1284925 A7 ____B7_ 五、發明説明（6 ) 20 :曲線 2 5 :曲線 40 : p型摻雜區 42 : p型摻雜區 501 : N型摻雜外延層 502 : N +摻雜基體 5 10 :矽層 512 :摻雜柱 520 :溝槽 實施方式 根據本發明，形成半導體裝置的電壓維持層之P型柱 的方法將說明如下。首先，在將形成裝置的電壓維持區之 外延層蝕刻一或多個溝槽。每一溝槽位於其所放置的摻雜 柱中間。藉由存在於用以蝕刻溝槽的氣體中之摻雜劑形成 摻雜柱。由於實施蝕刻的氣體能量，存在於蝕刻氣體的摻 雜劑種類與位於界定溝槽之表面的外延層部位混合。摻雜 劑種類擴散到外延層的最後深度以形成摻雜柱。溝槽充滿 不會對裝置特性有不利影響之材料。使用於塡滿溝槽的材 料之示範性材料包括未摻雜的聚矽、如二氧化矽或氮化矽 • 等電介質，或其他材料及材料的化合物。此處理順序形成 與圖3所描晝的那些類似之連續的摻雜柱。 根據圖解於圖4(a)-4(b)的下列示範性步驟可製造圖示 於圖3的電力半導體裝置。 ----^W——-- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝 訂 經濟部智慧財產局員工消費合作社印製 · - - i—- 1284925 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（7 ) 首先，在習知N +摻雜基體502上發展N型摻雜外延層 501。外延層501爲具有5-40 ohm-cm電阻率的400-800 V裝 置專用的15-50微米典型厚度。接著，藉由以電介質層覆蓋 外延層501表面形成電介質掩蔽層，然後習知上曝光及做 • 成模型以留下界定溝槽520的位置之掩蔽部位。藉由活性 離子蝕刻法經過掩蔽開口乾蝕刻溝槽520到範圍例如爲10-45微米的最初深度。另外，可使用諸如電漿蝕刻法及離子 束銑削法等其他乾蝕刻技術。使用其亦爲摻雜劑源之蝕刻 氣體蝕刻溝槽以形成摻雜柱。例如，如圖4(a)，若想要如 硼等P型摻雜劑，可使用BC13當作蝕刻氣體。另外，若需 要如磷等η型摻雜劑，可使用PH3當作蝕刻氣體。存在於 氣體中的摻雜劑與界定溝槽520表面的矽層510混合。 若需要的話，每一溝槽的側牆可以是平滑的。首先， 使用乾化學鈾刻自溝槽側牆去除氧化物薄層（典型大約 500- 1000A)以排除因活性離子蝕刻處理所引起的破壞。接 著，在溝槽520正上方發展具犧牲性質的二氧化矽層。藉 由緩衝氧化物蝕刻或HF蝕刻去除此犧牲性質層，使得結果 的溝槽側牆盡可能平滑。 在圖4(b)中，溝槽充滿不會對最後裝置特性有不利影 琴之絕緣材料，如二氧化矽、氮化矽、未摻雜的聚矽、或 此類材料的化合物等。在矽層5 10的摻雜劑種類擴散到外 延層501的最後深度以形成摻雜柱512。可於摻雜劑擴散形 成摻雜柱512之前或之後實施塡滿溝槽的步驟。通常，應 .選定溝槽深度、摻雜劑劑量、及擴散處理的量及持續時間 本紙張尺度適用中國國家標準（CNS )八4規格（21 〇 χ 297公釐） (請先閱讀背面之注意事項 裝-- -項再填寫本頁) 訂 1284925 A7 -- _ B7 五、發明説明（8 ) 以達成想要的電荷補償。最後，整平結構表面準備形成電 力半導體裝置的剩餘區域。 (請先閱讀背面之注意事項再填寫本頁} 產生描畫於圖4(b)的結構之上述處理步驟順序設置在 其上可製造任意數目的不同電力半導體裝置之具有p型摻 雜柱的電壓維持層。如上述，此類電力半導體裝置包括垂 直 DM〇S，V 溝 DMOS，及溝槽 DM〇S MOSFET，IGBTs，及 其他MOS閘裝置。例如，圖3圖示包括具有根據本發明原 則所構造的摻雜柱之電壓維持層的MOSFET例子。應留意 雖然圖4圖示用於形成摻雜柱的單一溝槽，但本發明亦考 慮到具有單一或多數溝槽以形成任意數目的摻雜柱之電壓 維持區。例如，當適當減少裝置的接通電阻時，單一摻雜 柱或多數摻雜柱可位於閘中央的下方或其他位置。 經濟部智慧財產局員工消費合作社印製 一旦已形成如圖4的電壓維持區及單一摻雜柱或多數 摻雜柱時，可利用下述方式形成圖示於圖3的MOSFET。在 形成活性區掩蔽之後發展閘氧化物。接著，澱積、摻雜、 及氧化多晶砂層。然後掩蔽聚政層形成閘區。使用臂知掩 蔽、植入、及擴散步驟形成P +摻雜深本體區5b及6b。例 如，大約lx 1014到5x 1015/cm2劑量的硼以20到200 KeV植 入P +摻雜深本體區。以相同方式形成淺本體區5a及6a。以 20到100 KeV的能量植入此區的劑量爲lx 1〇13到5x 1014/cm2。 接著，使用光阻鈾刻掩蔽處理法形成界定源極區7及8 之圖形掩蔽層。然後藉由植入及擴散處理形成源極區7及8 。例如，以濃度典型爲2x 1015到1.2x 1016/cm2範圍的砷以 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） 42- 1284925 A7 B7 五、發明説明（9 ) (請先聞讀背面之注意事項再填寫本頁) 20到100 KeV植入源極區。植入後，砷擴散到大約〇·5到 2·〇微米的深度。本體區的深度典型爲大約ι-3微米範圍， (右存在的g舌）Ρ+慘雜涂本體區稍微深一^些。藉由触刻氧 化物層以在其前表面上形成接觸開口之習知方式完成DMOS 電晶體。亦澱積及掩蔽金屬化層以界定源極本體及閘電極 。並且’使用墊片掩蔽以界定墊片接觸。最後吸極接觸層 形成於基體的底表面上，產生圖示於圖5的裝置。 應留意雖然揭不製造電力MOSFET的特定處理順序， 但只要在本發明的範圍中可使用其他處理順序。例如，可 在界定閘區之前形成P +摻雜深本體區。亦可以在形成溝槽 之前形成P +摻雜深本體區。在一些DMOS結構中，p +摻雜 深本體區比P摻雜本體區淺，或在某些例子中，甚至沒有 P +摻雜本體區。 經濟部智慧財產局員工消費合作社印製 雖然此文中已特別圖解及說明各種實施例，但應明白 本發明的修正及變化在無違背本發明的精神及範圍之下， 應涵蓋於上述原則中並在附錄於後的申請專利範圍條款中 。例如，以顛倒此文所說明之各種半導體區的導電性的方 式設置根據本發明的電力半導體裝置。而且，雖然使用垂 直DMOS電晶體圖解根據本發明製造裝置所需的示範性步 驟，但亦可遵循這些原則製造其他DMOS FETs及其他諸如 二極體、雙極電晶體、電力JFETs、IGBTs、MCTs、及其他 M〇S閘電力裝置等其他電力半導體裝置。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 4^

Claims (1)

1284925
A8 B8 C8 D8 六、申請專利範圍 附件2 A : 第9 1 1 3 7 1 80號專利申請案 中文申請專利範圍替換本 民國96年4月27日修正 I 一種形成電力半導體裝置的方法，包含步驟如下： A.:設置第一或第二導電型的基體； B 在該基體上形成電壓維持區，步驟如下： 1. :在基體上澱積外延層，該外延層具有第一 導電型； 2. :藉由具有第二導電型的摻雜劑種類之蝕刻 氣體在外延層蝕刻至少一溝槽以在界定溝 槽牆之外延層部位形成摻雜表面層； 3 .:位於該摻雜表面層的摻雜劑種類更進一步 擴散到外延層中以在相鄰溝槽及外延層中 形成摻雜外延區； 4.:在該溝槽中澱積塡充材料以大體上塡滿該 溝槽；及 C·:在該電壓維持區正上方形成至少一該第二導電 型區以界定其間的接合。 2. 如申請專利範圍第1項之方法，其中在擴散摻雜劑 種類的步驟之前執行澱積塡充材料的步驟。 3. 如申請專利範圍第1項之方法，其中在擴散摻雜劑 種類的步驟之後執行澱積塡充材料的步驟。 4. 如申請專利範圍第1項之方法，其中步驟（C)更包 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ----------^------1T------^ (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1284925 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 括步驟如下： 在閘電介質區上方形成閘導體； 在外延層形成第一及第二本體區以界定其間的漂移區 ’該本體區具有第二導電型； 各自在桌一及第一本體區形成第〜導電型的第一及第 二源極區。 如申請專利範圍第丨項之方法，其中塡充溝槽的該 材料爲未慘雑多晶砂。 6. 如申請專利範圍第丨項之方法，其中塡充溝槽的該 材料爲電介質材料。 7. 如申請專利範圍第6項之方法，其中該電介質材料 爲二氧化矽。 8. 如申請專利範圍第6項之方法，其中該電介質材料 爲氮化Ϊ夕。 1㈣if專·圍第丨項之方法，其中該摻雜劑種類 爲硼。 10.如申請專利範圍第9項之方法，其中該蝕刻氣體 爲 BC13 〇 Η.如申請專利範圍第〗項之方法，其中該摻雜劑種 類爲磷。 1 2 .如申g靑專利範圍第〗i項之方法，其中該鈾刻氣體 爲PH” 13*如申請專利範圍第4項之方法，其中該本體區包 括涂本體區。 ---------^------1T------^ (請先閲讀背面之注意事項再填寫本頁)
1284925 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 ~、申請專利範圍 14.如申請專利範圍第1項之方法，其中藉由設置界 定至少一溝槽之掩蔽層，並蝕刻由掩蔽層所界定的溝槽以 形成該溝槽。 1 5 .如申請專利範圍第1項之方法，其中藉由活性離 子蝕刻法執行触刻步驟。 16. 如申請專利範圍第4項之方法，其中藉由將摻雜 劑植入及擴散到基體中形成該本體區。 17. 如申請專利範圍第1項之方法，其中該電力半導 體裝置從由垂直DMOS，V溝DMOS，及溝槽 DMOS MOSFET，IGBT，及雙極電晶體所組成的群組中選擇。 18. —種電力半導體裝置，包含： 第一或第二導電型的基體； 澱積於該基體上的電壓維持區，該電壓維持區包括： 具有第一導電型的外延層； 至少一位於該外延層的溝槽； 至少一具有第二導電型的摻雜劑之摻雜柱，自藉由用 於形成溝槽之蝕刻氣體所引入溝槽表面並擴散到外延層的 摻雜劑形成該柱； 大體上塡滿該溝槽的塡充材料：及 至少一澱積於該電壓維持區正上方以界定其間的接合 之該第二導電區。 19·如申請專利範圍第18項之裝置，其中該至少一區 更包括： 閘電介質及澱積在該閘電介質上方之閘導體； 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210Χ297公釐） -3- U----------參------ίτ------0 (請先閱·«背面之注意事項再填窝本頁) 1284925 A8 B8 C8 D8 六、申請專利範圍 位於外延層以界定其間的漂移區之第一及第二本體區 ’該本體區具有第二導電型；及 各自位於第一及第二本體區之第一導電型的第一及第 ^-- (請先閲讀背面之注意事項再填寫本頁) 訂 線 經濟部智慧財產局員工消費合作社印製 二源極區。 20.如申請專利範圍第 該材料爲未摻雜多晶砂。 2 1.如申請專利範圍第 該材料爲電介質材料。 22.如申請專利範圍第 料爲二氧化砂。 23·如申請專利範圍第 料爲氮化矽。 24·如申請專利範圍第 硼。 2 5 .如申請專利範圍第 爲 BC13 〇 26. 如申請專利範圍第 磷。 27. 如申請專利範圍第 爲 PH3。 28. 如申請專利範圍第 括深本體區。 29. 如申請專利範圍第 體裝置從由垂直 DMOS， 1 8項之裝置，其中塡充溝槽的 1 8項之裝置，其中塡充溝槽的 21項之裝置，其中該電介質材 21項之裝置：其中該電介質材 I8項之裝置，其中該摻雜劑爲 24項之裝置，其中該蝕刻氣體 1 8項之裝置，其中該摻雜劑爲 26項之裝置，其中該蝕刻氣體 I9項之裝置，其中該本體區包 1S項之裝置，其中該電力半導 V溝DMOS，及溝槽DMOS 本紙張尺度適用中國國家操準（CNS ) A4規格（210X2S»7公釐） 1284925 aj C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 MOSFET，IGBT，及雙極電晶體所組成的群組中選擇。 J----------^-- (請先聞讀背面之注意事項再填寫本頁) 訂 線- 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） -5 -
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