TWI282664B - Method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL) - Google Patents

Method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL) Download PDF

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Publication number
TWI282664B
TWI282664B TW091134896A TW91134896A TWI282664B TW I282664 B TWI282664 B TW I282664B TW 091134896 A TW091134896 A TW 091134896A TW 91134896 A TW91134896 A TW 91134896A TW I282664 B TWI282664 B TW I282664B
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TW
Taiwan
Prior art keywords
delay
circuit
signal
clock
delay line
Prior art date
Application number
TW091134896A
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English (en)
Chinese (zh)
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TW200409462A (en
Inventor
Jinn-Shyan Wang
Yi-Ming Wang
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Nat Univ Chung Cheng
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Priority to TW091134896A priority Critical patent/TWI282664B/zh
Priority to JP2002373899A priority patent/JP3849871B2/ja
Publication of TW200409462A publication Critical patent/TW200409462A/zh
Application granted granted Critical
Publication of TWI282664B publication Critical patent/TWI282664B/zh

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  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW091134896A 2002-11-29 2002-11-29 Method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL) TWI282664B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW091134896A TWI282664B (en) 2002-11-29 2002-11-29 Method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL)
JP2002373899A JP3849871B2 (ja) 2002-11-29 2002-12-25 単一ディレイ線及び最小化工作ディレイセルを有するディレイロック回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091134896A TWI282664B (en) 2002-11-29 2002-11-29 Method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL)

Publications (2)

Publication Number Publication Date
TW200409462A TW200409462A (en) 2004-06-01
TWI282664B true TWI282664B (en) 2007-06-11

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TW091134896A TWI282664B (en) 2002-11-29 2002-11-29 Method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL)

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JP (1) JP3849871B2 (ja)
TW (1) TWI282664B (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100689837B1 (ko) 2005-08-02 2007-03-08 삼성전자주식회사 지연 동기 회로

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Publication number Publication date
JP2004187245A (ja) 2004-07-02
JP3849871B2 (ja) 2006-11-22
TW200409462A (en) 2004-06-01

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