TWI324779B - Delay locked loop circuit and method for generating a dll clock - Google Patents

Description

1324779 IX. DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to a delay locked loop (DLL) circuit for synchronous DR AM; and more particularly, to a low power operation for a semiconductor device A DLL circuit that performs stable operation in the power saving mode. [Prior Art] A synchronous semiconductor 5 memory device such as a dual data rate synchronous DRAM (DDR SDRAM) is implemented using an internal clock signal that is locked in synchronization with an external clock signal input from an external device such as a memory controller. Data transfer with external devices. The time synchronization between the reference clock signal and the data is important for the stable transfer of data between the memory device and the memory controller. In order to transmit data steadily, the data should be accurately located at the edge or center of the clock by compensating for the delay time inevitably due to the time difference between the data transmission of each component and the data being loaded into the bus. The clock synchronization circuit for compensating for the delay time is a phase locked loop (pLL) or

Delay locked loop (DLL). If the external clock signal is different in frequency from the internal clock signal, then the multiplier function must be used. Therefore, ριχ is mainly used in this case. Conversely, if the external clock signal is equal in frequency to the internal clock signal: then the DLI^DLL circuit is used to compensate for the transmission of the clock signal through each element to the data wheel terminal inside the semiconductor memory device. The clock delay component that occurs is used to generate an internal clock signal. Therefore, the shame circuit synchronizes the clock signal used for the final input/output data with the external clock signal. Compared with the PLL circuit, the DLL circuit has the advantage that the noise is low and the basin can be implemented in a small area t. Therefore, the DLL circuit is usually used as a synchronization circuit in the semiconductor memory JI2670.doc device. Among the different types of DLLs, recent techniques provide a DLL circuit that can be controlled by the register to reduce the time it takes to lock the first clock. The DLL circuit of the register control has a register capable of storing a lock delay value, and the DLL circuit stores the lock delay value in the register when the power is interrupted, and loads and stores it in the temporary storage when the power is turned on again. The lock delay value ' in the device so that the lock delay value is immediately used to lock the clock. Figure 1 is a timing loop β DLL circuit for the basic operation of a typical delay locked loop (DLL) circuit to receive an external clock signal and compensate for the delay of the internal clock of the dram [DLL circuit ensures the output signal of the DRAM and the external clock The signals are in phase. When the external clock has the same phase as the output of the DRAM, the data can be transferred to the chip set without error. 2 is a block diagram showing a known DLL circuit. Figure 2 is based on a DLL circuit controlled by a scratchpad. The DLL circuit includes a clock buffer 1〇, a power saving mode controller 20, a clock divider 25, a phase comparator 3〇, a delay controller 4G, a delay line 5〇, and a dummy delay line 6 〇, and - delayed replication model 7〇. The DLL clock signal D11_CLK outputted from the DLL circuit is transmitted to the output buffer 9 via the pulse signal line 80 to control the output timing of the data. The clock buffer 1 产生 generates the internal clock IDVD CLK by connecting the D-be clock signal CLK and the external clock-inhibiting signal CLKB to the slave's '1' and 1''. The j mode switch 20 turns off the clock hacking 10 when the DRAM enters the power saving mode. For low-power operation of the ship (10) without read/write operation, 112670.doc 1324779, the DRAM enters the power-saving mode when the clock enable signal CKE becomes the logic level 'LOW'. At this time, since the clock buffer 1 does not generate the internal clock signal IDVD_CLK, the clock buffer 10 is turned off to save the current state of the DLL circuit. The clock divider 25 generates the DLL source clock signal DVD_CLK by dividing the internal clock signal IDVD_CLK, and generates the reference clock signal REF_CLK by using the internal clock signal IDVD_CLK. Generally, to reduce the power consumption of the DLL circuit, the frequency of the externally applied clock is lowered via the clock divider 25 to generate the DLL source clock signal DVD_CLK. The phase comparator 30 detects the phase difference between the input clock and the output clock of the DLL circuit by comparing the phases of the input and output clocks with each other. Therefore, the reference clock signal REF_CLK passing through the clock buffer 10 and the feedback clock signal FB_CLK fed back through the internal circuit of the DLL circuit are compared with each other at the phase comparator 30. The phase comparator 30 controls the delay controller 40 based on the comparison result. The delay controller 40 is configured with a logic circuit (for determining the input path of the delay line 50) and a bidirectional shift register (for the direction of the shift path). The shift register that receives the four input signals and performs a shift operation has the maximum or minimum delay by reaching the initial input condition of the rightmost signal or the leftmost signal at the logic level "HIGH". The signal input to the shift register has two right shift signals and two left shift signals. For the shift operation, the two signals in the logic level "HIGH" should not overlap each other. The delay line 50 delays the phase of the DLL source clock signal 112670.doc K output from the clock divider 25 The delay amount is determined by the phase comparator 3. The delay line 5〇2 determines the delay path under the control of the delay controller 40, and the delay path confirms the phase delay. The delay line 5G includes a plurality of unit delays W that are axially coupled to each other. Each of the 4-bit delay units includes two "gates" connected in series with each other. The inputs of each of the unit delay units are connected in a one-to-one mapping manner to the shift registers in the delay controller 4''. The output of the shift register becomes the logic level "HIGH" is located in the area for inputting the clock of the traveling flux buffer ^ 1G 在 ^ in the dirty SDRAMf, the delay line 5 Constructed with two delay lines, the -1 delay line is used to raise the clock, and the other strip is used to lower the clock, so that the rising edge and the falling edge are treated by the same -# Duty ratio distortion. The sinus delay line 60 is a delay line for generating a feedback clock signal FB_CLK applied to the phase comparator 3A. The dummy delay line (6) is identical to the delay line 50 described above. The delayed replica model 70 is a circuit for modeling the delay factor for modeling the delay factor after the external clock input to the wafer and before the input to the delay line 5〇, and when outputting the delay line 5〇 from the chip output Other delay factors before the pulse. The precise delay factor determines the degradation value in the function of the DLL circuit. The delayed copy model 70 models the clock buffer, DLL clock driver, R/F divider, and output buffer as they are. The clock signal line 80 is a path for coupling the DLL clock signal DLL_CLK of the DLL circuit to the output buffer 90. 112670.doc 1324779 The output buffer 90 receives the data from the memory core and outputs the data to the data wheel out of the DLL circuit DLL CLK_CLK. Figure 3 is a timing diagram illustrating the operation of the DLL of Figure 2. Figure.

When entering the power saving mode, the clock enable signal CKE changes from the logic level "HIGH" to the logic level "L0W, at this time, the DLL circuit stops performing the phase update operation to save the current state, and stores the previously locked information. To enter the frozen state. In this paper, the phase update operation means comparing the phase of the feedback clock signal FB_CLK of the dll circuit with the phase of the internal clock signal REF_CLK to be determined and continuously tracked. The east node state means a state in which the previously locked information has been stored and the phase is not further updated. In the precharge power saving mode, the time period of the power saving mode t is in the range of a minimum of three clocks to a maximum of 7.8 μ3. During this time, the clock buffer 1Q is turned off by the power saving mode controller 2G so that the muscle clock signal DLL_CLK of the rainbow circuit is not generated. When the power saving mode is maintained for a long period of time, the minimum is shown in FIG. 3CLK to a maximum of 7.8fXS (the phase is not updated in the inter-segment), depending on the changes in the environment of the semiconductor device, such as external temperature changes, the current lock of the muscle circuit may be compared with the previous information before the power saving mode different. When the power saving mode is exited under this condition, it means that the information of the #pre-locking and the information of the previous locking do not match each other, and the information of the CLK-CLK of the hunger circuit is compared with the target clock to be locked in phase. different. Therefore, since the phase of the external clock signal and the phase-break signal of the DLL circuit are not zero, it is difficult to accurately transfer data to the DRAM/receive data from the DRAM. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a delay locked loop (DLL) circuit for a semiconductor memory device for preventing a semiconductor device from being used in a power saving mode for a relatively long period of time. A lock failure that occurs due to a change in the environment (such as an external temperature). According to an aspect of the present invention, a DLL of a memory device having a normal mode and a power saving mode is provided, comprising: a clock buffer for buffering an external clock signal to output an internal clock a painful electrical mode control H' for generating a power save mode control signal in response to the -clock enable signal to define the normal mode or the power save mode; a source clock generation unit for receiving the The internal clock signal generates a DLL source clock signal under the power saving mode control signal control; and a phase update list is used to perform a phase update operation based on the DLL source clock signal to output a dll Pulse signal. According to another aspect of the present invention, there is provided a method of generating a DLL clock 4 of a memory device having a normal mode and a power saving mode delay locked loop, comprising: buffering an external clock Generating an internal clock signal; generating a second frequency division clock signal by dividing the internal clock signal; generating a second frequency division clock signal based on the first frequency division clock signal; In the normal mode, a DLL phase update operation is performed based on the first frequency-divided clock signal; and a DLL phase update operation is performed based on the second frequency-divided clock signal in the power-saving mode. 670 2670.doc 1324779 [Embodiment] A delay locked loop (DLL) circuit according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. 4 is a block diagram of a DLL circuit in accordance with the present invention. The DLL circuit 600 includes a clock buffer 100, a power saving mode controller 200, a source clock generating unit 300, and a phase updating unit 400. The clock buffer 100 receives and buffers the external clock signal CLK and the external clock disable signal CLKB to output the buffered signal as the internal clock signal IDVD_CLK. The power saving mode controller 200 generates a power saving mode control signal CTRL in response to the clock enable signal CKE, the signal CTRL having information showing whether to enter the power saving mode or the normal mode. The source clock generation unit 300 generates a DLL source clock signal DVD_CLK based on a selected portion of the internal clock signal IDVD_CLK in response to the power saving mode control signal CTRL indicating the power saving mode or the normal mode, and receives the source voltage VDD to be based on the internal The clock signal IDVD_CLK generates a reference clock signal REF_CLK. The phase update unit 400 performs a phase update operation to output a DLL clock signal DLL_CLK based on the source clock signal DVD_CLK. The phase update unit 400 is a DLL controlled by a register, and includes a delay line 410, a dummy delay line 420, a delay controller 430, a delay replica model 440, and a phase comparator 450. The delay line 410 receives the DLL source clock signal DVD_CLK of the source clock generation unit 300 to delay the phase of the DLL source clock signal DVD_CLK by a predetermined time of 112670.doc 1324779. The dummy delay line 420 is substantially coincident with the delay line 41 0 . The delay replica model 440 outputs the feedback clock signal FB__CLK by modeling the output signal ' of the dummy delay line 420 with the delay factor of the external clock signal CLK and the external clock disable signal CLKB in the semiconductor memory device. The phase comparator 450 detects the phase difference between the reference clock signal REF_CLK of the source clock generation unit 300 and the feedback clock signal FB_CLK of the delayed replica model 440. The delay controller 430 controls the delay amounts of the delay line 410 and the dummy delay line 420 based on the output signal of the phase comparator 450. The DLL clock signal DLL_CLK of the DLL circuit 600 is transmitted via a clock signal line 700 to an output buffer 800 to control the output timing of the data. As described above, in the present invention, the clock buffer 1 〇〇 controls the source clock generation to generate a single 300 ' regardless of the power saving mode control signal cTRL. That is, the clock buffer 100 continuously supplies the internal clock signal 11) to the source clock generation unit 300, and the state of the semiconductor memory device (such as the power saving mode and the normal state). In addition, in the present invention, the source clock generation unit 300 generates a DLL source clock signal DVD_CLK for performing at least one phase update operation in the power saving mode. Hereinafter, source clock generation is described in detail. The operation of the unit 3 is a block diagram of the source clock generation unit 300 according to the embodiment of the present invention shown in FIG. 4; and FIGS. 6A and 6B are the second clock divider shown in FIG. Detailed circuit diagram. The scoop is as shown in the following description. The source clock generation unit 3 according to the first embodiment of the present invention includes first and second clock demultiplexers 31A and 32A, a selection unit, and a The operation logic unit 340, and the _ reference clock generation unit 35. n2670.d〇c 12 1324779 The first clock divider 310 generates the first frequency division clock by dividing the internal clock signal ID VD_CLK. Signal CLK_D1 to set the duration of the phase update operation in normal mode The second clock frequency divider 32 产生 generates a second frequency-divided clock signal CLK_D2 by dividing the first frequency-divided clock signal CLK_D1 to set the duration of the phase update operation in the power-saving mode. The selecting unit 330 selects one of the first and second frequency-divided clock signals CLK_D1 and CLK_D2 based on the power-saving mode control signal CTRL, thereby outputting the selected signal as the selected clock signal DVD_OUT. The clock signal DVD_OUT and the internal clock signal IDVD_CLK are combined to output a DLL source clock signal DVD_CLK. The reference clock generation unit 350 generates by performing an AND operation of the internal clock signal IDVD_CLK and the source voltage VDD. Referring to FIG. 6A, the second clock divider 320 may include a single divide by 2 clock divider or a single divide by 2n clock divider. Here, η is a positive integer. 6Β, the second clock divider 320 may include a plurality of unit clock dividers 320_1 to 320_Ν and a plurality of fuse units 325_1 to 325. A plurality of unit clock dividers to 32〇_Ν series connection' For generating a plurality of clocks having different unit clocks (eg, CLK_D2_1 to CLK_D2__N); and the plurality of fuse units 325_1 to 325-N are selected by fusing the selected fuses to select the output of the plurality of unit dividers One of the veins. In the present invention, it is possible to replace the fuse by using a plurality of metal selection processing units (cutting 〇pti〇n pr〇cessi, % 仙(1)) in the processing period 112670.doc 1324779 Units 325-1 through 325_N construct a second clock divider and y 320. Typically, a 5' semiconductor memory device has a power saving mode period depending on its specifications and the external environment. In a first embodiment of the present invention, a second frequency-divided clock signal for setting a portion of a phase update operation in a power saving mode

CLK_D2 is selected from a plurality of unit clocks (ie, CLK_D2J to CLK_D2 - N). Considering that the power-saving mode period varies with the environment, the second frequency-divided clock signal CLK_D2 is set after the test. Therefore, the corresponding fuses of the fuse units 325-1 to 325-N respond to the second frequency-divided clock. The signal CLK_D2 is turned on. As described above, according to the first embodiment of the present invention, the source clock signal dvd_clk is selectively generated based on the second frequency-divided clock signal CLK_D2 for setting the phase update portion in the power saving mode. Herein, the second frequency-divided clock signal CLK_D2 is selected according to the power saving mode.

Fig. 7 is a timing chart for the operation of the source clock generating unit according to the first embodiment of the present invention shown in Fig. 5. The first clock divider 31 receives the internal clock signal IDVD_CLK and divides it by 2, thereby outputting the frequency-divided clock signal as the first-divided clock signal CLKJD1. The second clock divider 32() receives the first divided clock signal CLK_DL· and divides it by using a plurality of unit frequency dividers _ n. Therefore, the output of the plurality of unit frequency dividers 32G i to n is output as the second frequency division clock signal CLK-02 having different unit clocks (that is, CLK_D2 - UClk Μ n). Different unit clocks H2670.doc 1324779 raw unit 350, a clock switching unit 360 and a clock demultiplexer 370. The clock divider 370 generates the first converted clock signal CLK_T1 by dividing the internal clock signal IDVD_CLK to set the duration of the phase update operation in the normal mode. The clock conversion unit 360 generates the second converted clock signal CLK_T2 by converting the first converted clock signal CLK_T1 to set the duration of the phase update operation in the power saving mode. The selecting unit 330 selects one of the first and second switching clock signals CLK_T1 and CLK_T2 based on the power saving mode control signal CTRL, thereby outputting the selected signal as the selection clock signal DVD_OUT. The operation logic unit 340 logically combines and selects the clock signal DVD_OUT and the internal clock signal IDVD_CLK to output the DLL source clock signal DVD_CLK. The reference clock generation unit 350 generates the reference clock signal REF_CLK by performing an AND operation of the internal clock signal IDVD_CLK and the source voltage VDD. Referring to FIG. 11A, the clock conversion unit 360 can include a single clock converter that periodically selects a portion of the first converted clock signal CLK_T1 to output the selected clock signal as the second converted clock signal CLK_T2. . In addition, referring to FIG. 11B, the clock conversion unit 360 may include a plurality of unit clock converters 360_1 to 360_N and a plurality of fuse units 365_1 to 3 65_N. A plurality of unit clock converters 360_1 to 360_N are connected in series to generate a plurality of clocks having different unit clocks (eg, CLK_T2_1 to CLK_T2_N); and a plurality of fuse units 365_1 to 365_N are selected by fuse selection 112670.doc 1324779 The one of the output clocks of the unit clock converters. In the present invention, it is possible to construct a clock switching unit by using a plurality of metal selection treatments for a single generation (four) silk early % 365 - u 365 - 。. The half (four) (four) μ set has different power saving mode cycles due to its specifications. In the second embodiment of the present invention, a new operation for =Τ2 is selected among the complex values V CL, T2-1 to CLK'T2-N)

Article 1 T2. Considering that the power saving mode period varies with the environment, the second switching clock signal CLK_Τ2 is set after the test. Therefore, the pair of materials, such as i to 365-N, is in response to the second conversion clock signal, and is used in the source clock generation unit 300 according to the first embodiment of the present invention. Timing diagram of the operation. As shown, the clock divider 370 receives the internal clock signal idvd-clk and performs frequency division, thereby outputting the frequency-divided clock signal as the first conversion clock signal CLK_T2. The clock conversion unit 36 receives the first conversion clock signal CLK_T1 and converts the first conversion clock signal CLKJT1 by using a plurality of unit clock converters 36〇j to 36〇-N. Therefore, the output of the plurality of unit clock converters is output as the second converted clock signal CLKJT2 having different unit clocks (that is, 〇匕反_丁2_1 to (:1^72-\). Medium, *cell clock CLK_Μ" to CLK_T2_N have different clock values 'meaning, 〗 〖n. Assume that the second signal CLK is in the second transition clock with different unit clocks (meaning CLK_T2_1 to CLK_T2_N) In T2, 'the third unit clock CLK_T2_2 outputted by the second unit clock converter 360_2 as shown in FIG. 11B is converted into one third of the frequency of the first conversion clock signal 112670.doc No. 1324779 CLK_T1. The portion of the phase update operation selected in the power saving mode is selected. The selecting unit 330 selects the second cell clock CLK_T2_2 as the selected clock signal DVD_OUT during the power saving mode. The arithmetic logic unit 340 logically combines the periods of the power saving mode. The clock signal DVD_OUT (ie, the second clock value CLK_T2_2) and the internal clock signal IDVD_CLK are selected to output a DLL source clock signal DVD_CLK suitable for different parts of the power saving mode. At this time, referring to FIG. 12, when enabled First The DLL source clock signal DVD_CLK has a valid value continuously for a short period of time at the cell clock CLK_T2_2. Therefore, it is possible to perform the phase update operation efficiently. In addition, it is possible to use the fuse unit 365_1 to 365_:^ or metal. The processing unit is selected to select one of the second converted clock signals CLK_T2 having different unit clocks (ie, CLK_T2_1 to CLK_T2_N). In the second embodiment of the present invention, the arithmetic logic unit of the source clock generating unit 300 The structure of the 340 and reference clock generation unit 350 is the same as that of the first embodiment shown in FIGS. 8 and 9. As described above, according to the second embodiment of the present invention, the DLL source clock signal DVD_CLK is selected by the A conversion clock signal CLK_T1 and one of the second conversion clock signals CLK_T2 having different unit clocks (that is, CLK_T2_1 to CLK_T2_N) are generated. At this time, the first and second conversion clock signals CLK_Tl And each of CLK_T2 has the same effective portion and different periods. Therefore, it is possible to provide a time period suitable for the normal mode or with the semiconductor memory device. The DLL source clock of the electrical mode 112670.doc -19-signal dvd_CLk, to ensure stable operation of the semiconductor memory device with low power operation τ. Figures 13A and 13B are diagrams for describing the application according to the first and second embodiments of the present invention. The timing diagram of the simulation result of the source clock generation unit. As shown in Fig. 13A, according to the first sound, the 音 钿 ' ' ' reference clock signal REF_CLK and DLL source clock signal DVD - CLK β The intervening lag is about! 62fs. In addition, as shown in FIG. 13A, according to the second embodiment, when referring to

The time between the pulse signal REF_CLK and the DLL source clock signal DVD CLK is approximately 322 fs. Therefore, each time lag of the first and second embodiments is practically zero. Hereinafter, referring to Figures 4 through 9, a method for generating a dll clock signal in a synchronous memory device having a normal mode or a power saving mode according to the first embodiment of the present invention will be described.

First, the clock buffer 100 generates the internal clock signal IDVD_CLK by receiving the external clock signal CLK and the external clock disable signal CLKB; the first clock divider 31 of the source clock generation unit 300 is internally The clock signal IDVD_CLK is divided to generate a first divided clock signal CLK_D1 for setting a portion of the phase update operation in the normal mode. The second clock divider 320 divides the first divided clock signal CLK-D1 to generate a second divided clock signal CLK_D2 for setting a portion of the phase update operation in the power saving mode. The selecting unit 330 selects and outputs the first divided clock signal CLK_D1 for the normal mode and the second divided clock signal CLK_D2 for the power saving mode based on the power saving mode control signal CTRL. The operation logic unit 34 outputs the DLL source clock signal DVD_CLK based on the first frequency-divided clock signal CLK_D1 and the internal clock signal IDVD_CLK in the normal mode 112670.doc -20-1324779, and the name is less than $-1. In the electrical mode, the DLL source clock signal DVD_CLK is output based on the second frequency division clock signal CLK_D2 and the inner IDVD_CLK. The steps of the phase update operation in the normal mode of the clock signal are described in detail as τ. First, the reference clock of the source clock generation unit 300 generates a "sum" operation output reference of the single internal clock signal IDVD_CLK and the source voltage VDD. Pulse signal REF CLK; operation logic unit 340; ^ &

- The phase delay signal 410 in the "n__~~" mode of the internal pulse signal IDVD_CLK and the first frequency-divided clock signal CLK_Dl receives the DLL source clock signal DVD-CLK to output the pulse signal DLL_CLK. Similarly, the dummy delay line 420 and the delayed replica model 44 产生 generate the feedback clock signal FB_CLK by modeling the DLL source clock signal DVD_CLK.

Count, to output the DLL source clock signal DVD_CLK for the positive update operation. The phase comparator 450 compares the feedback clock signal FB_CLK with the reference clock signal REF_CLK output from the source clock signal generating unit 300; the delay controller 430 controls the delay amount of the delay line 410 and the dummy delay line 420 to perform the normal mode. Phase update operation in the same manner. Similarly, the phase update operation in the power saving mode is described as follows. First, the reference clock generation unit 350 of the source clock generation unit 300 performs an AND operation of the internal clock signal IDVD_CLK and the source voltage VDD to output a reference clock signal REF_CLK; the operation logic unit 340 performs an internal clock signal IDVD_CLK and The second frequency-divided clock signal CLK_D2 is "and" 112670.doc 21 1324779, to output the DLL source clock signal DVD_CLK for the phase update operation in the power saving mode. Delay line 410 receives the DLL source clock signal DVD_CLK to output the DLL clock signal DLL_CLK. Similarly, the dummy delay line 420 and the delayed replica model 440 generate the feedback clock signal FB CLK by modeling the DLL source clock signal DVD_CLK. The phase comparator 45 0 compares the feedback clock signal fb_CLK with the reference clock signal REF_CLK output from the source clock signal generating unit 300; and the delay controller 430 controls the delay amount of the delay line 41〇 to perform the phase in the power saving mode. Update operation. As described above, according to the present invention, when a relatively fast phase update operation is required, such as in the normal mode, the internal clock signal is subjected to a smaller number of divisions, whereby the phase update operation is performed at a high frequency. The internal clock signal is subjected to a larger number of divisions when reducing power consumption, such as in power saving mode, whereby the phase update operation is performed more than once at low frequencies. Therefore, in the present invention, even if the semiconductor memory device stays in the power saving mode for a long time, the pulse generating unit effectively prevents the de-locking failure, thereby operating more stably. Fixing the clock of the clock frequency Pulse divider construction.

Set the power consumption. As mentioned above, in known configurations, the source clock generation unit is generated with . Conversely, in the variable clock frequency of the present invention, it is possible to reduce the semiconductor memory device for 29 days and December 19, 2005. The present application contains and is respectively at September 29曰112670.doc •22·1324779 〇〇 The inventions of the Korean Patent Application Nos. KR 2〇〇5 9i658 and KR 2005-125354, filed by the Korean Patent Office, the entire contents of each of which are hereby incorporated by reference. While the invention has been described with respect to the preferred embodiments of the present invention, those skilled in the art can readily appreciate that various changes can be made without departing from the spirit and scope of the invention as defined in the following claims. And modify. [Simple description of the map]

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a basic operation of a typical delay locked loop (DLL) circuit; Fig. 2 is a block diagram showing a known circuit; Fig. 3 is a timing chart for explaining the operation of the DLL of Fig. 2; FIG. 5 is a block diagram of the source clock generating unit of the first embodiment according to the present invention; FIG.

6A and 6B are detailed diagrams of the second clock demultiplexer in FIG. 5; FIG. 7 is used in FIG. 5 for you, a seven &&, w ', according to the present invention The timing diagram of the operation of the source clock of an embodiment generates a single 7L; FIG. 8 is a detailed circuit diagram of the logic diagram 7L shown in FIG. 5; FIG. 9 is the reference diagram generated in FIG. Detailed circuit diagram of a single cymbal; FIG. 10 is a block diagram of the present invention according to the present invention, which is shown in FIG. 4, which is scared by the secrets of the present invention. 11A and 11B are detailed circuit diagrams of the clock switching unit of FIG. 1 士 + 士# λ; 112670.doc -23- FIG. 12 is a source according to the second embodiment of the present invention shown in FIG. A timing diagram of the operation of the pulse generating unit; and FIGS. 13A and 13B are timing diagrams respectively describing simulation results of applying the source clock generating unit according to the first and second embodiments of the present invention. One

[Main component symbol description] 10 clock buffer 20 power saving mode controller 25 clock frequency divider 30 phase comparator 40 delay controller 50 delay line 60 dummy delay line 70 delay replica model 80 clock signal line 90 output buffer 100 clock buffer 200 power saving mode controller 300 source clock generation unit 310 first clock frequency divider 320 second clock frequency divider 330 selection unit 340 operation logic unit 350 reference clock generation unit 360 Pulse conversion unit I12670.doc •24· 1324779

370 400 410 420 430 440 450 600 8000 Clock Demultiplexer Phase Update Unit Delay Line Dummy Delay Line Delay Controller Delay Copy Model Phase Comparator DLL Circuit Clock Signal Line Output Buffer 112670.doc •25-

Claims (1)

丄 3: Z4/7y One of the modes of the memory device, the extension of the patent application No. 095124001, the Chinese patent application scope replacement (September 1998) X. The scope of the patent application: 1. A normal mode and a power-saving late lock loop (DLL), The method includes: a clock buffer for buffering an external clock signal to output an internal clock signal; a power saving chess controller for generating in response to a clock enable signal - power saving mode control a signal 'to define the normal mode or the power saving mode; a source clock generating unit for receiving the internal clock signal to generate a -DLL source clock under the control of the power saving control The signal and the phase update are used to output a DLL clock signal, , and medium based on the DLL source clock signal execution-phase update operation. The source clock generates a source clock signal for performing the phase update operation at least once during the power save mode. 2. The DLL of claim 1, wherein the source clock generation unit comprises: a first clock divider that is configured to generate a divide-by-frequency clock signal by dividing the internal clock signal by frequency division. To set one of the phase update operations in the normal mode for a duration; a first clock frequency divider, configured to generate a second frequency-divided clock signal by dividing the first frequency-divided clock signal to set one of the phase update operations in the power-saving mode Duration: : k select ItG ' | 帛 based on the power saving mode control signal to select the first and second frequency division clock (four) towel - thereby the selected I12670-980918.doc 1324779 signal And outputting a clock signal as a selection; and an arithmetic logic unit for logically combining the selected clock signal and the internal clock signal to rotate the DLL source clock signal. 3. The DLL of claim 2, wherein the selection unit selects the first-division clock signal for the positive f-mode, and selects the second frequency-divided pulse signal for the power-saving mode. 4. As requested in item 2 of the DLL' where the _th divider. The clock divider includes a divide-by-two clock pulse divider including a divide by 2n. 5. For the DLL of the second item, the tenth pulse divider is η, which is a positive integer. 6. The DLL of claim 2, wherein the poor _ _ 士 〆 甲 ° ° — 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时 时Each of the plurality of clocks has a plurality of fuse units; and has a plurality of fuse units different from the other clocks, which are used to cause 々 to cause one of the plurality of fuses to melt The wire is blown to select the one from the vein. When a plurality of early frequency readers are turned out 7·If the DLL of the request item 2, the middle whistle _ + (four), the check connection # , &quot; the first - clock demultiplexer includes: _ connected multiple units of the frequency division Pulse, each of the plurality of clocks generates a plurality of unit clocks, and 'and has a different clock from the other clocks for outputting a metal selection by using a frequency divider In the _ a plurality of selection processing units, the unit is selected from the plurality of single units. I12670-980918.doc 1324779 8. The DLL of claim 2, wherein the arithmetic logic unit comprises: a "reverse" gate for performing the "reverse" of the internal clock signal and the selected clock signal And an inverter for inverting an output signal of the "reverse" gate to output the DLL source clock signal. 9. The DLL of claim 2, wherein the source clock generation unit comprises a reference clock generation unit for generating a reference by performing an AND operation of the internal clock signal and a source voltage Clock signal. 10. The DLL of claim 9, wherein the phase update unit comprises: a delay line 'for delaying one phase of the DLL source clock signal to output the DLL clock signal; a dummy delay line having substantial a composition having the same composition as the delay line; a delayed replica model for modeling one of the output signals of the dummy delay line according to a delay factor of a clock signal in the memory device, thereby using the model The signal is output as a feedback clock signal; a phase comparator for comparing the reference clock signal with the feedback clock signal 'to detect a phase difference therebetween; and a delay controller for using Receiving an output signal of the comparator to control the delay amount of the delay line and the dummy delay line. 11. The request item 12DLL, wherein the source clock generation unit comprises: a clock demultiplexer configured to generate a first converted clock signal by dividing the internal clock signal to set the normal 112670-9809l8.doc one of the update operations; a clock conversion unit for generating a second converted clock signal by converting the first converted clock signal to set the power saving mode One of the phase update operations of the duration; a selection unit that selects one of the first and second converted clock signals based on the power save mode control signal, thereby using the selected signal as a Selecting a clock signal to output; and a sounding logic unit for logically combining the selected clock signal and the internal clock signal to output the DLL source clock signal. 12. The DLL of claim U, wherein the selection unit selects the first transition clock signal for the normal mode, and selects the second transition pulse signal for the power save mode. 13. The DLL of claim 11, wherein the clock divider comprises a divide-by-two clock multiplexer. 〃 14. If the request 丨丨 DLL 'where the clock conversion unit includes a clock conversion benefit, the clock converter periodically selects a portion of the first converted clock signal to select the selected clock signal As the second conversion, the pulse is far away. 15. The DLL of claim 11, wherein the clock conversion unit comprises: a plurality of unit clock converters connected in series for generating a plurality of clocks each of the plurality of clocks a unit clock different from the other clocks; and a plurality of fuse units for selecting a dissolved filament (4) from one of the plurality of fuses from the plurality of unit clocks (four) output 112670 -9809l8.doc One of the clocks. 16) The DLL of the request item, wherein, the clock conversion unit comprises: a plurality of single clock transitions connected in series, which are used to generate a complex clock, the mother of the plurality of clocks Having an early clock with other clocks; and a plurality of selection processing units in the clock by using a metal selection unit clock converter output, the unit selects from the complex number One of them. 17. A DLL as claimed, wherein the source clock generation unit includes a reference generation unit </ RTI> for generating an _ reference clock signal by performing an operation of the internal clock signal and a source voltage. 18. The DLL of claim 7, wherein the phase update unit comprises: a delay line for delaying a phase of the DLL source clock signal to output the DLL clock signal; a dummy delay line Having a composition substantially the same as the composition of the delay line; a delayed replica model for modeling one of the output signals of the dummy delay line according to a delay factor of a clock signal in the memory device, thereby The modeled signal is output as a feedback clock signal; a phase comparator 'used to compare the reference clock signal with the feedback clock signal' to detect a phase difference therebetween; and a delay controller, The method is configured to receive an output signal of the phase comparator to control a delay amount of the delay line and the dummy delay line. 112670-980918.doc U24779 19. The request item iijDLL, and the medium-eight-source source Bf pulse generating unit comprises: a first clock conversion unit; a second clock conversion unit; a selection unit for The power saving mode control signal selects one of the output signals of the first and second clock conversion units, whereby the selected signal is output as a selection clock signal; and the operation logic unit 其The selected clock signal and the internal clock signal are logically combined to output the DLL source clock signal. 2. The muscle of claim 19, wherein the first-clock conversion unit generates a -first-conversion clock signal by converting the (four) clock til number to set the phase update operation in the positive mode One of the durations; and the second clock conversion unit generates a second conversion clock signal by converting the first conversion clock signal to set a duration of the phase update operation in the power saving mode. 21. The DLL of claim 20, wherein the selection unit selects the first conversion clock signal for the normal mode, and selects the second conversion clock signal for the power saving mode. 22. The DLL of claim 20, wherein the first clock conversion unit comprises a divide-by-two clock divider. 23. The DLL of claim 20, wherein the second clock conversion unit comprises a clock converter, the clock converter periodically selecting a portion of the first transition clock signal to select the selected clock signal The second converted clock signal is output. 24. The DLL of claim 20, wherein the second clock conversion unit comprises: 112670-980918.doc -6-s = a plurality of connected unit clock transitions 用于, which are used to generate a complex number =::: plural Each of the clocks has an early clock that is different from the other clocks; and a plurality of (four) early π's are used to select the filaments by one of the plurality of filaments. One of the clocks from the plurality of unit clock outputs. For example, the DLL of the π-term 20 includes: the second clock conversion unit includes: a plurality of unit clock converters connected by the event, wherein (4) generating a plurality of clocks, each of the plurality of clocks having one a unit clock different from the other clocks; and f number of selection processing units 'which are used to select one of the clocks of the clock converter output from the plurality of unit by using the metal selection processing unit . &amp; DLL of claim 20, wherein the source clock generation unit &amp; includes a reference clock generation unit for performing an AND operation on the internal clock signal and a source voltage Generate a reference clock signal. 27. The DLL of claim 26, wherein the phase update unit comprises: a delay line for delaying a phase of the DLX source clock signal to rotate the DLL clock signal; a dummy delay line having a composition identical to the composition of the delay line; a delayed replica model 'for modeling one of the dummy delay lines to output a signal according to a delay factor of one of the clock signals in the memory device' The signal is output as a feedback clock signal; 112670-980918.doc 1324779 A phase comparator for comparing the reference clock signal with the feedback clock signal to detect a phase difference therebetween; and a delay The controller 'is configured to receive one of the phase comparator output signals' to control the delay amount of the delay line and the dummy delay line. 28. A method for generating a DLL clock of a memory device having a normal mode and a power saving mode, comprising: generating an internal clock signal by buffering an external clock; Generating a first frequency division clock signal by dividing the internal clock signal; generating a second frequency division clock signal based on the first frequency division clock signal; in the normal mode, based on the - a frequency division signal execution-DLL phase update operation; and in the power save mode, performing a DLL phase update operation based on the second frequency division clock signal, which causes the phase update in the power saving mode The operation is performed at least once during the power saving mode. 29. The method of π, wherein the generating the second divided clock signal comprises dividing the first divided clock signal. The method of claim 28, wherein generating the second frequency-divided clock signal comprises converting the first frequency-divided clock signal. 3 1 - The method of claim 28 wherein the _dividing clock signal is used to set the duration of the phase update operation in the normal mode. 32. The method of claim 28, wherein the second frequency-divided clock signal is used to set a duration of the phase update operation in the power save mode. The method of claim 28, wherein performing the DLL phase update operation based on the first frequency-divided clock signal comprises: performing an AND operation of the internal clock signal and a source voltage Generating a reference clock signal; generating a DLL source clock signal by performing an AND operation of the internal clock signal and the first frequency division clock signal; using a delay factor of the memory device Modeling the DLL source clock signal to generate a feedback clock signal; and controlling the delay amount of one of the VDD source clock signals by comparing the feedback clock signal with the reference clock signal. The method of claim 28, wherein the step of performing a far DLL phase update operation based on the second frequency-divided clock signal comprises: performing an AND operation of the internal clock signal and a source voltage, Generating a reference clock signal; generating a DLL source clock signal by performing an AND operation of the internal clock signal and the second frequency division clock signal; delaying by using the memory device The factor modeling the dll source clock signal generates a feedback clock signal; and controlling the delay amount of the DLL source clock signal by comparing the feedback clock signal with the reference clock signal. I12670-980918.doc •9-