TWI508458B - Delay locked loop and related method - Google Patents

Description

Delay locked loop and related methods

The present invention relates to a delay locked loop, and more particularly to a delay locked loop applied to a storage circuit.

At present, the prior art uses synchronous communication to achieve high data transmission rate of dynamic random access memory. However, when the technology of dynamic random access memory develops to a more advanced and higher speed generation, for example, the third generation double data rate Double Data Rate Three Synchronous Dynamic Random Access Memory (DDR3 SDRAM), a circuit that uses a phase-locked loop and an analog delay signal line to achieve synchronous communication, which cannot achieve high transmission data rate due to process limits. The need for dynamic random access memory. In addition, the signal transmission between the phase-locked loop and the analog-delay signal line is performed in the form of analog signals, and the voltage of the analog signal is susceptible to noise, resulting in errors in the data access time or signal level of the memory. This problem is particularly serious for high transmission data rate dynamic random access memory.

Accordingly, it is an object of the present invention to provide a digital delay locked loop for controlling a digital delay line that solves the aforementioned problems.

In accordance with an embodiment of the present invention, a delay locked loop is disclosed. The delay locked loop includes a pulse generator, a delay unit, a phase detector and a control unit. The pulse generator is configured to generate a predetermined pulse signal and a determination signal according to an input clock signal; the delay unit is coupled to the pulse generator for delaying the predetermined pulse signal according to the digital control signal, a delay pulse signal is generated. The phase detector is coupled to the delay unit and the pulse generator, and is configured to detect a time delay of the delayed pulse signal according to the determination signal to generate a detection result signal. The control unit is coupled to the phase detector and the delay unit, and configured to generate the digital control signal according to the detection result signal to control the delay caused by the delay unit to the predetermined pulse signal.

In accordance with an embodiment of the present invention, a method for use in a delay locked loop is further disclosed. The method includes: generating a predetermined pulse signal and a determination signal according to an input clock signal; delaying the predetermined pulse signal according to the digital control signal to generate a delayed pulse signal; detecting the delay according to the determination signal One time delay of the pulse wave signal to generate a detection result signal; and generating the digital control signal according to the detection result signal to control the step of delaying the predetermined pulse wave signal according to the digital control signal to the predetermined pulse wave The amount of delay caused by the signal.

In addition, the digital control signal of the above embodiment can be used to control the delay caused by another delay unit to receive an input signal (for example, another predetermined pulse signal), so that no other control mechanism is needed. Reduce overall circuit cost.

Referring to FIG. 1 and FIG. 2 together, FIG. 1 is a schematic diagram of the delay lock loop 100 according to the first embodiment of the present invention, and FIG. 2 is a schematic diagram of the signal relationship included in the delay lock loop 100 of FIG. 1. As shown in FIG. 1, the delay lock loop 100 includes a pulse generator 105, a delay unit 110, a phase detector 115, and a control unit 120. The delay unit 110 is implemented by a Digital Controlled Delay Line (DCDL), and the phase detector 115 is implemented by a D-type flip-flop, which is one of the D-type flip-flops. The pulse input end is configured to receive a determination signal S_J generated by the pulse wave generator 105, and one of the data input terminals of the D-type flip-flop is configured to receive a delayed pulse signal S_P2 output by the delay unit 110, and The data output end of the D-type flip-flop is used to generate a detection result signal S_D to the control unit 120 according to the determination signal S_J and the delayed pulse signal S_P2. It should be noted that the operation and function of the phase detector 115 implemented by the D-type flip-flop are not limited by the present invention. In other embodiments, different components may be used to implement the operation and function of the phase detector 115.

The pulse generator 105 refers to an external input clock signal S_CLK to generate a predetermined pulse signal S_P1 to the delay unit 110, and generates a determination signal S_J to the phase detector 115. The delay unit 110 is coupled to the pulse generator 105 for receiving the predetermined pulse signal S_P1, and delaying the predetermined pulse signal S_P1 according to a digital control signal S_C1 generated by the control unit 120, thereby generating the delayed pulse. Wave signal S_P2. The phase detector 115 is coupled to the delay unit 110 and the pulse generator 105, and is configured to receive the determination signal S_J generated by the pulse wave generator 105, and detect the delay unit 110 to the predetermined pulse according to the determination signal S_J. The time delay caused by the wave signal S_P1 (that is, the time delay of the pulse signal S_P2 after the delay) generates the detection result signal S_D. The control unit 120 is coupled to the phase detector 115 and the delay unit 110, and configured to generate the digital control signal S_C1 according to the detection result signal S_D to adjust the delay caused by the delay unit 110 to the predetermined pulse signal S_P1. , thereby adjusting the time delay of the delayed pulse signal S_P2. In addition, the pulse generator 105 further generates a notification signal S_J to the control unit 120 to notify the control unit 120 to perform the determination operation, that is, the pulse wave generator 105 can control the time point at which the control unit 120 makes the determination.

As shown in FIG. 2, it shows the signal relationship between the signals S_CLK, S_P1, S_P2 and S_J. In this embodiment, the predetermined pulse signal S_P1 generated by the pulse wave generator 105 is a square wave signal, and the period T1 of the square wave signal is set to be four times the period T_CLK of the input clock signal S_CLK. As the signal voltage or temperature changes, the delayed pulse signal S_P2 output by the delay unit 110 actually has different time delays. For example, the second figure shows that the delayed pulse signal S_P2 has different time delays D_1 and D_2. The phase detector 115 can determine whether the different time delays (for example, D_1 and D_2) are longer or shorter according to the determination signal S_J to determine whether shortening or lengthening is needed, for example, in the embodiment, when the pulse wave When the generator 105 generates the predetermined pulse signal S_P1, the determination signal S_J is also generated, and the pulse width T_J of the determination signal S_J is a designed ideal time delay. If the actual time delay is longer than the pulse width of the determination signal S_J , indicating that the actual time delay needs to be shortened, and vice versa, the actual time delay needs to be extended. In the example of FIG. 2, when the time delay of the delayed pulse signal S_P2 is D_1, the determination signal S_J is inverted and then passed through the clock input end by the D-type flip-flop of the phase detector 115. Receive (set an inverter in front of the clock input of the D-type flip-flop), therefore, when the signal S_J is judged to have a falling edge, the D-type flip-flop will input its data input terminal. After receiving the delayed pulse signal S_P2, the signal level is output to the data output end to generate the detection result signal S_D, taking the actual time delay D_1 as an example. Since the actual time delay is short, the D-type flip-flop device The received signal level is '1', so the signal logic level of the detection result signal S_D is '1', and the control unit 120 controls the delay appropriately according to the signal logic level of the detection result signal S_D. The unit 110 increases the delay caused by the predetermined pulse signal S_P1 to extend the actual time delay of the delayed pulse signal S_P2; otherwise, taking the actual time delay D_2 as an example, since the actual time delay is long, the D-type is positive and negative. The signal level obtained by the device is '0', because The signal logic level of the detection result signal S_D is '0', and the control unit 120 appropriately controls the delay unit 110 to reduce the delay caused by the predetermined pulse signal S_P1 according to the signal logic level of the detection result signal S_D. The amount is used to shorten the actual time delay of the pulse signal S_P2 after the delay. Thus, by repeatedly operating the plurality of times, the control unit 120 can adjust the actual time delay to approximate or be equivalent to the pulse width T_J of the determination signal S_J (ie, the designed ideal time delay).

It should be noted that the signal relationship contained in the delay locked loop 100 shown in FIG. 1 can also be designed in different styles, and is not limited to the signal relationship shown in FIG. For example, the period T1 of the predetermined pulse signal S_P1 can also be set to be twice, three times or other multiples of the period T_CLK of the input clock signal S_CLK, and the phase detector 115 can also be implemented by using other circuits. The time at which the detection result signal S_D is generated may occur at other time points than the falling edge of the determination signal S_J. For example, the phase detector 115 may be implemented by other circuits to cause the rising edge (Rising Edge) of the determination signal S_J. When the detection result signal S_D is generated, in other words, the embodiment of the present invention performs the foregoing time delay of the delayed pulse signal S_P2 when the transition of the logic level of one of the pulse signals S_J is used. / Late judgment; all variations of the design are within the scope of the present invention.

In addition, the control unit 120 may employ different algorithm logic to control the delay unit 110 such that the last output digital control signal S_C1 corresponds to a preferred adjustment amount. For example, a step-by-step search algorithm or a binary search algorithm can be used. In order to achieve better performance, in the embodiment, the control unit 120 uses a binary search algorithm to quickly obtain the digital control signal S_C1 corresponding to the preferred adjustment amount, for example, if the digital control The signal S_C1 has 10 bits, and the initial value of the digital control signal S_C1 is set to '1000000000'. When the initial value is used to adjust the actual time delay, the signal logic level of the detection result signal S_D is '0'. (that is, the actual time delay is long), the control unit 120 adjusts the digital control signal S_C1 to '0100000000' according to the signal level '0' of the detection result signal S_D, and then adjusts the value according to the value. Reduce the actual time delay. On the other hand, when the initial value '1000000000' is used to adjust the actual time delay and the signal logic level of the detection result signal S_D is '1' (that is, the actual time delay is short), the control unit 120 is based on The signal level '1' of the detection result signal S_D is adjusted to the digital control signal S_C1 to '1100000000', and then the adjusted value is used to extend the actual time delay. In other words, the control unit 120 adjusts the next highest effective bit from the Most Significant Bit (MSB) to obtain the digital control signal S_C1 until the value of the digital control signal S_C1 is determined to control the actual When the time delay is close to the ideal phase delay, the control unit 120 ends the operation of the binary search algorithm and uses the last generated digital control signal S_C1 as the optimal control signal. Since the phase detector 115 uses a simple Early/Late Judgment to determine the length of the actual time delay caused by the previous digital control signal S_C1, the control unit 120 uses a binary search algorithm. The preferred digital control signal S_C1 is obtained. Therefore, the delay locked loop 100 of the present embodiment can have higher performance. It should be noted that the temperature and signal voltage changes will change the current actual time delay value at any time. Therefore, when the control unit 120 performs time delay control, the value of the digital control signal S_C1 outputted will also change to correct. At present, the actual time delay, in other words, the Least Significant Bit (LSB) of the digital control signal S_C1 may jump between '0' and '1'. To solve this problem, the control unit 120 may perform multiple times. The binary search averages the search results multiple times, and the averaged result is used as the digital code corresponding to the digital control signal S_C1. Of course, if the performance of the algorithm is shortened and the operation time of the algorithm is shortened, the control unit 120 may also ignore the case where the least significant bit jumps between '0' and '1', and directly obtain the binary search for the first time. The search result is used as the digital code corresponding to the digital control signal S_C1.

Moreover, the delay unit 110 can design a function with multi-phase selection, and select one of the desired specific phases by the control unit 120 outputting the phase selection signal S_C2. Please refer to FIG. 3, which is a circuit diagram of an embodiment of the delay unit 110 shown in FIG. 1. As shown in FIG. 3, the delay unit 110 includes a plurality of phase delay circuits 405A-405H and a phase selection circuit 406. Each phase delay circuit includes a first inverter and a second inverter, respectively. Each of the inverters is provided with at least one controllable resistor (which is implemented by using two resistors in this embodiment, which is not a limitation of the present invention), wherein the digital control signal S_C1 generated by the control unit 120 is used. Controlling the resistance of the controllable resistors associated with each inverter to adjust the charging time of the supply voltage to the controllable resistors and capacitors to achieve an activation time delay of the inverter, the startup time delay is The amount of delay caused by the delay unit 110 for the predetermined pulse signal S_P1. In addition, regarding the operation and function of the first and second inverters, for example, the first inverter of the phase delay circuit 405A receives the predetermined pulse signal S_P1 input to the phase delay circuit 405A, and the predetermined pulse wave The signal S_P1 is inverted to generate an inverted signal, and the second inverter is inverted again by the inverted signal generated by the first inverter, and the signal generated at this time is used as the phase delay. The output signal of the circuit 405A is output to the next phase delay circuit 405B. In other words, for the input signal and the output signal of the phase delay circuit 405A, the signal relationship between them is not reversed and only has a phase delay. The phase delay of the delay circuit 405A is composed of the respective time delays of the first and second inverters from receiving the signal to generating the inverted signal; the other phase delay circuits 405B-405H and their respective first and second inverses The phase device also has the same or similar operations and functions as above, and will not be further described herein.

Since each inverter applies a phase delay amount to the predetermined pulse signal S_P1, the output signals of the different inverters can be regarded as the delayed predetermined pulse signal S_P2 having different phases, so that a specific phase is obtained. After the delay, the predetermined pulse signal S_P2 is selected, and the specific phase must be appropriately selected to obtain the signal S_P2. The phase selection circuit 406 in this embodiment is used to select the specific phase from the complex phase delay amount according to the phase selection signal S_C2. . In practice, the phase selection circuit 406 includes a plurality of multiplexers 410A-410G and an inverter 415. The output signals of each of the first inverters are first coupled to the input ends of the first group of multiplexers 410A and 410B. The output ends of the first group of multiplexers 410A and 410B are coupled to the input end of the multiplexer 410C, and then the output end of the multiplexer 410C is coupled to the input end of the multiplexer 410G via the connection of the inverter 415. The function of the inverter 415 is to eliminate the signal inversion caused by the first inverter. In addition, the output signal of each of the second inverters is first coupled to the input ends of the second group of multiplexers 410D and 410E, and the outputs of the first group of multiplexers 410D and 410E are coupled to the multiplexer 410F. The input, and then the output of the multiplexer 410F is coupled to the input of the multiplexer 410G. The multiplexers 410A-410G are appropriately controlled by the phase selection signal S_C2, and the output signal of the final multiplexer 410G is the delayed predetermined pulse signal S_P2 having a specific phase. For example, the delay locked loop 100 performs phase delay locking according to the output signal of the phase delay circuit 405H of the determining signal S_J and the delay unit 110. After the delay locked loop 100 is locked, the output of the phase delay circuit 405H of the delay unit 110 is output. The phase delay amount generated by the signal is equal to the pulse width T_J of the determination signal S_J. At this time, one of the inverters of each phase delay circuit in the delay unit 110 causes a pulse width T_J of one-sixteenth. The amount of phase delay, therefore, if the output signal of the multiplexer 410G is the output signal of the first inverter of the phase delay circuit 405B, the magnitude of the specific phase is the pulse width T_J of 16/3; If the output signal of the multiplexer 410G is the output signal of the first inverter of the phase delay circuit 405C, the magnitude of the specific phase is the pulse width T_J of 5/16; the others are the same. In another embodiment, the delay locked loop 100 may first control the phase selection circuit 406 with the phase selection signal S_C2 and select an output signal from the output signals generated by the phase delay circuits 405A-405H, and then select the output according to the selected output. The signal and the judgment signal S_J are used for phase delay locking. Therefore, when the delay lock loop 100 is phase-locked, the phase delay amount of the selected output signal is equal to the pulse width T_J of the determination signal S_J.

In addition, the control unit 120 of the present embodiment can generate a digital control signal S_C1 according to the detection result signal to control another delay amount caused by another delay unit to another predetermined pulse signal. Referring to FIG. 4, FIG. 4 is a schematic diagram of the delay locked loop 100 shown in FIG. 1 of the present invention applied to a high transmission data rate dynamic random access memory. The high transmission data rate dynamic random access memory can be, for example, a dual channel random access memory or other memory with a higher data access rate. Wherein, the high transmission data rate dynamic random access memory has a plurality of digital control delay lines. For convenience of description, FIG. 4 only shows four digital control delay lines, and the application of the present invention is the control of FIG. The digital control signals S_C1, S_C2 generated by unit 120 are output to other digital control delay lines to appropriately control the time delay caused by other digital control delay lines and to select an appropriate phase. In the circuit architecture of the high transmission data rate dynamic random access memory, the control signals S_C1 and S_C2 are in the form of digital signals on the control end (ie, the delay locked loop 100) and the controlled end (ie, other delays). The transmission between the lines is such that the circuit structure shown in Fig. 3 of the present embodiment can reduce or avoid errors caused by noise as compared with the conventional techniques for transmitting signals in the form of analog signals. In addition, since all digitally controlled delay lines implemented in the high transmission data rate DRAM should ideally have the same or similar characteristics, that is, when faced with temperature changes or signal voltage changes, The actual time delay amount should ideally have the same trend change. Therefore, this embodiment can control other digital control delay lines by using a single digital control delay line time delay control result to reduce the number of overall control circuits. .

Moreover, since the delay unit 110 can be designed to have a multi-phase selection function, in other embodiments, a phase compensation unit can also be used to make the phase detector 115 more accurate. Please refer to FIG. 5, which is a schematic diagram of a delay locked loop 500 according to a second embodiment of the present invention. The delay lock loop 500 includes a compensation unit 125 in addition to the pulse generator 105, the delay unit 110, the phase detector 115 and the control unit 120. The compensation unit 125 is disposed on the pulse generator 105 and the phase detector. Between 115, and used to phase compensate the judgment signal S_J generated by the pulse wave generator 105. For example, the delay unit 110 can apply a specific phase to the predetermined pulse signal S_P1 to generate the delayed pulse signal S_P2 having the specific phase, and the compensation unit 125 is configured to apply a phase amount to the determination signal S_J, wherein the compensation is performed. The amount of phase applied by unit 125 is proportional to the particular phase applied by delay unit 110. Since the phase amount is proportional to the particular phase, the amount of phase applied by compensation unit 125 will become greater when the particular phase is larger. Therefore, the phase compensation can be effectively performed, and the effect of reducing the phase deviation between the determination signal S_J and the delayed pulse signal S_P2 is achieved, and the judgment accuracy of the subsequent phase detector 115 is improved. In addition, if the phase amount applied by the compensation unit 125 is substantially the same as the specific phase applied by the delay unit 110, the phase amount will be used for phase compensation to eliminate the phase deviation between the two signals. In addition, the operation of the compensation unit 125 can be controlled by the control unit 120 to adjust the amount of phase applied thereto.

Please refer to FIG. 6. FIG. 6 is a flow chart showing the operation of the delay lock loop shown in FIG. 1. If the same result is generally achieved, it is not necessary to perform the sequence of steps in the process shown in FIG. 6, and the steps shown in FIG. 6 do not have to be performed continuously, that is, other steps may be inserted therein. The detailed step description is described below: Step 600: Start; Step 605: The pulse generator 105 receives the input clock signal S_CLK to generate a predetermined pulse signal S_P1 to the delay unit 110, and generates a determination signal S_J; Step 610: The delay unit 110 delays the predetermined pulse signal S_P1 according to the digital control signal S_C1 generated by the control unit 120, thereby generating the delayed pulse signal S_P2. Step 615: The phase detector 115 detects the delay of the delay unit 110 according to the determination signal S_J. The time delay caused by the pulse signal S_P2 is generated, thereby generating the detection result signal S_D; Step 620: The control unit 120 generates the digital control signal S_C1 according to the detection result signal S_D to adjust the delay pulse unit 110 to the predetermined pulse wave. The delay caused by the signal S_P1, thereby adjusting the time delay of the delayed pulse signal S_P2; Step 625: The control unit 120 according to the notification signal S_I Line B / late determination; Step 630: determining whether a binary search is completed; Step 635: determining whether obtaining the optimum / better S_C1 digital control signal; and Step 640: End.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 500. . . Delay locked loop

105. . . Pulse generator

110, 130A~130D. . . Delay unit

115. . . Phase detector

120. . . control unit

125. . . Compensation unit

405A~405H. . . Phase delay circuit

406. . . Phase selection circuit

410A~410G. . . Multiplexer

415. . . inverter

Fig. 1 is a schematic view showing a delay lock loop of the first embodiment of the present invention.

Figure 2 is a schematic diagram of the signal relationship contained in the delay locked loop of Figure 1.

Fig. 3 is a circuit diagram showing an embodiment of the delay unit shown in Fig. 1.

Figure 4 is a schematic diagram of the delay locked loop shown in Figure 1 of the present invention applied to a high transmission data rate dynamic random access memory.

Figure 5 is a schematic diagram of a delay lock loop in accordance with a second embodiment of the present invention.

Figure 6 is a flow chart showing the operation of the delay lock loop shown in Figure 1.

100. . . Delay locked loop

105. . . Pulse generator

110. . . Delay unit

115. . . Phase detector

120. . . control unit

Claims (14)

A delay lock loop includes: a pulse generator for generating a predetermined pulse signal and a determination signal according to an input clock signal; and a delay unit for delaying the predetermined pulse according to a digital control signal The signal generates a delayed pulse signal; a phase detector is configured to detect a time delay of the delayed pulse signal according to the determination signal to generate a detection result signal; and a control unit for Generating the digital control signal according to the detection result signal to control a delay amount caused by the delay unit to the predetermined pulse wave signal; wherein the phase detector is indicated by the width of the pulse wave of one of the determination signals A rising edge and a corresponding falling edge perform an Early/Late Judgment on the time delay of the delayed pulse signal to generate the detection result signal. The delay locked loop of claim 1, wherein the pulse generator is further configured to generate a notification signal, and the control unit generates the digital signal according to the detection result signal when receiving the notification signal. Control signal. The delay locked loop according to claim 1, wherein the phase detector performs the time delay of the delayed pulse signal when the logic level of the pulse wave of the determination signal is changed. The early/late judgment. The delay locked loop according to claim 1, wherein the control unit generates the digital control signal according to the detection result signal and a binary search method. The delay locked loop as described in claim 1, wherein the digital control signal generated by the control unit is used to control another delay unit. The delay lock loop of claim 1, wherein the delay unit is further configured to apply a specific phase to the predetermined pulse signal, and the delay lock loop further comprises: a compensation unit coupled to the pulse wave Between the generator and the phase detector, a phase quantity is applied to the determination signal for phase compensation, wherein the phase quantity applied by the compensation unit is proportional to the specific phase applied by the delay unit. The delay locked loop of claim 6, wherein the phase amount applied by the compensation unit is substantially the same as the specific phase applied by the delay unit. The delay locked loop according to claim 1, wherein the delay unit comprises: a complex phase delay circuit, wherein each of the phase delay circuits applies a phase delay amount according to the digital control signal The predetermined pulse wave signal; A phase selection circuit is configured to select the specific phase from the plurality of phase delay quantities generated by the phase delay circuits to output the delayed pulse signal having the specific phase. A method for using a delay locked loop includes: generating a predetermined pulse signal and a determination signal according to an input clock signal; delaying the predetermined pulse signal according to a digital control signal to generate a delayed pulse signal And detecting, according to the determining signal, a time delay of the delayed pulse signal to generate a detection result signal, the step of generating the detection result signal includes: indicating, according to a width of a pulse wave of the determination signal a rising edge and a corresponding falling edge, performing an early/late determination on the time delay of the delayed pulse signal to generate the detection result signal; and generating the digital control signal according to the detection result signal, The amount of delay of the pulse signal after the delay is controlled. The method of claim 9, wherein the step of generating the digital control signal according to the detection result signal is performed when a notification signal is received. The method of claim 9, wherein the step of performing the early/late determination of the time delay of the delayed pulse wave signal is when the logic level of the pulse wave of the determination signal is changed. carried out. The method of claim 9, wherein the step of generating the digital control signal comprises: generating the digital control signal according to the detection result signal and a binary search method. The method of claim 9, further comprising: applying a specific phase to the predetermined pulse wave signal; and before performing the step of detecting the time delay of the pulse signal after the delay according to the determining signal, A phase amount is applied to the determination signal for phase compensation; wherein the phase amount applied to the determination signal is proportional to the specific phase. The method of claim 13, wherein the phase amount applied to the determination signal is substantially the same as the specific phase.