KR100845804B1 - Circuit and method for controlling clock in semiconductor memory apparatus - Google Patents

Abstract

A circuit and a method for controlling a clock in a semiconductor memory apparatus are provided to improve the reliability of data output operation. A clock conversion unit(10) converts an external clock into an internal clock by controlling the phase of the external clock according to the control of a dividing enable signal. A transmission unit(20) transmits the internal clock. A data output strobe signal generation unit(30) corrects duty cycle of the internal clock transmitted from the transmission unit according to the control of the dividing enable signal, and generates a data output strobe signal using the same.

Description

Circuit and Method for Controlling Clock in Semiconductor Memory Apparatus

1 is a block diagram showing a configuration of a clock control circuit of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a detailed configuration diagram of the clock converting means shown in FIG. 1;

3 is a detailed configuration diagram of the data output strobe signal generating unit shown in FIG. 1;

4A is a detailed configuration diagram of the first duty cycle corrector illustrated in FIG. 3;

4B is a detailed configuration diagram of the second duty cycle correction unit illustrated in FIG. 3;

5 is a detailed configuration diagram of the duty cycle control unit shown in FIG. 3;

6 is a detailed configuration diagram of the dispensing determination unit shown in FIG. 3;

7 is a block diagram illustrating a configuration of a clock control circuit of a semiconductor memory device according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10/40: clock conversion means 20/50: transmission means

30/60: data output strobe signal generating means

110: DLL circuit 120: clock divider circuit

130: clock selector

The present invention relates to a clock control circuit and method of a semiconductor memory device, and more particularly to a clock control circuit and method of a semiconductor memory device for generating a data output strobe signal having a more accurate enable interval.

In general, a semiconductor memory device includes a data output buffer for a data output operation. The data output buffer performs a function of synchronizing the data transmitted through the global input / output line with the data output strobe signal. The data output strobe signal can be a clock having a high duration at the rising edge time of the DLL (Delay Locked Loop) clock (hereinafter, referred to as a rising clock) or a clock having a high duration at the falling edge time of the DLL clock (hereinafter, a falling clock). And a data output strobe signal generation circuit for this function.

In general, a DLL circuit generates a DLL clock having a predetermined time ahead of an external clock to compensate for delay values of delay elements existing in a semiconductor memory device, and divides the clock into a rising clock and a falling clock, respectively. The duty ratio is adjusted to 50%. Therefore, ideally, the duty ratio of the rising clock and the falling clock transmitted to the data output strobe signal generation circuit should not change, but the duty ratio actually changes due to the resistance and noise present in the transmission line of the clock. . As such, when the data output strobe signal is generated when the duty ratio of the rising clock and the falling clock is not 50%, the enable period of the data output strobe signal is changed so that the operation of the data output buffer cannot be accurately controlled. In extreme cases, a malfunction may occur in which the data output operation is not performed.

However, the data output strobe signal generation circuit of the semiconductor memory device according to the related art has generated the data output strobe signal from the rising clock and the falling clock whose duty ratios do not exactly match, and thus the data output strobe signal having the correct enable period. Could not be printed. As a result, the semiconductor memory device is exposed to data output malfunctions unprotected, thereby preventing the accurate data output operation, and the reliability of the data output operation of the semiconductor memory device is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a clock control circuit and method for a semiconductor memory device which improves reliability of a data output operation.

Another object of the present invention is to provide a clock control circuit and a method of a semiconductor memory device for generating a data output strobe signal having an accurate enable period even at the beginning of operation.

In addition, another object of the present invention is to provide a clock control circuit and a method of a semiconductor memory device for generating a data output strobe signal having an accurate enable period even in a DLL off mode.

A clock control circuit of a semiconductor memory device according to an embodiment of the present invention for achieving the above-described technical problem, Clock conversion means for controlling the phase of the external clock in accordance with the control of the frequency division enable signal to convert to an internal clock; Transmission means for transmitting the internal clock; And data output strobe signal generation means for correcting a duty cycle of the internal clock transmitted from the transmission means and generating a data output strobe signal using the divided enable signal under control of the frequency division enable signal.

In addition, a clock control circuit of a semiconductor memory device according to another embodiment of the present invention includes: clock converting means for selectively outputting a divided clock or DLL clock obtained by dividing an external clock at a predetermined ratio as an internal clock; And data output strobe signal generating means for receiving a data output strobe signal and controlling and outputting a duty cycle of the data output strobe signal in response to a cycle of the internal clock.

In addition, the clock control method of a semiconductor memory device according to an embodiment of the present invention, a) controlling the phase of the external clock under the control of the frequency division enable signal to convert to an internal clock; b) transmitting said internal clock; And c) correcting the duty cycle of the internal clock transmitted from step b) under the control of the division enable signal and generating a data output strobe signal using the same.

The method of controlling a clock of a semiconductor memory device according to another embodiment of the present invention may include: a) selectively outputting a divided clock or DLL clock obtained by dividing an external clock at a predetermined ratio as an internal clock; And b) receiving a data output strobe signal and controlling and outputting a duty cycle of the data output strobe signal in response to a period of the internal clock.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a configuration of a clock control circuit of a semiconductor memory device according to an embodiment of the present invention.

As shown, the clock control circuit includes a clock converting means 10 for controlling the phase of the external clock clk_ext and converting it to an internal clock clk_int under the control of the division enable signal divide, and the internal clock. Correcting the duty cycle of the internal clock clk_int transmitted from the transmission means 20 under the control of the transmission means 20 for transmitting the clk_int and the division enable signal divide, and outputting the data using the same. Data output strobe signal generating means 30 for generating the strobe signal dqs.

In the clock control circuit configured as described above, the internal clock clk_int is implemented as a divided clock or DLL clock that divides the external clock clk_ext at a predetermined ratio. To this end, the clock converting means 10 operates according to whether the division enable signal is enabled. That is, when the frequency division enable signal divide is enabled, the frequency division clock is output as the internal clock clk_int, and when the frequency division enable signal divide is disabled, the DLL clock is converted into the internal clock clk_int. Output as.

The transmission means 20 is a representation leading to a general transmission line, and includes a plurality of delay elements so that the transmission of the internal clock clk_int may occur due to the effects of delay and noise caused by the respective elements during transmission of the internal clock clk_int. The duty cycle is wrong.

The data output strobe signal generating means 30 corrects the duty cycle of the internal clock clk_int where the duty cycle is misaligned and generates the data output strobe signal dqs by using the same. At this time, the period of the DLL clock is shorter than the period of the divided clock. The data output strobe signal generating means 30 determines whether the internal clock clk_int is the division clock or the DLL clock according to whether the division enable signal divide is enabled, and the internal clock ( The duty cycle of the internal clock clk_int is corrected by performing an operation corresponding to the period of clk_int. By this operation, the duty ratio of the data output strobe signal dqs output from the data output strobe signal generating means 30 is close to 50%.

FIG. 2 is a detailed configuration diagram of the clock converting means shown in FIG. 1.

The clock converting means 10 is a delay locked loop (DLL) circuit 110 which generates the DLL clock clk_dll ahead of the external clock clk_ext, and whether the division enable signal is enabled. A clock divider circuit 120 for generating the divided clock clk_div by dividing the external clock clk_ext at a predetermined ratio and the DLL clock clk_dll according to whether or not the division enable signal divide is enabled. Or a clock selector 130 for selectively outputting the divided clock clk_div as the internal clock clk_int.

The DLL circuit 110 transmits the DLL clock clk_dll to the data output strobe signal generating means 30 and the data output buffer so that the timing between the data and the clock is correct when the DLL clock clk_dll is used for the data output operation. Generate the DLL clock (clk_dll) which is out of phase. A general DLL circuit includes a phase splitter to control the phase of the DLL clock to output two clocks having opposite phases. However, the DLL circuit 110 according to the present embodiment does not include a phase splitter and the DLL clock (clk_dll) does not have a phase splitter. ) Print only one.

The clock divider circuit 120 divides the frequency of the external clock (clk_ext) by a preset ratio (for example, 2 times or 4 times) when the frequency divider enable signal is enabled. Create (clk_div). At this time, the divided clock clk_div output from the clock divider circuit 120 is output in a form in which the duty ratio is close to 50%. In general, the clock divider outputs a clock having a duty ratio of approximately 50%, which corresponds to a circuit that can be easily implemented by those skilled in the art.

After that, when the division enable signal divide is enabled, the clock selector 130 outputs the division clock clk_div as the internal clock clk_int, and the division enable signal divide is disabled. The DLL clock clk_dll is output as the internal clock clk_int.

FIG. 3 is a detailed configuration diagram of the data output strobe signal generating unit shown in FIG. 1.

The data output strobe signal generating means 30 controls a phase of the internal clock clk_int transmitted through the transmission means 20 to output a rising clock rclk and a falling clock fclk 310. ), And outputting a corrected rising clock crtrclk by correcting the duty ratio of the rising clock rclk under the control of the n-bit control signal ctrl <1: n> transmitted from the frequency division determining unit 360. The duty cycle of the falling clock fclk is corrected by controlling the duty cycle correction unit 320 and the n-bit control signal ctrl <1: n> transmitted from the frequency division determiner 360. A data output strobe for generating the data output strobe signal dqs by receiving a second duty cycle corrector 330 that outputs a polling clock crtfclk, the corrected rising clock crtrclk, and the corrected polling clock crtfclk. Signal generator 340, the data output The duty cycle controller 350 generates the n bit control signal ctrl <1: n> by receiving the strobe signal dqs and the n bit of the n bit according to whether the division enable signal is enabled. And the division determination unit 360 for controlling a logic value of the control signal ctrl <1: n>.

Here, the phase splitter 310 outputs the rising clock rclk and the falling clock fclk having opposite phases from the internal clock clk_int transmitted from the transmission means 20.

Thereafter, the first duty cycle corrector 320 and the second duty cycle corrector 330 are a high signal and a low signal among the signals included in the n-bit control signal ctrl <1: n>. Low) controls the duty ratios of the rising clock rclk and the falling clock fclk, respectively. For example, as the number of high signals among the n-bit control signals ctrl <1: n> increases, the first duty cycle corrector 320 widens the high section of the rising clock rclk and the low section. The second duty cycle correction unit 330 widens the low period of the polling clock fclk and narrows the high period. Similarly, as the number of low signals among the n-bit control signals ctrl <1: n> increases, the first duty cycle corrector 320 expands the low period and narrows the high period of the rising clock rclk. In operation, the second duty cycle corrector 330 widens the high period of the polling clock fclk and narrows the low period.

The duty cycle controller 350 includes a feedback loop therein to determine the duty cycle of the data output strobe signal dqs, and thereby generate the n-bit control signal ctrl <1: n>. Since the duty cycle of the data output strobe signal dqs is influenced by the correction rising clock crtrclk or the correction polling clock crtfclk, each of the correction rising clock crtrclk and the correction polling clock crtfclk If the duty ratio is not exactly 50%, the duty ratio of the data output strobe signal dqs is also not exactly 50%. Therefore, by determining the duty cycle of the data output strobe signal dqs and generating the n-bit control signal ctrl <1: n>, the n-bit control signal ctrl <1: n>), the duty ratio of the corrected rising clock crtrclk and the corrected falling clock crtfclk can be obtained.

The division determination unit 360 controls a logic value of the n-bit control signal ctrl <1: n> according to whether the division enable signal divide is enabled. When the division enable signal is enabled, the internal clock clk_int is implemented as the division clock clk_div, and thus has a longer period than the DLL clock clk_dll. When the division enable signal is disabled, the internal clock clk_int is implemented as the DLL clock clk_dll, and thus a period is shorter than that of the division clock clk_div. The period of the rising clock rclk and the falling clock fclk follows the period of the internal clock clk_int. Accordingly, the first duty cycle corrector 320 and the second duty cycle corrector 330 perform duty cycle correction operations differently according to periods of the rising clock rclk and the falling clock fclk, respectively.

To this end, the division determination unit 360 determines the period of the internal clock clk_int from the division enable signal diven, and when the division enable signal divide is disabled, the control signal of the n bit. By reducing the number of high signals included in (ctrl <1: n>) at a predetermined ratio, the first duty cycle correction unit 320 and the second duty cycle correction unit 330 differ in duty cycle correction operation. Do it.

4A is a detailed configuration diagram of the first duty cycle correction unit illustrated in FIG. 3, and FIG. 4B is a detailed configuration diagram of the second duty cycle correction unit illustrated in FIG. 3.

As illustrated, the first duty cycle corrector 320 performs a pull-up operation 322 for the driver 326 in response to an input of the n-bit control signal ctrl <1: n>. ), A pull-down unit 324 which performs a pull-down operation on the driving unit 326 in response to an input of the n-bit control signal ctrl <1: n>, and the pull-up unit 322 and the pull-down unit ( The driving unit 326 outputs the corrected rising clock crtrclk by driving the rising clock rclk by receiving power supplied from the power source 324.

Here, the pull-up unit 322 receives the n-bit control signal (ctrl <1: n>) by one bit at a gate terminal, and is parallel between a supply terminal of an external power supply VDD and the driving unit 326. And n first transistors TR1 <1: n>.

The pull-down unit 324 receives the n-bit control signal ctrl <1: n> bit by bit at a gate terminal and is provided in parallel between the supply terminal of the ground power source VSS and the driving unit 326. N second transistors TR2 <1: n>.

The driving unit 326 receives the power supplied from the pull-up unit 322 and the pull-down unit 324 and receives the rising clock rclk from the first inverter IV1 and the first inverter IV1. And a second inverter IV2 that receives an output signal and outputs the corrected rising clock crtrclk.

By such a configuration, the duty ratio correction operation for the rising clock rclk input to the driver 326 is performed. That is, when the number of low signals among the n bits of control signals ctrl <1: n> increases, the pull-up unit 322 supplies power to the first inverter IV1 of the driving unit 326. The amount is increased, so that the high level section of the output signal of the first inverter IV1 is widened. Since the corrected rising clock crtrclk is inverted and output by the second inverter IV2, the low level section is widened.

On the other hand, when the number of high signals among the n-bit control signals ctrl <1: n> is increased, the pull-down unit 324 of the power supplied to the first inverter IV1 of the driving unit 326 The amount is increased, so that the low level section of the output signal of the first inverter IV1 is widened. Since the correcting rising clock crtrclk is inverted and output by the second inverter IV2, the high level section is widened.

The second duty cycle corrector 330 also has the same structure as the first duty cycle corrector 320, but receives the polling clock fclk instead of the rising clock rclk and controls the n bit. The operation of the inverted signal / ctrl <1: n> of the signal ctrl <1: n> may be different from that of outputting the correction polling clock crtfclk instead of the correction rising clock crtrclk. It is only.

Therefore, when the number of low signals among the n bits of control signals ctrl <1: n> increases, the inverted signal / ctrl <1: n> is used, so that the high level of the correction polling clock crtfclk is used. The interval becomes wider, and as the number of high signals among the n bits of control signals ctrl <1: n> increases, the low level interval of the correction polling clock crtfclk becomes wider.

FIG. 5 is a detailed configuration diagram of the duty cycle control unit shown in FIG. 3.

The duty cycle controller 350 compares the phase of the data output strobe signal dqs and the feedback signal fdb to generate a phase comparison signal phcmp and the phase comparison signal phcmp. A delay control unit 353 which generates a delay control signal dlcnt in response to the delay control signal dlcnt, and delays the data output strobe signal dqs by an amount corresponding to the delay control signal dlcnt and inverts it as the feedback signal fdb. An output delay unit 357 for outputting the duty output unit 357 which inverts the data output strobe signal dqs and the feedback signal fdb, and compares a phase thereof to generate a counting enable signal cnten; And a counter 359 for generating the n-bit control signal ctrl <1: n> in response to a counting enable signal cnten.

If the duty ratio of the rising clock rclk and the falling clock fclk is not 50%, the duty ratio of the data output strobe signal dqs is also not 50%. The phase comparison unit 351 compares the phase of the data output strobe signal dqs with the feedback signal fdb delayed and inverted therefrom to determine which of the two signals has a rising edge time. Outputs the phase comparison signal phcmp containing. The delay controller 353 generates the delay control signal dlcnt in response to the phase comparison signal phcmp, and the delay unit 355 generates the data output strobe in response to the delay control signal dlcnt. The delay time is given to the signal dqs.

Thereafter, the duty detector 357 receives the data output strobe signal dqs and the feedback signal fdb, inverts them, and compares the phases of the two signals. The rising edges of the data output strobe signal dqs and the feedback signal fdb are gradually matched by the phase comparator 351, the delay controller 353, and the delay unit 355. . Accordingly, since the data output strobe signal dqs and the feedback signal fdb are inverted and input to the duty detector 357, the falling edges of the two signals input to the duty detector 357 are coincident with each other. . Thereafter, the duty detector 357 compares the rising edges of the two signals and enables the counting enable signal cnten according to the result, so that the counter 359 is inverted the data output strobe signal. The logic value of the n-bit control signal ctrl <1: n> is increased or decreased until the rising edge of dqs matches the rising edge of the inverted feedback signal fdb. As a result, the duty ratios of the data output strobe signal dqs and the feedback signal fdb gradually match, and the duty ratios of the corrected rising clock crtrclk and the corrected falling clock crtfclk coincide. As a result, the duty ratio of the data output strobe signal dqs is corrected.

FIG. 6 is a detailed configuration diagram of the dispensing determination unit shown in FIG. 3.

As illustrated, the frequency division determiner 360 shifts a logical value of the control signal ctrl <1: n> of the plurality of bits according to whether the frequency division enable signal divide is enabled. 362 and a decoder 364 for decoding the output signal of the shift register 362.

The shift register 362 shifts a logic value of the plurality of bits of the control signal ctrl <1: n> to the lower bits by one bit when the division enable signal divide is disabled. For example, when the division enable signal (disven) is disabled when the logic value of the plurality of bits of the control signal (ctrl <1: n>) is (0, 1, 1, 0), the shift register ( 362 outputs a signal whose logic value is (0, 0, 1, 1).

The decoder 364 outputs a signal including a high signal as the plurality of bits of the control signal ctrl <1: n> corresponding to a logic value of a signal transmitted from the shift register 362 to the first signal. The duty cycle corrector 320 and the second duty cycle corrector 330 are transferred to the duty cycle corrector 320. For example, if the logic value of the signal transmitted from the shift register 362 is (0, 1, 1, 0), the signal output from the decoder 364 includes six high signals, and the shift register ( If the logical value of the signal transmitted from 362 is (0, 0, 1, 1), the signal output from the decoder 364 includes three high signals.

By this operation, the division determination unit 360 performs duty cycle correction operations of the rising clock rclk and the falling clock fclk differently depending on whether the division enable signal divide is enabled. The designer uses the first duty cycle corrector 320 and the first duty cycle corrector 320 according to the plurality of bits of the control signal ctrl <1: n> whose logic value is changed according to whether the division enable signal divide is enabled. The operation of the second duty cycle corrector 330 may be tested and a more efficient duty cycle correction operation may be realized by changing the configurations of the shift register 362 and the decoder 364 from the test result.

7 is a block diagram illustrating a configuration of a clock control circuit of a semiconductor memory device according to another embodiment of the present invention.

As shown, the clock control circuit 40 controls the phase of the external clock clk_ext under the control of the division enable signal diven to output a rising clock rclk and a falling clock fclk 40. ), The transmitting means 50 for transmitting the rising clock rclk and the falling clock fclk, and the rising clock rclk transmitted from the transmitting means 50 under the control of the division enable signal diven. And data output strobe signal generation means 60 for correcting the duty cycle of the polling clock fclk and using the same to generate a data output strobe signal dqs.

In general, the DLL circuit includes a phase splitter to output the rising and falling clocks of opposite phases, and the transmission line transfers the rising and falling clocks output from the DLL circuit to the data output buffer and the data output strobe signal generation circuit. do. This embodiment proposes a clock control circuit that can be implemented when such a general DLL circuit is used. To this end, a phase splitter is provided in the clock divider circuit as well as the DLL circuit provided in the clock converting means 40 to output a rising clock and a falling clock as an internal clock, and the data output strobe signal generating means 60 No phase splitter should be provided. All other configurations are the same as those shown and described with reference to Figs.

For the preferred operation of the clock control circuit of the semiconductor memory device of the present invention, the designer generates an internal clock using the clock divider circuit before the DLL circuit operates, and then transfers it to the data output strobe signal generating means. At this time, the internal clock transmitted to the data output strobe signal generating means changes the duty cycle due to the resistance and noise of the transmission line. Subsequently, a duty cycle correction operation on the internal clock is performed to generate an n-bit control signal, and the operation of the first and second duty cycle correction units is controlled to generate a corrected rising clock and a corrected falling clock. After disabling the frequency enable signal, the internal clock is generated from the DLL circuit. The logical value of the control signal of n bits previously generated is changed.

By this operation, the data output strobe signal generating means can take the advantage of presetting the duty cycle correction operation before the DLL circuit operates. That is, the degree of deformation of the duty cycle by the transmission line is determined in advance, and the value of the n-bit control signal is set. If the DLL circuit operates, the logical value of the n-bit control signal is changed after the operation of the DLL circuit. By correcting the cycle, a data output strobe signal having a stable waveform can be generated even at the beginning of operation.

Accordingly, a data output strobe signal having a more accurate enable period can be generated, thereby improving the reliability of the data output operation of the semiconductor memory device. In addition, since the internal clock can be generated using the clock divider circuit even in the DLL off mode, more stable data output operation can be supported.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The clock control circuit and method of the semiconductor memory device of the present invention described above have the effect of improving the reliability of the data output operation by supporting the data output strobe signal having a more accurate enable period for the data output operation.

In addition, the clock control circuit and method of the semiconductor memory device of the present invention, by setting the duty cycle correction operation for the internal clock in advance before the DLL circuit operates, the data output strobe signal having an accurate enable period even at the beginning of operation Has the effect of generating

In addition, the clock control circuit and method of the semiconductor memory device of the present invention generate an internal clock using a clock divider circuit, thereby generating a data output strobe signal having an accurate enable period even in a DLL off mode. .

Claims (48)

Clock converting means for controlling the phase of the external clock and converting the internal clock to an internal clock according to the control of the division enable signal; Transmission means for transmitting the internal clock; And Data output strobe signal generation means for correcting a duty cycle of the internal clock transmitted from the transmission means according to the control of the frequency division enable signal and generating a data output strobe signal using the same; A clock control circuit of a semiconductor memory device comprising a. The method of claim 1, The clock converting means outputs a divided clock obtained by dividing the external clock at a predetermined ratio as the internal clock when the division enable signal is enabled, and outputs a DLL clock as the internal clock when the division enable signal is disabled. And a clock control circuit of the semiconductor memory device. The method of claim 2, The clock conversion means, A delay locked loop (DLL) circuit configured to generate the DLL clock in response to the external clock; A clock divider circuit for generating the divided clock by dividing the external clock at a predetermined ratio according to whether the divided enable signal is enabled; And A clock selector configured to selectively output the DLL clock or the divided clock as the internal clock according to whether the division enable signal is enabled; A clock control circuit of a semiconductor memory device comprising a. The method of claim 3, wherein The DLL circuit and the clock divider circuit further comprises a phase splitter for controlling the phase of each output clock to generate a rising clock and a falling clock, respectively. The method of claim 3, wherein The data output strobe signal generating means determines the period of the internal clock according to whether the division enable signal is enabled, thereby setting the duty cycle correction range of the internal clock and correcting the duty cycle. A clock control circuit of a semiconductor memory device. The method according to claim 1 or 5, The data output strobe signal generating means, A duty cycle controller configured to receive the data output strobe signal and generate a plurality of bits of control signal; A division determination unit that controls a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; A first duty cycle corrector configured to correct a duty ratio of a rising clock and output a corrected rising clock according to the control of the plurality of bits of the control signal transmitted from the division determining unit; A second duty cycle corrector for outputting a corrected polling clock by correcting a duty ratio of a polling clock according to the control of the control signal of the plurality of bits transmitted from the division determining unit; And A data output strobe signal generator configured to receive the corrected rising clock and the corrected falling clock to generate the data output strobe signal; A clock control circuit of a semiconductor memory device comprising a. The method of claim 6, The data output strobe signal generating means further comprises a phase splitter for controlling the phase of the internal clock transmitted through the transmission means to output the rising clock and the falling clock. Circuit. The method of claim 6, The first duty cycle corrector and the second duty cycle corrector control the duty ratios of the rising clock and the falling clock, respectively, according to the number of high and low signals among the signals included in the plurality of bits of the control signal. A semiconductor memory device comprising a clock control circuit. The method of claim 6, And the duty cycle controller includes a feedback loop to determine the duty cycle of the data output strobe signal and to generate the plurality of bits of control signal accordingly. The method of claim 9, The duty cycle control unit, A phase comparator configured to compare a phase of the data output strobe signal and a feedback signal to generate a phase comparison signal; A delay controller configured to generate a delay control signal in response to the phase comparison signal; A delay unit delaying the data output strobe signal as much as the delay control signal, inverting the data output strobe signal, and outputting the inverted signal as the feedback signal; A duty detector for inverting the data output strobe signal and the feedback signal and comparing a phase thereof to generate a counting enable signal; And A counter for generating the plurality of bits of control signal in response to the counting enable signal; A clock control circuit of a semiconductor memory device comprising a. The method of claim 6, And the division determining unit reduces the number of high signals included in the plurality of bits of the control signal by a predetermined ratio when the division enable signal is disabled. The method of claim 11, The dispensing determination unit, A shift register shifting a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; And A decoder for decoding the output signal of the shift register; A clock control circuit of a semiconductor memory device comprising a. Clock converting means for selectively outputting a divided clock or DLL clock obtained by dividing an external clock at a predetermined ratio as an internal clock; And Data output strobe signal generation means for receiving a data output strobe signal and controlling and outputting a duty cycle of the data output strobe signal in response to a cycle of the internal clock; A clock control circuit of a semiconductor memory device comprising a. The method of claim 13, The clock converting means outputs the divided clock as the internal clock when the division enable signal is enabled, and outputs the DLL clock as the internal clock when the division enable signal is disabled. Clock control circuit. The method of claim 14, The clock conversion means, A delay locked loop (DLL) circuit configured to generate the DLL clock in response to the external clock; A clock divider circuit for generating the divided clock by dividing the external clock at a predetermined ratio according to whether the divided enable signal is enabled; And A clock selector configured to selectively output the DLL clock or the divided clock as the internal clock according to whether the division enable signal is enabled; A clock control circuit of a semiconductor memory device comprising a. The method of claim 15, The DLL circuit and the clock divider circuit further comprises a phase splitter for controlling the phase of each output clock to generate a rising clock and a falling clock, respectively. The method of claim 15, The data output strobe signal generating means determines the period of the internal clock according to whether the division enable signal is enabled, thereby setting the duty cycle correction range of the internal clock and correcting the duty cycle. A clock control circuit of a semiconductor memory device. The method according to claim 14 or 17, The data output strobe signal generating means, A duty cycle controller configured to receive the data output strobe signal and generate a plurality of control signals; A division determination unit that controls a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; A first duty cycle corrector configured to correct a duty ratio of a rising clock and output a corrected rising clock according to the control of the plurality of bits of the control signal transmitted from the division determining unit; A second duty cycle corrector for outputting a corrected polling clock by correcting a duty ratio of a polling clock according to the control of the control signal of the plurality of bits transmitted from the division determining unit; And A data output strobe signal generator configured to receive the corrected rising clock and the corrected falling clock to generate the data output strobe signal; A clock control circuit of a semiconductor memory device comprising a. The method of claim 18, And the data output strobe signal generating means further comprises a phase splitter for controlling the phase of the internal clock to output the rising clock and the falling clock. The method of claim 18, The first duty cycle corrector and the second duty cycle corrector control the duty ratios of the rising clock and the falling clock, respectively, according to the number of high and low signals among the signals included in the plurality of bits of the control signal. A semiconductor memory device comprising a clock control circuit. The method of claim 18, And the duty cycle controller includes a feedback loop to determine the duty cycle of the data output strobe signal and to generate the plurality of bits of control signal accordingly. The method of claim 21, The duty cycle control unit, A phase comparator configured to compare a phase of the data output strobe signal and a feedback signal to generate a phase comparison signal; A delay controller configured to generate a delay control signal in response to the phase comparison signal; A delay unit delaying the data output strobe signal as much as the delay control signal, inverting the data output strobe signal, and outputting the inverted signal as the feedback signal; A duty detector for inverting the data output strobe signal and the feedback signal and comparing a phase thereof to generate a counting enable signal; And A counter for generating the plurality of bits of control signal in response to the counting enable signal; A clock control circuit of a semiconductor memory device comprising a. The method of claim 18, And the division determining unit reduces the number of high signals included in the plurality of bits of the control signal by a predetermined ratio when the division enable signal is disabled. The method of claim 23, The dispensing determination unit, A shift register shifting a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; And A decoder for decoding the output signal of the shift register; A clock control circuit of a semiconductor memory device comprising a. a) controlling the phase of the external clock and converting the internal clock to an internal clock according to the control of the division enable signal; b) transmitting said internal clock; And c) correcting the duty cycle of the internal clock transmitted from step b) according to the control of the division enable signal and using the same to generate a data output strobe signal; Clock control method of a semiconductor memory device comprising a. The method of claim 25, In the step a), when the division enable signal is enabled, a division clock divided by the external clock at a predetermined ratio is output as the internal clock, and when the division enable signal is disabled, a DLL clock is output as the internal clock. A clock control method of a semiconductor memory device, characterized in that. The method of claim 26, Step a) is a-1) generating the delay locked loop (DLL) clock in response to the external clock, and generating the divided clock by dividing the external clock at a predetermined ratio according to whether the divided enable signal is enabled; And a-2) selectively outputting the DLL clock or the divided clock as the internal clock according to whether the division enable signal is enabled; Clock control method of a semiconductor memory device comprising a. The method of claim 27, The step a-1) further comprises the step of generating a rising clock and a falling clock by controlling the phase of each output clock clock control method of a semiconductor memory device. The method of claim 27, The step c) determines the period of the internal clock according to whether the division enable signal is enabled, thereby setting the duty cycle correction range of the internal clock and correcting the duty cycle. How to control the clock on your device. The method of claim 25 or 29, C), c-1) receiving the data output strobe signal to generate a plurality of bits of control signal; c-2) controlling a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; c-3) outputting a corrected rising clock and a corrected falling clock by correcting a duty ratio between the rising clock and the falling clock according to the control of the control signal of the plurality of bits transmitted from step c-2); And c-4) generating the data output strobe signal by receiving the corrected rising clock and the corrected falling clock; Clock control method of a semiconductor memory device comprising a. The method of claim 30, And the step c) further includes controlling the phase of the internal clock transmitted through the step b) before the step c-3) to output the rising clock and the falling clock. How to control the clock on your device. The method of claim 30, And c-1) comprises a feedback loop to determine the duty cycle of the data output strobe signal and to generate the control signal of the plurality of bits accordingly. The method of claim 32, Step c-1), c-1- a) comparing a phase of the data output strobe signal and a feedback signal to generate a phase comparison signal; c-1-b) generating a delay control signal in response to the phase comparison signal; c-1-c) delaying and inverting the data output strobe signal as much as the delay control signal and outputting the feedback signal as the feedback signal; c-1-d) inverting the data output strobe signal and the feedback signal and comparing a phase thereof to generate a counting enable signal; And c-1-E) generating the multi-bit control signal in response to the counting enable signal; Clock control method of a semiconductor memory device comprising a. The method of claim 30, And c-2) is a step of reducing the number of high signals included in the plurality of bits of the control signal by a predetermined ratio when the division enable signal is disabled. The method of claim 34, wherein Step c-2), c-2-) shifting a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; And c-2- b) decoding the output signal of the shift register; Clock control method of a semiconductor memory device comprising a. The method of claim 30, In step c-3, the duty cycle of the rising clock and the falling clock is controlled according to the number of the high signal and the low signal among the signals included in the plurality of bits of the control signal. Way. a) selectively outputting, as an internal clock, a divided clock or DLL clock that divides an external clock at a predetermined ratio; And b) receiving a data output strobe signal and controlling and outputting a duty cycle of the data output strobe signal in response to a period of the internal clock; Clock control method of a semiconductor memory device comprising a. The method of claim 37, wherein The step a) includes outputting the divided clock as the internal clock when the division enable signal is enabled, and outputting the DLL clock as the internal clock when the division enable signal is disabled. How to control the clock. The method of claim 38, Step a) is a-1) generating the delay locked loop (DLL) clock in response to the external clock, and generating the divided clock by dividing the external clock at a predetermined ratio according to whether the divided enable signal is enabled; And a-2) selectively outputting the DLL clock or the divided clock as the internal clock according to whether the division enable signal is enabled; Clock control method of a semiconductor memory device comprising a. The method of claim 39, The step a-1) further comprises the step of generating a rising clock and a falling clock by controlling the phase of each output clock clock control method of a semiconductor memory device. The method of claim 39, In the step b), the cycle of the internal clock is determined according to whether the division enable signal is enabled, thereby setting a duty cycle correction range of the internal clock and correcting the duty cycle. How to control the clock on your device. 42. The method of claim 37 or 41 wherein B), b-1) receiving the data output strobe signal and generating a plurality of bits of control signal; And b-2) controlling a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; b-3) correcting the duty ratio between the rising clock and the falling clock according to the control of the control signal of the plurality of bits transmitted from the step b-2) and outputting a correcting rising clock and a correcting falling clock; b-4) receiving the corrected rising clock and the corrected falling clock to generate the data output strobe signal; Clock control method of a semiconductor memory device comprising a. The method of claim 42, And b) controlling the phase of the internal clock to output the rising clock and the falling clock before step b-3). The method of claim 42, B-1) comprises a feedback loop to determine the duty cycle of the data output strobe signal, and to generate the control signal of the plurality of bits according to the step. The method of claim 44, Step b-1), b-1- a) comparing a phase of the data output strobe signal and a feedback signal to generate a phase comparison signal; b-1-b) generating a delay control signal in response to the phase comparison signal; b-1-c) delaying the data output strobe signal by the amount corresponding to the delay control signal and inverting the data output strobe signal to output the feedback signal; b-1-d) inverting the data output strobe signal and the feedback signal and comparing the phases to generate a counting enable signal; And b-1- e) generating the multi-bit control signal in response to the counting enable signal; Clock control method of a semiconductor memory device comprising a. The method of claim 42, B-2) is a step of reducing the number of the high signal included in the control signal of the plurality of bits when the division enable signal is disabled by a predetermined ratio. The method of claim 46, Step b-2), b-2-) shifting a logic value of the control signal of the plurality of bits according to whether the division enable signal is enabled; And b-2-b) decoding the output signal of the shift register; Clock control method of a semiconductor memory device comprising a. The method of claim 43, In step b-3, the duty cycle of the rising clock and the falling clock is controlled according to the number of the high signal and the low signal among the signals included in the plurality of bits of the control signal. Way.

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