TW200409462A - Method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL) - Google Patents

Abstract

A method of single delay line and working-cell number minimization for an all digital delay locking loop (ADDLL) comprises the flow-controlled mechanism for the clock signal and the reversed delay cell arrangement. The present invention provides only one delay line for skew measurement, the matching problem between different delay lines being removed, and reducing the maximum number of active cells and corresponding power consumption after locking.

Description

200409462 V. Description of the invention (l) [Field of the invention] The present invention relates to a type of delay lock circuit with a left-right delay cell, which includes: a delay line and minimizing the effect of the working delay cell, and reducing the work 4 can reduce The manufacturing process consumes β and the complexity of the circuit. [Know-how] The clock signal quality has always been the shadow band q; along with the performance of semiconductor technology; one of the key factors is that the clock signal frequency and the complexity of the chip follow the speed: the quality of the internal clock signal in Lu 2 ' Then, more open = fast ;; ,, = low; clock skew and clock jitter 7 decrease in progress, materials I > cl jck jitter, etc. f = Shinan performance The design of super large integrated circuit or system single chip (soc) is ten: an important issue. Improving the quality of the clock signal can not only support the operating frequency of the second system, but also reduce the chance of system failure, and improve the reliability of the chip. At present, delay locked circuits are widely used to solve the problem of clock signal quality. Recently, many new design methods have been proposed to improve the delay, the performance of the fixed circuit and the quality of the pulse signal. If the lock principle is used to roughly classify, the delay lock circuit can be divided into two types: open circuit and closed circuit. The most typical examples of open-circuit architectures are synchronous mirror delay (SMD) and clock synchronized delay (CSD). The biggest advantage of the open-circuit architecture is that under the condition that the sum of the transfer delay time of the input clock buffer and the output clock driver + device is less than the input clock cycle,

5. Description of the invention (2) It has the ability to be in two external clocks. Because of the open-circuit pole speed lock (that is, to synchronize the phase), this is often used for the memory to have the ability to lock the phase. Due to the delay line and the clock driver, the = η-type architecture requires the matching between the complex line circuits. Personal shadow: Erbu'an circuit diagram. A clock-out clock driver 8 is set in the circuit. 2. One you :: Clock buffer gain 8 1.-Japan Japan system + ^ A duplicate clock delay line 8 3 (input clock buffer and output time Pulse driver), two stops (column clock delay lines 8 4, 8 5 (Meas. R Π ar · delay 1 lne) and a delay mapping circuit 8 6 (delay cii_cui ^ The transmission delay time of the road / ίΐ has been marked in the figure, and when this electricity & temple, the total transmission delay time from input to output will be equal to two input solar periods, that is, one for one. + As in the first As shown in Figure 2, it is a wooden structure of a traditional open-circuit delay lock circuit of type 2. The circuit includes an input clock buffer 9 1, an output clock driver 9 2, and a duplicate clock delay line 9 3 ( Copy only the input clock buffer), two clock delay lines 9 4 and 9 5 (Meas. Delay line and Var. Delay 11ne) arranged in parallel and a delay mapping to synchronize two parallel clock delay lines Circuit 9 6 (de 1 aymirr 〇rcircuit) and an additional twisted inferiority is 9 7 (Skew det ector) and multiplexer 9 8. This traditional open-circuit delay lock circuit

V. Description of the invention (3) Under the same operating conditions, the capacity is changed, but the duplication of the input clock is locked in the two input clock cycles; the number of spots ^ The traditional delay lock circuit must be simultaneously; the rotation of the copy Clock drive; the disadvantages of the driver, eliminating the frame of the late lock circuit; the second is the power consumption. However, in the case of Type 2, the clock delay line needs to be matched and the clock delay line needs to be copied. This way 1 · Because of the following problems in the layout, construction, and limous structure: It is difficult to ensure two: temples: J = JIR drop effect and other factors will be different, which will directly affect the output r-path characteristics-&. And the main i t state phase error and clock jitter of such a differential delay lock circuit

Because of circuit performance. Acceleration lock, so when the delay line and the principle of mapping must be used to complete the lock action at the same time, two (as done in Figure 11> if G k transfer delay time π is not), increase the power consumption of the circuit . [Purpose and Effect] Therefore, the main purpose of the 4 delay line and the minimum chemical industry is to provide a delay lock circuit with a single low process pair delay cell ^: cell 70, which can reduce the complexity. The effect of ^ 'and reduce power consumption and circuit ^ To achieve the above-mentioned purpose, the present invention minimizes the work delay & u, has an early delay line clock signal flow control machine field 2 and late-lock circuit 'Including the transposition of the cell arrangement under the flow control mechanism, under which the delay lock circuit only needs a single-clock delay. Page 7 200409462 V. Description of the invention (4) Line, this single clock The function of delaying the synchronization clock has been removed; 弁;: the measurement of the clock distortion and the reduction of the step-up power consumption; the result is minimized, and at the same time, [the preferred implementation, see the circuit diagram, t, circuit The path diagram of the path and minimize the use of more than one Λ 5 tiger in this cut mode, with the architecture 2, a delay device 5, a multiplexer 6 1 circuit complexity without delay line momentum will also be revised (Shown in Figure 2 of the invention) For details of the example, "The first operation diagram, extension. As shown in the figure, the work is delayed until the input is not obtained by the late mapping, only 6 2 degrees and power s have been good; the delay, when the electrical details are explained] Phase 6 bit map ιΓ7 " The diagram of the present invention, the two-phase anticipatory delayed cell design diagram, and the figure from w ~ / skin shape: The present invention includes the delayed cell input + ~ and we know that one has- Delay-locked circuit, straight main = 15 to make the circuit work in different phases and lock the effect circuit after… to delay at a different clock 堍 1 ^ t control μ t output clock drive control to 3,-timing control unit pulse Buffer 64 and a first, second, and ^ east: composition; by the above composition, the rate consumption I can be expected to be greatly reduced, and at the same time, the detailed operation of the pulse phase structure and the static phase error after the problem is locked The principle will be explained as follows: The lock circuit has two operating phases in total (for example, after the first reset), it sequentially enters the measurement phase 200409462. V. Description of the invention (5) = (Measurement Phase) and fast lock phase

Phase) is locked after two operating phases; and when the present invention is powered, it is necessary to continuously adjust the clock distortion caused by voltage and environmental changes, and additional auxiliary circuits are required to allow this circuit to enter the "maintenance" ) " The only auxiliary circuit is the Xi circuit. Therefore, I will not go into details here, so the electronic phase operation for self-use: the function is-after iG, the two of the circuit of the present invention are as described above. When the phase is measured ( "Μ

Phase) $ to the effect of the lock; Among them, the purpose of measuring phase (measurement of two tau is to measure the internal clock signal (Ck-Int) and external clock signal (Ck- Ext) clock distortion, = 3 The expected waveform of the signal is not in these two phases. When the signal is opened for measurement phase operation, the signal is set to a low level (Smart / The system is used to indicate that the circuit has just started from the initial (/ η 111 a 1) state or the selection signal of the delay cell has been determined. The circuit through which the clock signal passes will be set to an open circuit structure, as shown in Figure 4 (Path i). Finally, the 'internal clock signal will drive a timing control unit composed of flip-flops triggered by some positive edges 4 (Timing control

Unit.), The TDC —Start signal is generated by Ck—Int, and then ck —Ext =, TDC —Stop is sent; therefore, from the timing diagram in Figure 3, we can know 'TDC_Start and TDC — The time difference between the two signals of Stop is the difference between the "clock cycle" and "clock skew (Tci 200409462 V. Description of Invention (6) (Skew))" at the beginning. It is also the clock delay line 1 The required delay time.

The purpose of Fast-Lock Phase is to convert (map) the time difference between the TDC — Start and TDC_Stop signals into the number of delayed cells to generate the required delay time, so that the internal clock signal is locked to the external time Pulse signal. In order to facilitate the description of the operation of the delay mirror circuit 3, we first mark the two output terminals of each delay cell in the variable delay line 1 as D0 ~ Dn and D '~ Dn, Its output selection signal is marked as. A possible design pattern of the delay cell (as shown in Figure 5); the operation of the delay mapping circuit 3 is described as follows: 1. When the delay mapping operation starts—the system is still 0, and the TDC-start signal will enter the delay line. , As shown in Path 2 in Figure 4. 2. When TDC-Stop is at the moment when the signal transitions to a high level, the value will be locked at the output of the delay mapping circuit 3. The relationship between TDC_Start, TDC_S_top and the output of each delayed cell (as shown in Figure 6). In the example in FIG. 6, the outputs of the first three bits of the delay mapping circuit 3 are 1, and the outputs of the remaining bits are 0, indicating that the number of delay cells required is three.

3. The circuit works so far. In the next step, you can use the output multiplexer 61, 6 2 6 3 to select and control the clock signal to output after the required number of elements; State, its turn-out selection signal must first pass through the encoder 5, so that only the third bit is the high level and the rest is the low level.

200409462

5. Description of the invention (7) Output (as shown in the attached table in Figure 6). 4 · When the required number of delay cells is determined, the timing control circuit 4 will set the "/ & / transition to 1, and then end the delay mapping action and enter the locked state. At this time, the static phase error will not exceed A delayed cell transfer time. This phase error can be reduced as the process progresses.

Please refer to "shown in Figs. 7 to 10", which are a circuit diagram of another embodiment of the present invention, a design diagram of a delay line design, an output diagram of a bit translator, and a circuit path diagram of another embodiment. As shown in the figure: the architecture of the delay lock circuit capable of reducing power consumption of the present invention (as shown in FIG. ^); The description of the low power design is as follows: β must first replace the delay cell to a specific composition type, so that Each stage of the delayed cell can select the output of the previous delayed cell or the external clock input. One possible clock delay line 1 design is shown in Figure 8.

Add a set of bit transposers and 7 (bit-reverser) to the output of the encoder of the first new architecture of the first new type. The modified circuit block is shown in Figure 7. The function of the bit transposition device 7 is to retranspose the delayed cell selection signal output by the original programming device 5; the transposition action is to reverse the bit order of the delayed cell selection signal. There are many ways to realize the conversion action. One of the most efficient methods is to use hard-wired. As shown in Fig. 9, the bit% transposition device 7 will make the example in Fig. 6, 200409462. V. Invention description (8), at this time, the path of the clock signal passing through the delay cell is as shown in Fig. 10. As shown. In this way, the clock signal passes the required number of delay cells near the output, and the first few delay cells will remain static to achieve power saving. However, the above are only the preferred embodiments of the present invention, and the scope of implementation of the present invention cannot be limited by this; therefore, simple equivalent changes and modifications made according to the scope of the patent application and the content of the invention specification of the present invention, All should still fall within the scope of the invention patent.

Page 12 200409462 Brief description of the drawings [Simplified description of the drawings The detailed description of other particularly preferred embodiments of the present invention: = With the following reference to the drawings: The Ming will be clearly understood in the diagram t The 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 1st, 1st, and 1st diagrams are circuit diagrams of the present invention. The diagram is a circuit operation phase diagram of the present invention. = ΐ t The expected signal waveforms for the two phases are shown in the circuit diagram of the present invention. The diagram is a design pattern diagram of the delayed cell element of the present invention. The figure is a & diagram of the delayed cytokine output of the present invention. The diagram is a circuit diagram of another embodiment of the present invention. The diagram is a design diagram of the delay line design of the present invention. The figure is an output diagram of the bit transpose device of the present invention. Figure is another embodiment of the present invention-Figure 1 is a conventional open-circuit delay lock circuit. Figure 2 Figure 2 is another conventional open-circuit delay lock = Figure. Copies) Clock Delay Line ·· Output Clock Driver Delay Map Controller Timing Control Unit · Encoder · ···· 2 ·· 3 ·· 4 ·· 5

Page 13 200409462 Schematic description of the first, second, and third multiplexers · · · 61, 62, 63, bit transposers ......... 7 (conventional part ): Input clock buffer ..... 81, 64, 91 Output clock driver ... 82 Copy clock delay line ......... 83 Clock delay line ... ... 8 4, 8 5 Delay Mapping Circuit ......... 86 Output Clock Driver ......... 92

Duplicate clock delay line ......... 9 3 Clock delay line ... 9 4、9 5 Delay mapping circuit ... ..96 Distortion Detector ......... 97 Multiplexer ......... 98

Page 14

Claims (1)

200409462 Scope of patent application 1 · A single delay line and a minimum chemical lockout circuit, which are characterized as follows: • The delay operation of Tian Shenfan is performed during the measurement phase operation (Measurem is mainly used to generate Control of the required size of the clock delay line L Λ Λ 1 _ mesh & μ The control of the size of the clock delay line produced by the mitigation maps to the delay of the required delay cell and locks the thunderbolt. Twisting the clock of the dagger: Twice: the delay line can achieve the purpose of summer measurement and synchronization of the four sizes. 2. The range of item 1 has a single delay line and a delay lock circuit that minimizes the work delay. The delay lock circuit, when the delay lock circuit operates in the phase of the measurement, the clock delay line signal path uses more than one In the evening, the multiplexer controls to temporarily isolate it from the clock delay line. When the circuit operates in the speed-locking phase, the signal path of the clock delay line also uses the multiplexer control to pass it through the clock delay line. . 3. The delay lock circuit with a single delay line and minimizing the working delay cell as claimed in item 1 of the claim range, wherein the control signal for generating the required size of the clock delay line is provided by a timing control unit (Ti mi ng Con t ro 1 Un it) is completed; and among them, the first internal clock signal < ^ 11111 :) positive edge trigger generates Ding 1) (: one 8-7 8): 1; signal, then the first one The first external clock signal after the positive edge of the internal clock signal ([^ 一 £ χ 七) The positive edge of the signal triggers the generation of the TDC — Stop signal; in addition, TDC — Stop and the coded output will trigger together ⑤ / & / Signal. 1 · If the application scope item 1 has a single delay line and minimizes the work delay 200409462 Six patent application scope Delay cell delay key Jing Leiyou makes the mapping = where 'mainly in fast lock phase motion' is caused by delay The mapping circuit (Delay ΜΐΓΓ〇〇 Clrcuit) and the encoder (Enc), the delay mapping circuit is made up of only one „„ / 兀. When the medium number is switched, the forward and reverse 51 interference will be: 2 $, When TDC-StOP signal, the encoder goes further; locked at the output end; and 5. Bits are high-level data types. The output of the circuit is compiled into only single-SC single: delay line and least The delay lock circuit of the delay cell of the chemical work is a six-key reduction circuit. It is characterized by the following: a delay lock circuit that consumes 4% of its power; a rate a: the phase of the delay lock circuit that consumes 在 ^^; h; ; E Vf ^ ^ ^ ^ ^ Hour (Fast ϊ n L · DU controls 5 tigers' and when the fast-lock phase operation occurs, the large delay line circuit will measure the phase operation, and at the same time, , The system maps to the required delayed cell closure; makes fast: 6 ί Delayed extra delay cells can be turned off and achieve the goal of saving power consumption =. Size plus 5 test and synchronization, 6 · If the application scope item 5 is the delay lock of the delayed cells: early :: late and Minimize the work delay. When measuring phase operation, when the delay lock circuit is multiplexed, the signal delay path of the signal delay line is the same as that of the clock delay line. Temporary isolation; and the signal path of the clock delay line is also when the fan is locked in phase operation. Page 16 200409462 6. The scope of the patent application uses the one or more multiplexers to control the clock delay line. 7 · such as The delay lock circuit with a single delay line and minimizing the working delay cell is declared in item 5 of the scope. The timing control unit (Timing Control Uni t) is used to generate the required size of the clock delay line. Completed; and among them, the first internal clock signal (Ck-Int) is triggered to generate a TDC —start signal, and then the first external clock signal (Ck — Ext) after the positive edge of the first internal clock signal ) Positive edge-triggered produce TDC - Stop signal; in addition, TDC st wash compiled output will trigger ⑯ ... co-ed signal a horse. 8. If the delay lock circuit with a single delay line and a minimum chemical delay cell is applied in item 5 of the scope of application, the mapping action in the fast lock phase is mainly performed by a delay mapping circuit (DeiM Mirror Circuit), an encoder ( Enc〇der) and bit-reVe ^ Ser are completed. Among them, the delay mapping circuit is composed of a set of flip-flops. When the TDC-Stop signal transitions, the input data of The output is locked, and the output of the encoder is adjusted to a single bit with a high level; the holy dagger, ^ 4-bit inverter is used to output the _ high bit and The least significant bits are sequentially swapped with each other.卄