TWI277214B - The method for manufacturing thin film transister - Google Patents

The method for manufacturing thin film transister Download PDF

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Publication number
TWI277214B
TWI277214B TW093138294A TW93138294A TWI277214B TW I277214 B TWI277214 B TW I277214B TW 093138294 A TW093138294 A TW 093138294A TW 93138294 A TW93138294 A TW 93138294A TW I277214 B TWI277214 B TW I277214B
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substrate
thin film
gate
film transistor
laser cvd
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TW093138294A
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TW200620671A (en
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Chiang-Hung Tseng
Jia-Pang Pang
Chih-Cheng Lin
Tse Wu
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Innolux Display Corp
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Priority to TW093138294A priority Critical patent/TWI277214B/zh
Priority to US11/301,019 priority patent/US7396705B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C10/00—Solid state diffusion of only metal elements or silicon into metallic material surfaces
    • C23C10/02—Pretreatment of the material to be coated
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/047—Coating on selected surface areas, e.g. using masks using irradiation by energy or particles
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C8/00—Solid state diffusion of only non-metal elements into metallic material surfaces; Chemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
    • C23C8/02—Pretreatment of the material to be coated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • General Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1277214 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種薄膜電晶體之製造方法。 【先前技術】 TFTCThinFilmTmnsister，賴電晶體)是液晶顯示器之基 礎元件。現有薄膜電晶體技術是在玻璃或塑料基板等非單晶片 或單晶片上藉由濺射、化學沉積方法形成電路必須之各種膜， 通過對膜之加工製作積體電路。薄膜電晶體—般採用心或 P-Si製成’以a-Si製程為例，其一般包括：活性層製作、間極 製作、源/没極製作三個步驟，其順序可根據結構之不同而改 變，且每一步驟工序都包括沈積、微影及蝕刻。 如第-圖所示，縣前技術薄膜電晶體之電路製作流程 圖，其包括如下步驟：提供-基板；賴基板進行清洗之後於 基板上鑛-金制；在該金屬虹塗佈光阻紐對其進行曝光 及顯影；將娜狀餘_ ; 卩峨去除曝光後殘留 之光阻。 惟’該先前技術之薄膜電晶體製程過於繁項，活性層製 作、閘極製作、源/汲極製作三個步驟中均包括沈積、郷^ 蝕刻工序’且每-製作步驟都需要具相應功能之沉積設備、微 影設備及蝕刻設備，因此設備成本較高。同時由於基板在各工 站間轉換雜中，產生廢品的解增大，使得成品之良率較低。 1277214 有雲於此’確有必要挺板^ 省製程設似! 有賴㈣縣雜製程，節 " ’提南生產良率之薄膜電晶體之製造方法。 【發明内容】 本發明之目的在於提供一種可有效簡化薄膜電晶體製 私即省製％3 又備成本’提高生產良率之薄膜電晶體之製造方 法。 本發明之_電晶體之製造方法，包杨下步驟：提供一 基板’對該基板進行清洗；在基板上利用雷射修補技術 沉積-由金屬線構成之閘極；於該沉積有_之基板上利用雷 射CVD修補技術形成一閘極氧化物層；在該閘極氧化物層之 上利用雷射CVD修抛術沉積—金麟作為數觀，該數據 線之排佈方向係與_之排佈方向垂直；_雷射cv〇修補 技術沉積源極，該源極係由二條平行金屬線構成，該二金屬線 位於閘極之上方’且其一端與數據線連通；利用雷射cvd修 補技術沉積汲極，該汲極設於閘極之間且與數據線及閘極之二 金屬線間隔一定距離。 相較先前技術，本發明之薄膜電晶體製造方法係利用雷射 CVD的修補方式直接進行電路的沉積，從而省去了傳統薄膜 電晶體製程中薄膜沉積、曝光、蝕刻等步驟，減少了製程設備， 使得設備成本大降低。因薄膜電晶體製程簡化，在被縮減的各 工站中可能產生之問題亦得以避免，產品良率提高。 1277214 【實施方式】 睛參閱第二圖，係、本發明薄膜電晶體製程之流程圖。本 發明揭示之_電晶狀製紗法觀㈣—紐，將基板進 行清洗後利用雷射CVD在基板上進行鍍膜形成。 該基板係-裸板，該清洗步驟係採用基板清洗設備利用清 洗液進行清洗。 該電路沉積轉係_雷射CVD侧对_梅用計算 機程序控制完成，因此可滿足大面積基板之電路沉積。該雷射 CVD修補技術原理係利用雷射能量密度高、與材料作用時升 /皿迅速等特點，來誘導含有預成膜元素之氣體源反應，進而分 解出預成膜元素，並沈積於基板(Substrate)上。將雷射直接投 射於基板上，對基板進行局部加熱或去除基板上原有不利於成 膜之薄層，以實現對基板局部成膜，未被雷射照射之區域因未 達到反應溫度而不能沈積薄膜。 請參閱第三圖至第七圖所示，係本發明薄膜電晶體製程中 利用雷射CVD設備7進行電路沉積之示意圖。該電路沉積包 括如下步驟： 如第三圖所示，在基板丨上沉積一由金屬線構成之閘極2; 如第四圖所示，於該沉積有閘極2之基板i上形成一閘極 氧化物層3; 在該閘極氧化物層3之上沉積一金屬線作為數據線4，該 1277214 數據線4之排佈方向係與閘極2之排佈方向垂直； 如第五圖所示’沉積源極5 ’該源極5係由二條平行金屬 線構成，該二金屬線位於閘極2之切，且其—端與數:線* 連通； ' 如第六圖及第七圖所示，沉積沒極6，該没極6設於間極 5之間且與數據線4及閘極5之二金屬線間隔一定距離。、甲° 該電路沉積亦可按照如下步驟進行： 在基板1上>儿積一由金屬線構成之閘極2 ; 於1^冗積有_ 2之基板i上形成—閘極氧化物層3 ; 在該’氧化物層3之上沉積源極5，該源極5係由二條 平行金屬線構成’該^一金屬線位於閘極2之上方· ' 沉積-金屬線作為數據線4，該數據線4之排佈方向係盘 閑極2之排佈方向垂直，且與源極5之二金屬線之一端相連通| 沉積沒極6 ’舰極6設於_ 5之間且與數據線*及問 極5 ^—金屬線間隔一定距離。 該電路沉積卿叙各魏金祕之寬度、厚度及排佈方 式均係根據實際需要做不同設計。因該沉積動作係通過雷射 CVD設備置就計算她序控制，耻可通過向雷射設 備輸入不@之程序改變該沉積具體步驟之順序，或改變電路金 屬線之排佈。 相較先前技術，本發明之_電晶難造方法翻用雷射 1277214 CVD的修補方式直接進行電路的沉積，從而省去了傳統薄膜-電晶體製程中薄膜沉積、曝光、蝕刻等步驟，簡少了製程設備，' 使得設備成本大降低。因薄膜電晶體製程簡化，在被縮減的各-工站中可能產生的問題亦得以避免，產品良率提高。 綜上所述，本發明確已符合發明專利之要件，爰依法提出 專利申請。惟’以上触者僅為本侧之健實财式，本發 明之範隨不社翁鮮式魏，舉凡熟f本紐藝之人i 援依本發敗精摘狀f歸飾峻化，絲涵蓋於以下申 清專利範圍内。 【圖式簡單說明】 第一圖係先前技術薄膜電晶體之電路製作示意圖。 第二圖係本發明薄膜電晶體製程之流程圖。 第三圖至第七圖係本發_膜電晶體製程中電路沉積之示意 圖0 【主要元件符號說明】 基板 1 閘極 2 閘極氧化物層 3 數據線 4 源極 5 汲極 6 雷射CVD設備 7

Claims (1)

1277214 十、申請專利範圍： l 一種薄膜電晶體之製造方法，包括如下步驟·· 提供一基板； 將該基板進行清洗； 在基板上利用雷射CVD修補技術沉積一由金屬線構成之閘極； 於該沉積有閘極之基板上利用雷射CVD修補技術形成一閘極 氧化物層； 在該閘極氧化物層之上利用雷射CVD修補技術沉積一金屬線 作為數據線，該數據線之排佈方向係與閘極之排佈方向垂直； 利用雷射CVD修補技術沉積源極，該源極係由二條平行金屬線 構成，該二金屬線位於閘極之上方，且其一端與數據線連通； 利用雷射CVD修補技術沉積汲極，該汲極設於閘極之間且與數 據線及閘極之二金屬線間隔一定距離。 2·如申請專利範圍第1項所述之薄膜電晶體之製造方法，其中電 路沉積之步驟係利用雷射CVD設備進行。 3·如申請專利範圍第1項所述之薄膜電晶體之製造方法，其中其 中利用該雷射CVD 備在基板上進行電路沉積之步驟係通過 計算機程序控制完成。 4. 如申請專利範圍第i項所述之薄膜電晶體之製造方法，其中該 基板係一裸板。 5. 如申請專利範圍第i項所述之薄膜電晶體之製造方法，其中該 基板之清洗雜基板清洗設備巾_清絲進行清洗。’、 11 1277214 七、指定代表圖： (一) 本案指定代表圖為：第（二）圖。 (二) 本代表圖之元件符號簡單說明： 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式：
TW093138294A 2004-12-10 2004-12-10 The method for manufacturing thin film transister TWI277214B (en)

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US11/301,019 US7396705B2 (en) 2004-12-10 2005-12-12 Method for manufacturing a thin film transistor

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US20110033638A1 (en) * 2009-08-10 2011-02-10 Applied Materials, Inc. Method and apparatus for deposition on large area substrates having reduced gas usage
EP4118034A4 (en) * 2020-03-10 2024-05-01 National University of Singapore SEED LAYER, HETEROSTRUCTURE COMPRISING THE SEED LAYER AND METHOD FOR FORMING A LAYER OF MATERIAL USING THE SEED LAYER
CN113355745A (zh) * 2021-05-21 2021-09-07 陕西宇腾电子科技有限公司 一种薄膜电晶体电特性优化方法

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US4681640A (en) * 1986-08-06 1987-07-21 The United States Of America As Represented By The Secretary Of The Army Laser-induced chemical vapor deposition of germanium and doped-germanium films
JPH0799791B2 (ja) * 1992-04-15 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 透明基板上の回路ライン接続方法
TW297950B (zh) 1994-12-16 1997-02-11 Handotai Energy Kenkyusho Kk
US5623160A (en) * 1995-09-14 1997-04-22 Liberkowski; Janusz B. Signal-routing or interconnect substrate, structure and apparatus
JP3460170B2 (ja) 1997-02-03 2003-10-27 シャープ株式会社 薄膜トランジスタ及びその製造方法

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