TWI268553B - A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing - Google Patents

A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Info

Publication number
TWI268553B
TWI268553B TW094128198A TW94128198A TWI268553B TW I268553 B TWI268553 B TW I268553B TW 094128198 A TW094128198 A TW 094128198A TW 94128198 A TW94128198 A TW 94128198A TW I268553 B TWI268553 B TW I268553B
Authority
TW
Taiwan
Prior art keywords
gate dielectric
modifying
dielectric stack
plasma
layer
Prior art date
Application number
TW094128198A
Other languages
English (en)
Chinese (zh)
Other versions
TW200618091A (en
Inventor
Hiroaki Niimi
Luigi Colombo
Koji Shimomura
Takuya Sugawara
Tatsuo Matsudo
Original Assignee
Tokyo Electron Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd, Texas Instruments Inc filed Critical Tokyo Electron Ltd
Publication of TW200618091A publication Critical patent/TW200618091A/zh
Application granted granted Critical
Publication of TWI268553B publication Critical patent/TWI268553B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/20—Diffusion for doping of insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Landscapes

  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW094128198A 2004-08-18 2005-08-18 A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing TWI268553B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/920,990 US7163877B2 (en) 2004-08-18 2004-08-18 Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Publications (2)

Publication Number Publication Date
TW200618091A TW200618091A (en) 2006-06-01
TWI268553B true TWI268553B (en) 2006-12-11

Family

ID=35431477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094128198A TWI268553B (en) 2004-08-18 2005-08-18 A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Country Status (6)

Country Link
US (1) US7163877B2 (https=)
JP (1) JP4950888B2 (https=)
KR (1) KR101163264B1 (https=)
CN (1) CN100568462C (https=)
TW (1) TWI268553B (https=)
WO (1) WO2006023373A1 (https=)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005086215A1 (ja) * 2004-03-03 2005-09-15 Tokyo Electron Limited プラズマ処理方法及びコンピュータ記憶媒体
US20070049048A1 (en) * 2005-08-31 2007-03-01 Shahid Rauf Method and apparatus for improving nitrogen profile during plasma nitridation
EP2020911A4 (en) 2006-05-13 2011-07-27 Tensys Medical Inc CONTINUOUS POSITIONING DEVICE AND METHOD
WO2007132884A1 (ja) * 2006-05-17 2007-11-22 Hitachi Kokusai Electric Inc. 半導体装置の製造方法および基板処理装置
WO2009048602A1 (en) 2007-10-12 2009-04-16 Tensys Medical, Inc. Apparatus and methods for non-invasively measuring a patient's arterial blood pressure
US7964515B2 (en) * 2007-12-21 2011-06-21 Tokyo Electron Limited Method of forming high-dielectric constant films for semiconductor devices
US20090233430A1 (en) * 2008-02-19 2009-09-17 Hitachi-Kokusai Electric In. Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, and semiconductor device manufacturing system
US8193586B2 (en) * 2008-08-25 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Sealing structure for high-K metal gate
US20100044804A1 (en) * 2008-08-25 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Novel high-k metal gate structure and method of making
US8252653B2 (en) 2008-10-21 2012-08-28 Applied Materials, Inc. Method of forming a non-volatile memory having a silicon nitride charge trap layer
US8198671B2 (en) * 2009-04-22 2012-06-12 Applied Materials, Inc. Modification of charge trap silicon nitride with oxygen plasma
US8962454B2 (en) * 2010-11-04 2015-02-24 Tokyo Electron Limited Method of depositing dielectric films using microwave plasma
KR101893471B1 (ko) * 2011-02-15 2018-08-30 어플라이드 머티어리얼스, 인코포레이티드 멀티존 플라즈마 생성을 위한 방법 및 장치
US9655530B2 (en) 2011-04-29 2017-05-23 Tensys Medical, Inc. Apparatus and methods for non-invasively measuring physiologic parameters of one or more subjects
KR101241049B1 (ko) 2011-08-01 2013-03-15 주식회사 플라즈마트 플라즈마 발생 장치 및 플라즈마 발생 방법
KR101246191B1 (ko) * 2011-10-13 2013-03-21 주식회사 윈텔 플라즈마 장치 및 기판 처리 장치
US8890264B2 (en) * 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
US9224644B2 (en) * 2012-12-26 2015-12-29 Intermolecular, Inc. Method to control depth profiles of dopants using a remote plasma source
US9343291B2 (en) * 2013-05-15 2016-05-17 Tokyo Electron Limited Method for forming an interfacial layer on a semiconductor using hydrogen plasma
US9331168B2 (en) 2014-01-17 2016-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacuturing method of the same
CN104821276B (zh) * 2014-01-30 2018-08-10 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制作方法
US20170084464A1 (en) * 2015-09-18 2017-03-23 Tokyo Electron Limited Germanium-containing semiconductor device and method of forming
JP6671166B2 (ja) * 2015-12-15 2020-03-25 東京エレクトロン株式会社 絶縁膜積層体の製造方法
US11152214B2 (en) * 2016-04-20 2021-10-19 International Business Machines Corporation Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device
TWI635539B (zh) * 2017-09-15 2018-09-11 Corremax International Co., Ltd. 高介電常數介電層、其製造方法及執行該方法之多功能設備
KR102384865B1 (ko) 2018-01-31 2022-04-08 삼성전자주식회사 반도체 소자 제조 방법
CN108735607A (zh) * 2018-05-25 2018-11-02 中国科学院微电子研究所 基于微波等离子体氧化的凹槽mosfet器件的制造方法
US20210057215A1 (en) * 2019-05-03 2021-02-25 Applied Materials, Inc. Treatments to enhance material structures
US12249511B2 (en) * 2019-05-03 2025-03-11 Applied Materials, Inc. Treatments to improve device performance
US11417517B2 (en) * 2019-05-03 2022-08-16 Applied Materials, Inc. Treatments to enhance material structures
TWI837538B (zh) * 2020-11-06 2024-04-01 美商應用材料股份有限公司 增強材料結構的處理
JP7587716B2 (ja) * 2021-03-04 2024-11-20 アプライド マテリアルズ インコーポレイテッド デバイスのパフォーマンスを向上させるための処理

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05221644A (ja) * 1992-02-13 1993-08-31 Matsushita Electric Ind Co Ltd 酸化タンタル薄膜の製造方法
JP3230901B2 (ja) * 1993-06-22 2001-11-19 株式会社東芝 半導体装置の製造方法及びその製造装置
JPH0964307A (ja) * 1995-08-29 1997-03-07 Hitachi Ltd 酸化物薄膜の熱処理方法
US6709715B1 (en) * 1999-06-17 2004-03-23 Applied Materials Inc. Plasma enhanced chemical vapor deposition of copolymer of parylene N and comonomers with various double bonds
ATE514181T1 (de) * 2000-03-13 2011-07-15 Tadahiro Ohmi Verfahren zur ausbildung eines dielektrischen films
WO2002001622A2 (en) * 2000-06-26 2002-01-03 North Carolina State University Novel non-crystalline oxides for use in microelectronic, optical, and other applications
US6677254B2 (en) 2001-07-23 2004-01-13 Applied Materials, Inc. Processes for making a barrier between a dielectric and a conductor and products produced therefrom
JP4643884B2 (ja) 2002-06-27 2011-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100493022B1 (ko) 2002-07-10 2005-06-07 삼성전자주식회사 Ｓｏｎｏｓ 구조를 갖는 불휘발성 메모리 소자의 제조 방법
WO2004030049A2 (en) * 2002-09-27 2004-04-08 Tokyo Electron Limited A method and system for etching high-k dielectric materials
US6730566B2 (en) * 2002-10-04 2004-05-04 Texas Instruments Incorporated Method for non-thermally nitrided gate formation for high voltage devices
US6649538B1 (en) * 2002-10-09 2003-11-18 Taiwan Semiconductor Manufacturing Co. Ltd. Method for plasma treating and plasma nitriding gate oxides
US6689675B1 (en) * 2002-10-31 2004-02-10 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
JP2006505954A (ja) 2002-11-08 2006-02-16 アヴィザ テクノロジー インコーポレイテッド 高ｋ誘電体の窒化物形成
US6787440B2 (en) 2002-12-10 2004-09-07 Intel Corporation Method for making a semiconductor device having an ultra-thin high-k gate dielectric
JP2004228355A (ja) * 2003-01-23 2004-08-12 Seiko Epson Corp 絶縁膜基板の製造方法、絶縁膜基板の製造装置及び絶縁膜基板並びに電気光学装置の製造方法及び電気光学装置
KR20060054387A (ko) * 2003-08-04 2006-05-22 에이에스엠 아메리카, 인코포레이티드 증착 전 게르마늄 표면 처리 방법
JP4280686B2 (ja) * 2004-06-30 2009-06-17 キヤノン株式会社 処理方法

Also Published As

Publication number Publication date
TW200618091A (en) 2006-06-01
US20060040483A1 (en) 2006-02-23
JP2008510319A (ja) 2008-04-03
KR20080009675A (ko) 2008-01-29
CN101006566A (zh) 2007-07-25
JP4950888B2 (ja) 2012-06-13
CN100568462C (zh) 2009-12-09
US7163877B2 (en) 2007-01-16
KR101163264B1 (ko) 2012-07-05
WO2006023373A1 (en) 2006-03-02

Similar Documents

Publication Publication Date Title
TWI268553B (en) A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing
ATE514181T1 (de) Verfahren zur ausbildung eines dielektrischen films
TW200717651A (en) Method and system for forming a high-k dielectric layer
TW200517524A (en) Processing apparatus and method
WO2010014380A3 (en) Within-sequence metrology based process tuning for adaptive self-aligned double patterning
TW200509246A (en) Plasma apparatus, gas distribution assembly for a plasma apparatus and processes therewith
TW200737026A (en) Transforming metrology data from a semiconductor treatment system using multivariate analysis
TW200500498A (en) Method for etching an aluminum layer using an amorphous carbon mask
ATE174538T1 (de) Hydrophile filme durch plasmapolymerisation
TWI265569B (en) Plasma processing method
WO2006038990A3 (en) Method for treating a substrate
TW200623425A (en) Method of forming at least one thin film device
TW200505631A (en) Method and apparatus for local polishing control
WO2005062345A3 (en) A method of forming a silicon oxynitride layer
WO2006083380A3 (en) Method for fabricating a semiconductor device
TW200704815A (en) Method for producing silicon oxide film, control program thereof, recording medium and plasma processing apparatus
TW200618110A (en) Method of forming a transistor having a dual layer dielectric
TW428328B (en) Fabricating method of thin film transistor
TW200725695A (en) Method for manufacturing semiconductor device
TW200501225A (en) Method and apparatus for bilayer photoresist dry development
TW200717654A (en) Multi-source method and system for forming an oxide layer
GB2434687B (en) Thin film transistor array substrate system and method for manufacturing
TW200717686A (en) Apparatus and method for treating substrate
TW200701372A (en) Method of forming nanoclusters
TW200512788A (en) Method of fabricating thin film transistor (TFT) array

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees