TWI263219B - Semiconductor memory device and control method thereof - Google Patents

Semiconductor memory device and control method thereof

Info

Publication number
TWI263219B
TWI263219B TW092129958A TW92129958A TWI263219B TW I263219 B TWI263219 B TW I263219B TW 092129958 A TW092129958 A TW 092129958A TW 92129958 A TW92129958 A TW 92129958A TW I263219 B TWI263219 B TW I263219B
Authority
TW
Taiwan
Prior art keywords
read
write
address
memory device
semiconductor memory
Prior art date
Application number
TW092129958A
Other languages
English (en)
Other versions
TW200410253A (en
Inventor
Hiroyuki Takahashi
Original Assignee
Nec Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Electronics Corp filed Critical Nec Electronics Corp
Publication of TW200410253A publication Critical patent/TW200410253A/zh
Application granted granted Critical
Publication of TWI263219B publication Critical patent/TWI263219B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
TW092129958A 2002-10-29 2003-10-28 Semiconductor memory device and control method thereof TWI263219B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002314327A JP4236903B2 (ja) 2002-10-29 2002-10-29 半導体記憶装置及びその制御方法

Publications (2)

Publication Number Publication Date
TW200410253A TW200410253A (en) 2004-06-16
TWI263219B true TWI263219B (en) 2006-10-01

Family

ID=32105372

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092129958A TWI263219B (en) 2002-10-29 2003-10-28 Semiconductor memory device and control method thereof

Country Status (4)

Country Link
US (2) US6930945B2 (zh)
JP (1) JP4236903B2 (zh)
KR (1) KR20040038740A (zh)
TW (1) TWI263219B (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4731730B2 (ja) * 2001-06-04 2011-07-27 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP4236901B2 (ja) * 2002-10-23 2009-03-11 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及びその制御方法
US20050289293A1 (en) * 2004-06-28 2005-12-29 Parris Michael C Dual-port DRAM cell with simultaneous access
JP2006092640A (ja) * 2004-09-24 2006-04-06 Sanyo Electric Co Ltd メモリ
US7403446B1 (en) 2005-09-27 2008-07-22 Cypress Semiconductor Corporation Single late-write for standard synchronous SRAMs
JP2007157296A (ja) * 2005-12-08 2007-06-21 Toshiba Corp 半導体記憶装置
US7492656B2 (en) * 2006-04-28 2009-02-17 Mosaid Technologies Incorporated Dynamic random access memory with fully independent partial array refresh function
JP2007312300A (ja) * 2006-05-22 2007-11-29 Matsushita Electric Ind Co Ltd データ転送システム及びデータ処理装置
JP2009238332A (ja) * 2008-03-27 2009-10-15 Renesas Technology Corp 半導体記憶装置
US8004907B2 (en) * 2009-06-05 2011-08-23 Freescale Semiconductor, Inc. SRAM with read and write assist
JP2010282511A (ja) * 2009-06-05 2010-12-16 Elpida Memory Inc メモリモジュール及びこれを備えるメモリシステム
US8174881B2 (en) * 2009-11-24 2012-05-08 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor device
JP5430484B2 (ja) * 2010-04-15 2014-02-26 ルネサスエレクトロニクス株式会社 半導体記憶装置、及びその制御方法
US8723329B1 (en) * 2013-03-15 2014-05-13 Invensas Corporation In-package fly-by signaling
DE102014106909B4 (de) * 2014-05-16 2019-08-14 Infineon Technologies Ag Verfahren zum Zugreifen auf einen Speicher und Speicherzugriffsschaltung
US20160306569A1 (en) * 2015-02-25 2016-10-20 Kabushiki Kaisha Toshiba Memory system
US9928895B2 (en) * 2016-02-03 2018-03-27 Samsung Electronics Co., Ltd. Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof
US9959921B2 (en) * 2016-04-01 2018-05-01 Micron Technology, Inc. Apparatuses and methods for refresh control
US10475492B1 (en) * 2018-07-27 2019-11-12 Macronix International Co., Ltd. Circuit and method for read latency control
US10892764B1 (en) * 2020-08-14 2021-01-12 Winbond Electronics Corp. Delay locked loop device and update method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2653689B2 (ja) 1987-12-21 1997-09-17 テキサス インスツルメンツ インコーポレイテツド ランダムアクセスメモリおよびその書込み／読取り方法
JPH03263685A (ja) 1990-03-13 1991-11-25 Nec Corp ダイナミックランダムアクセスメモリ
KR100317195B1 (ko) * 1998-10-28 2002-02-28 박종섭 반도체메모리의리프레쉬제어회로
US6151236A (en) 2000-02-29 2000-11-21 Enhanced Memory Systems, Inc. Enhanced bus turnaround integrated circuit dynamic random access memory device
JP2001357670A (ja) * 2000-04-14 2001-12-26 Mitsubishi Electric Corp 半導体記憶装置
JP4201490B2 (ja) * 2000-04-28 2008-12-24 富士通マイクロエレクトロニクス株式会社 自動プリチャージ機能を有するメモリ回路及び自動内部コマンド機能を有する集積回路装置

Also Published As

Publication number Publication date
US6930945B2 (en) 2005-08-16
US6977859B2 (en) 2005-12-20
JP2004152349A (ja) 2004-05-27
JP4236903B2 (ja) 2009-03-11
US20050152201A1 (en) 2005-07-14
KR20040038740A (ko) 2004-05-08
TW200410253A (en) 2004-06-16
US20040079968A1 (en) 2004-04-29

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees