TWI254982B - Method for forming gate oxide in semiconductor device - Google Patents

Method for forming gate oxide in semiconductor device Download PDF

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TWI254982B
TWI254982B TW092135384A TW92135384A TWI254982B TW I254982 B TWI254982 B TW I254982B TW 092135384 A TW092135384 A TW 092135384A TW 92135384 A TW92135384 A TW 92135384A TW I254982 B TWI254982 B TW I254982B
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film
gate oxide
oxide film
forming
semiconductor device
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TW200423237A (en
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Byoung-Hee Cho
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Non-Volatile Memory (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Description

1254982 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於再彡士、 用於形成—半導體裝置之一開極氧介 物溥膜之方法，而且更明墟上々 y ^ 確§之，係關於—種用於形成能 夠減少截留於該氧化物薄膜令 丁叼甩千及電洞數量的一本違 體裝置之-閑極氧化物薄膜之方法。 【先前技術】 一電性可抹除可程式快閃 作之時需要一古^隐肢早疋在程式化或抹除操 夕舌 β B i。具㈣高電虔的程式化及抹除摔作 之重複導致在該快閃#丨陰赌时一 ^ ^ + α ^ ^早兀的閘極氧化物薄膜中發生 电子及電洞截留。進而，截 截邊於該閘極氧化物薄膜中的電 及^ ^偏移施加於該單元間 竽聱穸斗儿Ώ Τ心闸枝^ Μ。例如，如將 截留電抹除操作重複1MGG至丨，_，_次，則該等 α私何矛、積偏移該單元之臨限電壓。 :精由使用1氧化物薄膜而減少在該 電荷截留。即，可蕻w ^ 寻m Ϋ的 肖由形成一陶來抑制該等電荷截留 ^ 輕障層之形成係在生長該氧 Ν20或Ν，#挪二+ H导腰之k措由 行。^ 矽基板方向上組合-氧化物與氮來進 是在泫快閃單元的情況下，在 電流。+ 在相極之二端均發生 物鱼”戶斤 在㈣方向上之電荷截留受到由該氧化 方向上卜成的阻障層抑制，但並不能抑制在該多晶石夕 的阻障。：何截留，因為此處沒有由該氧化物與氮所形成 17，在該基板方向上的電荷截留受到抑制，但在
〇 '%\9〇〇93 DOC 1254982 該多晶矽方向上的電荷戴留並未受到抑制。 現在，將參考圖1A至丨C對形成一閘極氧化物薄膜之一傳 統方法進行說明。 如圖1A中所示，在該半導體基板1〇上實施用於控制一單 ，之臨限電壓之一井形成程序及一離子植入程序。接下 來藉由使用一氧化程序而形成一閘極氧化物薄膜2〇，然 後，在該閘極氧化物薄膜20之上形成一多晶矽薄膜3〇。 參考圖1B，在該多晶石夕薄膜3〇之上形成一氮化物薄膜· 圖1C為^兄明藉由實行用於形成一裝置隔離薄膜之一圖案 ^狂序、一自我對準接觸氧化程序、一HDP氧化物薄膜埋 藏程序以及一氮化物薄膜移除程序，而形成該閘極氧化物 2〇與一裝置隔離薄膜之一狀態之一斷面圖。 如以上說明，在該傳統方法的情況下，電流發生於該問 極之二端。因& ’儘管在該矽方向上之電荷截留受到由該 ，化物與該氮所形成的阻障之抑制’但並不能抑制在該多 晶石夕方向上的電荷截留’因為此處沒有由該氧化物與氮所 形成的阻障。#，在該基板方向上的電荷截留受到抑制， 但在該多晶矽方向上的電荷截留並不受抑制。 【發明内容】 本舍明係關於一種一半導體裝 &乳’丨G初潯膜之； 法，該閘極氧化物薄膜能夠抑制在一多晶矽方向上之_ 荷截留以及抑制在一半導體基板方向上一— 〜 兒何截留。 本發明之一方面係提供一種用於形成一半導體裝置之— 開極氧化物薄膜之方法’其包含以下步驟：在導體違
0 ' 9〇\90093 DOC 1254982 板上連續形成—閘極氧 礼化物溥騃及一多晶矽薄膜；對包括 該閘極氧化物薄膜盥兮少a 、/、α亥夕日日矽溥膜之半導體基板實行一氮 離子植入鞋库·每· /- . ^ 貝仃…處理程序以藉由在該半導體基板 與該閘極氧化物薄膜 八品老 一 、之間之一"面處，以及在該閘極氧化
物薄膜與該多晶矽薄M 、4之一"面處的氧化物與氮组合 來形成阻障層；以及扃 曰 ^ 、 Μ夕日日夕潯膜上形成一氮化物薄膜。 在依據本發明之另_具體實施例而形成—半導體之一閉 極氧化物薄膜之_古 方法的上述内容中，藉由一 RTp火花退火 序而貫行該熱處理程序。 在依據本發明之另_具體實施例而形成—半導體之一閉 極氧化物㈣之_方法的上述内容中，藉由使用包括矿或 N2之/原乳體亚以1E14個原子/_2至1£16個原子,咖2之 Μ里與1 keV至2G keV之-植人能量來實行該氮離子植 入程序。 在依據本發明之另_具體實施例而形成—半導體之一問 極^化物薄膜之—方法的上述内容中，該咖火花退火程序 <丁、戶、订於N风體環境中，—斜波充電溫度為約⑽。〇 t ’而ό亥RTP溫度為9⑻。匚至h〇〇〇c。 【實施方式】 現在將*考附圖詳細說明本發明的較佳具體實施例。 圖2A至2D係用於解說用於依據本發明形成一半導體擎 置之一閘極氧化物之一方法之斷面圖。 如圖2 A中所不，在一半導體基板1 0上實施用於控制一單 元之臨限私壓之一井形成程序與一離子植入程序。接下
〇 .9〇\9〇〇Q3 DOC 1254982 來藉由使用一氧化程序而形成一閘極氧化物薄膜2〇， 後’在該閘極氧化物薄膜2〇之上形成一多晶矽薄膜3〇。 圖2B係說明一狀態之一斷面圖，該狀態係實施一氮離子 植入程序以在該多晶矽薄膜3〇與該閘極氧化物薄膜2〇之間 的介面處植入該氮離子，然後，在一 K氣體環境中實行一 快速熱處理（rapid thermal processmg ; RTP)。藉由該熱處理 程序，該氮與該氧化物在該半導體基板1〇與該閘極氧化物 薄膜2 0之間的介面處以及在該多晶㈣膜3 G與該閘極氧化 物薄膜20之間的介面處反應，以形成阻障層。藉此，在該 半導體基板方向上的電荷截留以及在該多晶矽方向上的電 荷截留受到抑制。藉由使用包括N%ilN2 +之—源氣體並以 1EM個原子/cm^1E16個原子之一劑量與i ㈣ 之：植入能量來實行該氮離子植入程序。藉由使用一㈣ 火花退火程序來實施該熱處理程序。在氣體環境中實 仃該RTP火花退火程序，一斜波充電溫度為約^⑻。。秒，而 該RTP溫度為9〇〇。(：至U〇〇cC。 在二方向上形成之阻障層作為對該等電子及該 留（其在該快閃單元上葙式# 平几上式化及抹除操作之時發生於一 向上）之阻障而發揮作用，以 疋』犯有效避兄施加於該單 閘極之閘極電壓之偏移。 參考圖2C，在該多晶矽薄膜 、 之上开》成一氮化物薄膜4( 圖4 D係說明藉由實行用 Λ仃用於形成—裝置隔離薄膜之一圖 化程序、一自我對準接觸 + 虱化辁序、一 HDP氧化物薄膜j 臧私序以及一氮化物薄膜 秒除狴序，而形成該閘極氧1
0 90\9G〇93 D0C 1254982 物20與一裝置隔離薄膜50之一狀態之一斷面圖。 如以上說明，依據本發明，可能藉由使用因該氧化物與 成氮之反應而在二方向上形成的阻障層而減少因在一 NAND快閃記憶體單元程式化及抹除操作之時該閘極氧化 物中的電流而發生的截留電荷量，從而能夠抑制該臨限電 壓之偏移。 藉由使用在二方向上之阻障層而避免該單元臨限電壓之 偏移’其導致在該等程式化及抹除操作重複時保持該單元 之均勻特徵，從而可改進與該等程式化及抹除操作相關聯 之特徵。 此外，在一 NAND快閃記憶體之情況下，由於一熱處理程 序而產生一氧化增強擴散效應（oxidation-enliaiiced diffusion ; 〇ED)，該熱處理程序係在該圖案化程序之前實 知’以在用於形成一 P型井並控制該單元之臨限電壓之離子 植入程序之後形成一裝置隔離薄膜。可將該RTP火花退火程 序作為該N2熱處理程序而實行以組合在該閘極氧化物薄膜 中的氧化物與氮，而藉此減小該0ED效應，從而可獲得該 單元之一均勻臨限電壓。 【圖式簡單說明】 圖1A至1C係用於解說依據一傳統方法形成一半導體裝 置之一閘極氧化物之一方法之斷面圖。 圖2A至2D係用於解說依據本發明形成一半導體裝置之 一閘極氧化物之一方法之斷面圖。 【圖式代表符號說明】 〇； \90\90093.doc 1254982 10 半 導 體 基板 20 閘 極 氧 化 物 薄膜 30 多 晶 矽 薄 膜 40 氮 化 物 薄 膜 50 裝 置 隔 離 薄 膜 O:\90\90093 DOC -10-

Claims (1)

125498®135384號專利申請案 中文申睛專利範圍替換本(95年〗月） 拾、申請專利範圍·· 種用於形成一丰導辦妒署夕 法，其包含以下步驟： 千¥體衣置之-閘極氧化物薄膜之方 在 半導體基板上連續形成_ Μ極氧化物 晶石夕薄膜； 薄膜及一多 對，括該閘極氧化物薄膜與該多晶石夕薄膜之該半導體 基板實行一氮離子植入程序； 實行-熱處理程序以藉由在該半導體基板與該間極氧 化物薄膜之間之-介面處以及在該閘極氧化㈣膜與該 多晶石夕薄膜之間之-介面處的氧化物與氮之組合而形成 阻障層；以及 在該多晶矽薄膜上形成一氮化物薄膜。 2.如申請專利範圍第丨項之形成一半導體裝置之一閘極氧 化物薄膜之方法，#中藉由一 RT ρ火花退火程序而實行該 熱處理程序。 3 ·如申请專利範圍第1項之形成一半導體裝置之一閘極氧 化物薄膜之方法，其中藉由使用包括Νκ之一源氣體 並以1E14個原子/cm2至iE16個原子/cm2之一劑量與i让〜至⑼ keV之一植入能量來實行該氮離子植入程序。 4.如申請專利範圍第2項之形成一半導體裝置之一閘極氧 化物薄膜之方法，其中在一 ％氣體環境中實行該RTp火花 退火程序，一斜波充電溫度為約1〇〇〇c/秒，而該RTp溫度 為 900°C至 1100°C。 O:\90\90093-950116.DOC
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US7314812B2 (en) * 2003-08-28 2008-01-01 Micron Technology, Inc. Method for reducing the effective thickness of gate oxides by nitrogen implantation and anneal
KR100537554B1 (ko) * 2004-02-23 2005-12-16 주식회사 하이닉스반도체 반도체 소자의 산화막 형성 방법
US7619926B2 (en) * 2007-03-29 2009-11-17 Sandisk Corporation NAND flash memory with fixed charge
US7732275B2 (en) * 2007-03-29 2010-06-08 Sandisk Corporation Methods of forming NAND flash memory with fixed charge
KR100894764B1 (ko) * 2007-10-10 2009-04-24 주식회사 하이닉스반도체 반도체 소자의 제조 방법
CN109494224B (zh) * 2017-09-08 2020-12-01 华邦电子股份有限公司 非挥发性存储器装置及其制造方法

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US5851893A (en) * 1997-07-18 1998-12-22 Advanced Micro Devices, Inc. Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection
US6373114B1 (en) * 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6450116B1 (en) * 1999-04-22 2002-09-17 Applied Materials, Inc. Apparatus for exposing a substrate to plasma radicals
US6093661A (en) * 1999-08-30 2000-07-25 Micron Technology, Inc. Integrated circuitry and semiconductor processing method of forming field effect transistors
US6242348B1 (en) * 1999-10-04 2001-06-05 National Semiconductor Corp. Method for the formation of a boron-doped silicon gate layer underlying a cobalt silicide layer
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