TWI251082B - Method for testing semiconductor chips - Google Patents
Method for testing semiconductor chips Download PDFInfo
- Publication number
- TWI251082B TWI251082B TW091107302A TW91107302A TWI251082B TW I251082 B TWI251082 B TW I251082B TW 091107302 A TW091107302 A TW 091107302A TW 91107302 A TW91107302 A TW 91107302A TW I251082 B TWI251082 B TW I251082B
- Authority
- TW
- Taiwan
- Prior art keywords
- test
- wafer
- mode
- state
- check mode
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/83—Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
1251082 五、發明説明( 本發明ί系關於一插田^、, 、.. … ;測試半導體晶片的方法,特別是 怜體記憶體晶片’其中,在欲測試之晶片中,會設定至 : 丨錢式,該測試模式係在該晶片中執行並且會將 測a式心不從該晶片輸出。
如果適合的話,合太A 曰 9在進一步生產之前對半導體晶片進行 曰曰Η寺級的測試及修鈾、風& /人 /補過私(除錯)以便決定晶片的品質並且 勿1J除或修補晶片。葬^ s力於詖供載入或設定於欲測試之晶片 數種測試模式,#此可以在該晶片中執行個別的測 賴單元可以同時對大量的晶片進行相關的晶 :在此权序中所取得之測試結果會從該晶片輸出至 〇玄測试早元。贫、、目丨 田 σ 试方法的順序係假設設定於該晶片中及 二°果適當的言舌’相關的暫存器中的測試模式實際上已經 :又:亚且已經初始化所需要的測試順序。換言《,判斷測 試模式f ρ μ θ 、疋否已經成功地初始化之檢查只會根據該晶 勺反應來進仃。該些檢查係手動進行’其係與對 及成本方面的Μ有關,特別是現今的測試模式 女、?侍更加龐大及複雜。丨過’在手動檢查的情形中亦 有問題發峰,君β 4 g 匕^ 卩就疋所衍生的反應並無法輕易地分配到晶 力能區域令。#由實例,如果晶片的内部計數器 :::確地運作的言…瞻只能從一般係藉助於額外的 刀析所讨生的反應中非常困難地進行瞭解。此外,如 2 ^數個測試模式彼此結合成測試程序的話,那麼在此 會發生問題。纟此情形中’即使只遺忘或錯誤傳 达一禮測試模式的話,那麼亦無法直接從晶片對所設定之 -4 - Μ規格(210X297公釐)
本紙張度it t 準(cnH 1251082 A7 B7 五、發明説明(2 測試模式的反應中推斷晶片上的缺陷,反而只能間接地以 及论費非常長的時間來推斷ΰ 因此在序言中所提及之_本道μ a u 捉汉^牛夺日日片的測試方法具有只能 以非$间的費用以及只能在某些例子中才能取得可靠的測 试結果的缺點。 US 4,970,727所提供的係根據申請專利範圍第^項之序言 的方法。此份文件說明一種可以執行複數種經由外部測試 器所選擇之測試模式的積體半導體記憶體。最後,會經由 輸入及輸出緩衝器及連接至暫存器的Μ由該㈣測試器 將施加於該積體半導體記憶體之終端上之信號載人並且儲 存在其中’因此即使該半導體記憶體之終端上的信號改變 ’所選取的測試模式仍然保持已定義狀態。之後,會將儲 存在暫存器中的資料在一輪屮普+ 铷出對應该測試模式的信號給控 制電路的解碼器中進行解碼,該控制電路隨即會初始化該 測試模式。在測試模式執行期間,在半導體記憶體的情形 中,後者可以經由該電路及該輸入及輸出緩衝器及該外部 測m終端’藉由正在讀取之暫存器開始進行。 本發明的目的之一係提供一種用於測試在序言中所提及 之類型的半導體晶片之方 月之方法其通常可以產生可靠的及可 理解的測試結果。 此目的可以藉由申請專利範圍第^之待徵來達成。本發 明之優點會在子申請專利範圍_提出。 取代以前的半導體晶片的測試方法之控 目地執行’如同之前它所進行’因A 、’、 U马忒;則試的品質只能夠 本紙悵尺度適川肀国國家標準(CNS) A4現格(210X 297公釐) 1251082 A7 _______B7 ^、發明説明(3^ ^ 經由衍生的反應推斷’所以本發明在内部執行個別的半導 體晶片的測試之前會監視測試模式的狀態。因此,根據本 發明的方法會提供測試方法的監視,其會顯示該測試模# 貫際上是否已經完全地及正確地載入該晶片中,因此在、、則 試順序執行之前及在取得測試結果之前可以確定該測試的 正確初始狀態。因此,藉助於根據本發明之方法,可以在 早期的階段中將該些未正確設定測試模式之晶片從循環中 取出或進行修補,或是可以在早期階段檢查以及重新定義 用於設定測試模式的條件。 因此根據本發明之方法具有能夠節省時間及增加新的晶 片設計驗證及測試順序開發及除錯的品質之優點。 對於用於測試半導體晶片之方法的情形來說,在該晶片 中亦提供至少一個可以與個別的檢查模式一起設定的暫存 為’較佳的係該設定暫存器的狀態係以根據本發明額外提 供之檢查模式的方式讀取出來的。 對於在該晶片令設定多種欲進行測試之模式以及,如果 適备的活’複數個暫存器的情形來說,為了節省時間會讀 取檢查模式中只有預設測試模式及,如果適當的話,暫存 為的狀恕。假如並非所有的測試資訊都係有關的話。 較佳的係該檢查模式所定義之輸出格式包含規定之起始 簽名(Start Slgnature)以及規定之停止簽名(st〇p signature)。 這係作為移動資料串之簡單識別之用。 原則上,根據本發明之方法亦適用於測試生產參數,舉 例來說’ DRAM之自動更新盪器之頻率。 -6 - 本紙張尺度適用中國國家標準(CNS) Λ‘〖規格(21()X297公資)
Claims (1)
- 々、申請專利範園 1. -種用於測試半導體晶片的方法, 設定至少-種測試模式在一預測試二驟包括: 藉由在-已定義的袼式中讀取:片、中’ 的-狀態以執行一檢查模 =裡的該測試模式 驟之後,在該晶片裡執行該測試^亥執行檢查模式的步 從S亥晶片輪出檢查結果。 '及 2. 如申請專利範圍第丨項之方法,复 起’至少會在該晶片中設定-個暫^ •與檢查模式— 該設定暫存器的狀態亦會在檢查模式中。以及其特徵為 3. 如申請專㈣圍第〗或2項之方法,^出為 數個測試模式及,如 二、$ 4 •在設定複 ,只有所選取之測個暫存器經設定 射…二: 式的狀態以及,如果適當的話, 暫存益的狀態會在檢查模式讀取出。 4. :申料利範圍第_項之方法,其特徵為在檢查模式 所疋義之輪出格式包含一起始簽名及-停止簽名 5· 圍第2項之方法’其特徵為提供該暫存器之 ::?的比較值會輸入至該晶片中’其特徵為該些比 車乂值θ入在該晶片内部的暫存器數值作比較,以及其特 徵為該些比較結果係在檢查模式以PASS/FAIL拓樸讀出 6. 請專利範圍第i,2或5項之方法’其特徵為其包括該 半導體晶片之除錯。 本紙張尺度適用巾g國*標準(CNS) Μ規格挪公楚)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10124735A DE10124735C1 (de) | 2001-05-21 | 2001-05-21 | Verfahren zum Testen von Halbleiter-Chips |
Publications (1)
Publication Number | Publication Date |
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TWI251082B true TWI251082B (en) | 2006-03-11 |
Family
ID=7685594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW091107302A TWI251082B (en) | 2001-05-21 | 2002-04-11 | Method for testing semiconductor chips |
Country Status (6)
Country | Link |
---|---|
US (1) | US6858447B2 (zh) |
JP (1) | JP2003077297A (zh) |
KR (1) | KR100868416B1 (zh) |
DE (1) | DE10124735C1 (zh) |
FR (1) | FR2824916B1 (zh) |
TW (1) | TWI251082B (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6472239B2 (en) * | 2001-04-02 | 2002-10-29 | Micron Technology, Inc. | Method for fabricating semiconductor components |
DE102004053316A1 (de) | 2004-11-04 | 2006-05-18 | Infineon Technologies Ag | Verfahren zur Ein- und Ausgabe von Betriebsparametern eines integrierten Halbleiterspeichers |
DE102004057483B3 (de) * | 2004-11-29 | 2006-08-10 | Infineon Technologies Ag | Verfahren zum Testen von Halbleiter-Chips mittels Bitmasken |
US8499208B2 (en) * | 2006-10-27 | 2013-07-30 | Qualcomm Incorporated | Method and apparatus for scheduling BIST routines |
KR100970895B1 (ko) * | 2009-08-31 | 2010-07-16 | 리노공업주식회사 | 반도체 칩 검사용 소켓 |
CN103890595B (zh) * | 2011-03-01 | 2017-03-22 | 塞勒林特有限责任公司 | 利用多路复用处理机测试单元中的独立控制器进行无索引串行半导体测试的方法和系统 |
CN114328340B (zh) * | 2021-12-30 | 2024-06-07 | 南京英锐创电子科技有限公司 | 芯片检测装置和功能板卡 |
CN115549820B (zh) * | 2022-12-02 | 2023-03-24 | 深圳市锦锐科技股份有限公司 | 收音芯片测试方法及芯片测试系统 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH081760B2 (ja) * | 1987-11-17 | 1996-01-10 | 三菱電機株式会社 | 半導体記憶装置 |
JPH02260200A (ja) * | 1989-03-30 | 1990-10-22 | Sharp Corp | 複数ビット並列テスト機能を有する半導体記憶装置における複数ビット並列機能テスト方法 |
US5299203A (en) * | 1990-08-17 | 1994-03-29 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with a flag for indicating test mode |
JP2796590B2 (ja) * | 1991-08-07 | 1998-09-10 | 三菱電機株式会社 | メモリ装置及びそれを使用したデータ処理装置 |
EP0786675B1 (en) | 1996-01-26 | 2002-11-06 | Teijin Chemicals, Ltd. | Spectacle lens |
JP3867862B2 (ja) * | 1997-04-16 | 2007-01-17 | 株式会社ルネサステクノロジ | 半導体集積回路およびメモリの検査方法 |
US6314011B1 (en) * | 1997-08-22 | 2001-11-06 | Micron Technology Inc | 256 Meg dynamic random access memory |
US6557128B1 (en) * | 1999-11-12 | 2003-04-29 | Advantest Corp. | Semiconductor test system supporting multiple virtual logic testers |
US6259639B1 (en) * | 2000-02-16 | 2001-07-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device capable of repairing defective parts in a large-scale memory |
-
2001
- 2001-05-21 DE DE10124735A patent/DE10124735C1/de not_active Expired - Fee Related
-
2002
- 2002-04-11 TW TW091107302A patent/TWI251082B/zh not_active IP Right Cessation
- 2002-05-14 FR FR0205896A patent/FR2824916B1/fr not_active Expired - Fee Related
- 2002-05-15 JP JP2002140670A patent/JP2003077297A/ja not_active Withdrawn
- 2002-05-17 KR KR1020020027455A patent/KR100868416B1/ko not_active IP Right Cessation
- 2002-05-21 US US10/151,990 patent/US6858447B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2003077297A (ja) | 2003-03-14 |
KR20020088402A (ko) | 2002-11-27 |
US6858447B2 (en) | 2005-02-22 |
KR100868416B1 (ko) | 2008-11-11 |
FR2824916B1 (fr) | 2004-10-08 |
DE10124735C1 (de) | 2002-11-14 |
FR2824916A1 (fr) | 2002-11-22 |
US20030059962A1 (en) | 2003-03-27 |
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