TW477898B - Method and apparatus for verifying the accuracy of built-in self-test - Google Patents

Abstract

In addition to the built-in self-test circuit included in the invented method of verifying the accuracy of built-in self-test, a preset debug pattern database is provided. The preset debug pattern database includes preset debug patterns. The preset debug error detection patterns are implanted into the characteristic model of the memory in advance before the test is conducted. After that, the verification step is performed, and a comparison is made between output signal and debug patterns in the debug error detection database in order to judge the accuracy of self-test. The apparatus of verifying built-in self-test accuracy contains built-in self-test (BIST) unit, which is used as the control unit generated by self-test, and memory characteristic model, which is coupled with data/address scramble. The test signal generated by the BIST control unit will input the memory characteristic model through data/address scramble to perform the test. The preset debug pattern database coupled with memory characteristic model is used to implant or write a preset debug pattern into the memory characteristic model. And an error comparator is coupled with a preset debug pattern database so as to conduct a comparison between the preset detection pattern and output signal.

Description

V. Description of the invention (1) Field of the invention: The present invention relates to a built-in self-test (bui 1 d _ inse 1 f ΐ est; BI ST), especially a method for confirming the quasi-domain nature of the built-in self-test unit test. method. Background of the invention: In the special application of deep sub-micron, the chip usually contains a variety of electronics used to make these memories. The flaws in the chip's memory can be lost or the computer can't describe the state of the memory. Set value comparison. Use integrated circuit (ASIC) or a large amount of memory. Memory products, such as manufacturers of computers and other products, may cause serious effects on memory performance and work properly. Therefore, our system is used to confirm the status of the current part or device, and it is widely used in general integrated circuit (R A M). There are defects in the designer and the system, and the data storage person needs to automatically detect whether the function is normal. Convenient for analysis and prediction. Regarding these defects, many memory chips currently contain RAMB j s sigma ’to detect defects in random access memory. Usually, when ^ r = is turned on, RAM BIST will start to test the random access system. If it finds a defect, it will stop operating the computer's operating system. In addition, at any time, RAM BIST may test the memory. When testing, it usually involves writing specific patterns into the memory and comparing them. If the two cannot be compared normally, it means that there is a defect in the memory. Generally, the algorithm of MARCH is used to test the lack of memory.

_____ ‘One or five, description of the invention (2) ' This type of test involves many components and programs such as processing a sequence of reads / writes to specific locations. & The conventional technique generally belongs to an internal test pattern, and the test pattern is implanted through a tester. The tester looks at the response from the component and compares the signals. In this case, the BIST is implanted into a finite state machlne (FSM) to analyze the above-mentioned response information. In test mode, perform a self-test b. There are many different deductive methods for testing uranium. In addition to the above μ arc η C ’, there are also so-called MARCH C +, Checkerboard, MARCH A, MARCH B and other test methods. When designing a BIST circuit, the most important consideration is to ensure the correctness of the B I ST function. Based on the current test method, the B I S T generates the pattern and compares it by itself, so it is very difficult to verify the accuracy of the current self-test of the BIST circuit. If BIST is lacking, it will be difficult to confirm whether the test results are correct. And this self-debugging method ’B I S T not only plays the dual role of referee but also player. As far as BIS Ding ’s self-debugging patterns are concerned, if the prior art has defects in BiST, it is difficult to determine whether the debugging patterns it produces are correct or not, and it is impossible to determine the self-debugging results. Therefore, a method for confirming the accuracy of the built-in self-test is urgently needed. For the previous case of BIST, please refer to the US patent, USP No. 5, 822228, and the invention name is ‘’ Method for using built in self test to characterize input-to-output delay

Page 6

time of embedded cores and other integrated circuits ". US Patent, USP No. 6, 012, 157, the invention name is" System for verifying effectiveness of a RAM BIST controller's ability to detect faults in a RAM memory using states indicating by fault severity information " Purpose and Summary of the Invention: The purpose of the present invention is a method and device for confirming the accuracy of the built-in self-test (BI ST). The method for confirming the accuracy of the built-in self-test is characterized by the built-in self-test A default debug pattern database is provided outside the unit (BI ST). The above default debug pattern database contains the default debug pattern. The above default debug pattern is implanted into the memory before testing. In the characteristic model, a confirmation step is performed, and the self-test control unit inputs a test signal into the above memory characteristic model to detect the above-mentioned debugging pattern preset therein, and then outputs the output signal and stores it in the preset debugging Compare the debug patterns in the pattern database to determine the accuracy of the self-test The above-mentioned self-test control unit includes a finite state machine (jinUe state machlne; FSM), which is used to generate simulation and sub-test response messages, a “test pattern generator”, which is used to generate a test pattern upon receiving a test finger. Among the above presets Debug pattern database contains

Page 7 V. Description of Invention ⑷

The FSM compiles the corresponding addresses and data, and the above-mentioned FSMs in different states have different codes. Conducive to FSM algorithms include

MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH A device to confirm the accuracy of the built-in self-test, including a self-test (BIST) control unit, which is used as a control unit generated by the self-test. It is used after receiving the test command To generate a test pattern. The data / address scrambl e is coupled to the self-test control unit to scramble the position of the transmitted information. A memory characteristic model, which is light on the data / address scrambling unit, and the test signal generated by the self-test (BIST) control unit will be entered into the memory characteristic model for testing by the data / address scrambling unit. . The preset debug pattern database is combined with the memory characteristic model, and is used to implant or write a preset debug pattern into the memory characteristic model, so as to facilitate subsequent tests generated by the self-test control unit. Signal detection. The data / address scrambling unit is coupled to the above-mentioned memory characteristic model, and the information read out from the memory characteristic model passes through the data / address scrambling unit to return the data address sequence. The error comparator compares the preset detection pattern with the output signal. Detailed description of the invention: What is disclosed in the present invention is a method and a device for self-test. The method and device can confirm the accuracy of the built-in self-test. And the special model ca n’t be as erroneous as the transcontinental chip.

Page 8 4 ^ 98 and so on Λ 鹞 V. Cai Liang's explanation (5) The change of level (REGISTER TRANSFER LEVEL, RTL) and the error of the interpolar state are very important issues. Referring to FIG. 1, the self-test apparatus of the present invention includes a self-test (BIST) control unit 100, which is used as a control unit generated by the self-test, and includes a finite state machine (FSM) to analyze a test response. message. And includes a test pattern generator, which is used to generate a test pattern after receiving a test instruction to facilitate testing the state of the memory. A data / address scrambling unit (data / add I * ess scramb 1 e) 11 0, which is coupled to the above-mentioned self-test control unit i 〇〇 is used to scramble the position of the information to be transmitted, and then transmit it. The receiver must have the same solution data / address scrambling algorithm to recover and decode the original transmission information. The memory to be tested or the memory characteristic model 丨 2 〇 Lightly fit the data / address scramble unit 110 described above. The above test signal generated by the self-test (BIST) control unit 100 will be input into the memory characteristic model 120 through the data / address scrambling unit 1 10. One of the features of the present invention includes a preset error detection pattern database 50, which is adapted to the memory to be tested 120 and is implanted outside the self-test circuit. The preset horizontal error pattern database 150 includes a FSM and a preset debugging pattern. Generally, before the self-test is performed, the preset debug pattern database 15 will embed or write a preset debug pattern in the memory characteristic model 12 to facilitate subsequent self-tests ( BI ST) The test signal generated by the control unit 1000 is measured. Since the test pattern is generated independently of the self-test circuit, when the self-test (BIST) control unit 100 has an error, it can be compared by

4BS & 8 90.12.31 Tong Dangshu etc. Λ _ 7% ^ Five, the date of delivery ^ Erming (J) '" * --- To determine whether the error detection pattern matches the preset detection pattern or not Self-testing correctness. Decomposition material / address scrambling unit 1 3 0, coupled to the above-mentioned memory characteristic model 120 to be tested, passes the information read out from the memory characteristic model 丨 20 to the de-data / address scrambling unit 1 The sequence of the 30 data addresses is fed back to the B I ST comparator 1 4 0. After that, the signal is passed to the error comparator 170. Generally, the memory characteristic model 120 is described using VerUog or VHDL language to facilitate the simulation of register TRANSFER LEVEL (RTL) and gate states. A solution characteristic data scramble unit (behavior data descramble) 160 is coupled to the above-mentioned default debug pattern database 15 and is used to scramble the preset detection pattern data address and transmit it to the error comparator In (faults comparator) 170, the preset detection pattern is compared with the output number. If the comparison result ’matches the preset pattern, it means that the self-test is accurate. Conversely, if it cannot match the preset pattern, it means that the self-test is incorrect. Therefore, based on the above comparison results, it can be judged whether the above self-test is accurate. Figure 2 shows the composition of the preset error pattern database, which includes the F S M code, the corresponding address (a d d r e s s), and the data (d a t a). F S M in different states has different codes. Please refer to Figure 3. For example, use algorithm encoding to separate different states; PSM encoding. For example, the state of the MARCH C + algorithm state 2 is read 0 / write 1 / read 1 (R0W1R1), and the FIST code of the BIST circuit is 0.0001. Profit

Page 10

Use the state 3 of the MARCH C + algorithm to read 1 / write 0 / read 0 (R1W0R0), and the FSM code in the BIST circuit is 0010. Another example is to use the Step 1 state of the CheckBoard algorithm, which is 0101 in the BIST circuit. The algorithm or coding form described above is only used for illustration, and is not intended to limit the present invention. For example, the algorithm is not limited to the method described above. Therefore, different algorithms can be applied to the present invention, including methods such as MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH B, and so on. According to different F S M codes, the preset debug pattern database 150 inserts or writes a preset debug pattern into a predetermined address before performing a self-test. As shown in Fig. 2, the FSM code 00001 means that the debug pattern 0 0 is implanted at the address of 1111, and the FS M code 00001 means that the debug pattern 10 is implanted at the address 010. . The rest and so on. Therefore, when the self-test is performed by the B I S T subsequently, the B I S T circuit will simulate the gate and pass the output of the BIST comparator. In the error comparator, compare the output signal with the pre-implanted pattern stored in the preset debug pattern database 150 to confirm whether the preset pattern is in the preset memory address. , So confirm the accuracy of the self-test. What has been described above is used for illustration only, and is not intended to limit the present invention. Therefore, those skilled in the art can use different algorithms and encoding methods to generate different codes. Figure 4 shows the method for confirming the accuracy of the built-in self-test according to the present invention. The method includes providing a database of preset debugging patterns, including FS Μ and preset debugging patterns, and then in step 4 〇〇, implant the preset

Take ... 1 ____ ____ __ 5. Description of the invention (8) The error detection pattern information is in the memory characteristic model 丨 2 〇, in order to facilitate subsequent steps to confirm whether the BIST is accurate. After the preset debug pattern is implanted, the BI ST control unit performs a confirmation step 4 and performs a test to output a test signal. The test signal is processed by scrambling the data position (step 4 2 0), and then input into the above memory characteristic model 2 0 2. In step 43, a test is performed on the memory characteristic model to detect a debugging pattern preset therein. The read signal signal is descrambled by the data position and will be read out from the memory characteristic model 120. The information passes through the data / address scrambling unit 丨 3 0 and returns the order of the material address, and then feeds it into the BI ST comparator 1 40. After that, the signal is output outside the BIS circuit. In the final step 44, a comparison is made between the output signal and the previously implanted debug pattern stored in the default debug pattern database to determine whether the signal output by the BIST self-test can capture the implanted signal. pattern. The above results are used to determine self-accuracy. Based on the debugging method of the present invention and the preset debugging pattern is set outside the nature τ $ road, the role of player and referee will be avoided to improve accurate RTh and help to judge the results of the B1ST test. Compared with the prior art by β i 〇 T white, reading

As far as the method of generating debug patterns is concerned, there is no state where a fixed error occurs when the prior art generates a condition. If the B 1 ST itself is wrong, it is difficult to determine the correctness of the debug pattern, and it is impossible to determine the result after the debug. Second, the method of the present invention will help confirm the correctness of the self-test.

Page 12 V. Description of the invention (9) The present invention has been described above with reference to the preferred embodiments. Those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention, and the scope of patent protection is more appropriate. Depending on the scope of the attached patent application and its equivalent fields.

W19% 12.3t]

S-free image etc. H •-丨 丨 _ 丨…, 』---- The diagram is briefly explained and illustrated: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures : Figure 1 shows the functional block diagram of the present invention. FIG. 2 is a schematic diagram showing the composition of a preset error detection pattern according to the present invention. Figure 3 shows a schematic diagram of the FSM encoding of the present invention. Figure 4 shows a flowchart of the method of the present invention. Symbol comparison table BIST control unit 100 Data / address scrambling unit 1 1 0 Memory characteristic model 1 2 0 Decryption data / location scrambling unit 130 BIST comparator 140 Default debug pattern database 1 5 0 Decryption characteristic data Random unit 1 6 0 Error comparator 1 7 0

Claims (1)

477898 6. Scope of patent application Patent scope: 1. A device for confirming the accuracy of the built-in self-test, including: a self-test (BIST) control unit, which is used to generate a test pattern after receiving a test instruction; data / address settings The data / address scramble is used to scramble the position of the transmitted information; ^ The memory characteristic model is coupled to the data / address scramble unit and is tested by the self-test (BIST ) The test pattern generated by the control unit is input to the memory characteristic model for testing through the data / address scrambling unit; a preset debug pattern database is coupled to the memory characteristic model for planting or writing Enter a preset error detection pattern into the memory characteristic model, to facilitate subsequent detection of the test pattern generated by the self-test control unit; a data / address scrambling unit, coupled to the above-mentioned memory Characteristic model, the information read out from the memory characteristic model is passed through the data / address scrambling unit to return the data address order; BI ST ratio And a decompression unit coupled to the BI ST comparator; and a decompression feature data scrambling unit coupled to the above-mentioned default debug pattern database φ and the The error comparator is used to scramble the preset detection pattern data address, and then transmit to the error comparator to compare the preset detection pattern with the output signal. 2. If the built-in self-test accuracy is confirmed in item 1 of the scope of patent application Page 15 477S98 90.12.31: --------- 3 .-. '… .., g _______ 6. The scope of patent application, where the above self-test control unit includes: finite state machine (finite state machine) machine (FSM), which is used to generate simulation and analyze test response information, and a test pattern generator is used to generate the test pattern after receiving the test instruction. 3. As for the device for confirming the accuracy of the built-in self-test in item 2 of the scope of patent application, the algorithms that facilitate the above FSM are included in MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH B 0 4. 1 device for confirming the accuracy of the built-in self-test, in which the above-mentioned default debug pattern database includes FSM codes, corresponding addresses, and data, and the above-mentioned FSMs in different states have different codes . 5 · If the built-in self-test accuracy device is confirmed in item 4 of the scope of patent application, the algorithms that are beneficial to the above FSM are included in MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH B ° ❿ A method for establishing the accuracy of self-testing includes: providing a database of preset debugging patterns, which includes preset debugging patterns; and embedding the above-mentioned default debugging patterns in a memory characteristic model to facilitate the recognition of the self-test Whether the accuracy is accurate; perform the confirmation steps to perform the test, and the self-test control unit will test the signal Then enter the above-mentioned memory characteristics. The sixth part of the patent application is in the process of scrambling the data position. Perform the above-mentioned memory special pattern and the order of the data address in the detected memory characteristics model is output. The signal uses the embedded debugging pattern to make a seat model test. The information that is detected by the data through the data bit is de-funded, and then it is fed into the BIST ratio and stored in the default debug-comparison, which is used to determine the test preset in Among them, the misplacement and scrambling will be returned to the comparator by the data / address scrambling unit; and / or the first seven self-test accuracy in the pattern database. Λ If the method of confirming the accuracy of the built-in self-test is stated in item β of the patent scope, wherein the above-mentioned self-test control unit includes: a finite state machine (FSM), which is used to generate simulation and analyze test response information; test The pattern generator is used to generate the test pattern after receiving the test instruction. 8 · Method for confirming the accuracy of the built-in self-test, as described in item 7 of the scope of patent application, in which the algorithms that facilitate the above FSM are included in MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH B 〇9. 6 methods for confirming the accuracy of the built-in self-test, wherein the above-mentioned default debug pattern database includes FSM codes and corresponding addresses and data, and the above-mentioned FSMs in different states have different codes. 6. Scope of patent application 10. If the method of confirming the accuracy of the built-in self-test is specified in item 9 of the scope of patent application, the algorithms that are beneficial to the above FSM include MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH B ° 11. A method for confirming the accuracy of a built-in self-test, which includes providing a preset debug pattern database in addition to the built-in self-test unit (BIST), wherein the above-mentioned default debug pattern database includes preset debug patterns The wrong pattern is implanted into the memory characteristic model before the test is performed, and then the confirmation step is performed. The self-test control unit inputs a test signal into the memory characteristic model to detect The above-mentioned debug patterns are preset therein, and then the output signal and the debug patterns stored in the preset debug pattern database are compared to determine the accuracy of the self-test. 1 2. The method for confirming the accuracy of the built-in self-test as described in item 11 of the scope of patent application, wherein the above-mentioned self-test control unit includes: a finite state machine (FSM) for generating simulation and analyzing the test response message; The test pattern generator is used to generate the test pattern after receiving the test instruction. 1 3. As for the method of confirming the accuracy of the built-in self-test, as described in item 12 of the scope of patent application, the algorithms that are conducive to the above FSM are included in MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH B ° Page 18: Γ Adjustment 6. Application scope 1 4. If the method for confirming the accuracy of the built-in self-test is specified in item 11 of the application scope, the above-mentioned default debug pattern database includes FSM code and corresponding address (Address), data (data), and the above-mentioned FS M in different states have different codes. 1 5. If the method of confirming the accuracy of the built-in self-test is as described in item 14 of the scope of patent application, the algorithms that are beneficial to the above FSM include MARCH C, MARCH C +, Checkerboard, MARCH A, MARCH B o Page 19