TWI236112B - Chip package structure - Google Patents

Chip package structure Download PDF

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Publication number
TWI236112B
TWI236112B TW092122339A TW92122339A TWI236112B TW I236112 B TWI236112 B TW I236112B TW 092122339 A TW092122339 A TW 092122339A TW 92122339 A TW92122339 A TW 92122339A TW I236112 B TWI236112 B TW I236112B
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TW
Taiwan
Prior art keywords
chip
wire
contact
carrier
bonding
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Application number
TW092122339A
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English (en)
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TW200507207A (en
Inventor
Chi-Hsing Hsu
Kenny Chang
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Via Tech Inc
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Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW092122339A priority Critical patent/TWI236112B/zh
Priority to US10/695,018 priority patent/US20050035448A1/en
Publication of TW200507207A publication Critical patent/TW200507207A/zh
Application granted granted Critical
Publication of TWI236112B publication Critical patent/TWI236112B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

1236112
1236112
134、136、138以及一封膠（未繪示）所構成。承載器11(}之 表面具有-晶片接合區112，而晶片12〇之背面122係貼附 在晶片接合區112上，且晶片12〇之主動表面124具有多個 接合墊1 2 6，其分別對應於承載器丨丨〇之表面上的接點，其 中接點由内而外之順序例如為接地接點丨丨4、電源接點1工6 以及訊號接點1 18等。此外，每一導線134、136、138之兩 端分別連接至晶片12〇之接合墊126之一及其所對應之接地 接點114、電源接點116以及訊號接點118上。 产值付注意的是，為了·有效提昇晶片封裝結構1 〇 〇的電 氣特性’通常是利用表面黏著技術（Sur f aCe Mount Technology, SMT )將小型被動元件丨3〇貼附在承載器i 1() 之表面，用以減少訊號在切換時所產生之雜訊串音干擾 (c r 〇 s s t a 1 k )，並維持訊號傳輸品質。其中，被動元件 1 30例如為電感元件（induct〇r )或電容元件（capaci ）， 而被動元件1 30跨置於承載器丨丨〇之電源接點丨丨6以及接地 接點1 14之間，且被動元件13〇之二接腳132&、13礼分別連 接至電源接點1 1 6以及接地接點丨丨4。 然而，當晶片1 2 0與承載器11 〇之間進行打線接合製程 日寸’對應連接晶片1 2 0之接合墊1 2 6以及承載器11 〇之電源 接點1 1 6的導線1 3 6，必須先跨過被動元件1 3 0之上方，之 後再銲接至電源接點1 1 6之表面上。由於導線1 3 6必須先拉 長弧線，才能跨過被動元件丨3 〇之上方，所以相對導致導 線136本身之長度增長，而訊號行經導線丨36之傳輸路徑增 長’將使晶片1 2 0的電氣性能降低，且影響鄰近導線之佈
1236112 五、發明說明（3) 設空間。 發明内容 因此，本發明 用以縮短導線之長 為達本發明之 構，至少包括一承 點以及一接 點以及接地 係位於晶片 器之表面， 晶片係以背 墊，其配置 承載器之電 二接腳，其 地接點 接點均 接合區 而晶片 面貝占附 於主動 源接點 分別電 的目的 度，並 上述目 載器， ，且表 配置於 之外的 具有一 至晶片 表面。 以及接 性連接 者，至少一第一導線之兩 墊之一以及這些接腳之一 元件以及第 上述本 連接至被動 短，而訊號 能提高，且 為讓本 顯易懂，下 細說明如下 導線 加以包 晶片封 接腳上 線之傳 近導線 發明之 元件之 行經導 增加鄰 發明之上述和 文特舉一較佳 就是在 增加導 的，本 此承載 面具有 表面， 區域。 主動表 接合區 另夕卜， 地接點 至電源 端係分 。再者 覆。 裝結構 ，因此 輸路徑 之佈線 其他目 實施例 提供一種晶片封裝 線之佈線空間。 •種晶片 發明提出一 器具有一表 一晶片接合 且電源接點 此外’晶片 面以及對應 面 、一 區 ^而 以及接 係配置 之 背 ’且晶片更具有多 至少一被動元件係 元件具 地接點 片之這 一封膠係將晶片 之間，被動 接點以及接 別連接至晶 ，其中導線之一端 導線的長度將可有 縮短’將使晶片的 空間。 的、特徵、和優點 ，並配合所附圖式 結構’ 封裝結 電源接 電源接 地接點 於承載 面，且 個接合 跨置於 有至少 〇再 些接合 、被動 可直接 效的縮 電氣性 能更明 ，作詳
11476twf.ptd 第8頁 1236112
實施方式 請參考第2A及2B圖，其中第2A圖繪示本發明一較佳實 施例之一種打線接合型態之晶片封裝結構的局部剖面圖，、 而第2B圖繪示本發明一較佳實施例之一種打線接合型態之 晶片封裝結構的俯視示意圖。晶片封裝結構2〇〇主要係u由 一承載器210、一晶片22〇、一被動元件“Ο、多個第三導 線234、236、至少一第二導線238以及一封膠（未繪示） 所構成，其中承載器210例如為一基板，其表面呈^ 晶 片接合區212 ’·而晶片220之背面22 2係貼附在晶片'接合= 212上，且晶片220之主動表面224具有多個接合墊22β，其 分別對應於承載器210上之接點，這些接點例如為接地接' 點2 1 4、電源接點2 1 6以及訊號接點2 1 8等。在本實施例 中，如第2B圖所示，其中電源接點216以及接地二:214例 如位在晶片接合區2 1 2之外的同一側，且兩者例如分別由 環繞於晶片接合區2 1 2之外圍的一電源環（未緣示）以及 一接地環（未繪示）的局部線段所形成，而電源環的部分 表面以及接地環的部分表面暴露於圖案化之一鮮罩層24〇 之開口中，以做為連接第一導線234、2 3 6或被動元;23〇 之用的電源接點2 1 6或接地接點2 1 4。 請參考第2A及2B圖，訊號接點218位於電源、接點216以 及接地接點2 1 4之同一側，而訊號接點2 1 8相對遠離晶片接 合區2 1 2且位於電源接點2 1 6以及接地接點2 1 4之外側。此 外，訊號接點2 1 8以及晶片接合區2 1 2同樣可暴露於圖案化 之銲罩層2 4 0的開口中。 ° '
11476twf.ptd 第9頁 1236112 五、發明說明（5) ---- 另外，請參考第2A圖，被動元件23 0跨置於雷％上 兒你接里上 216以及接地接點214之間，且被動元件23 0具有至少— 腳23 2a、23 2b，其利用表面黏著技術（SMT )而分別^接 在電源接點2 1 6以及接地接點2 1 4之表面，用以有吟4 接 w义文抑制楚 一導線2 34、2 3 6以及第二導線238之間所產生之交互/ 性耦合。其中，被動元件2 3 〇例如為小型電感元件或電f 元件，且被動元件230之接腳232a、232b表面還具有二= 屬層2 4 2 ’此金屬層2 4 2例如以電鍍的方式所形成，且公1 層242之材質可為鎳、金或其他合金，用以增加後續打孟線 製程時第一導線2 34、2 3 6與接腳2 3 2a、232b之間的接丁人 性。 σ 值得注意的是，為了縮短導線234、236之長度，本實 施例直接將至少一第一導線236之一端銲接在被動&元件2/〇 之接腳2 3 2a上，其中第一導線236之兩端可對應連接至晶 片220之一接合墊226a以及被動元件22 0之遠離晶片22()= 接腳2 3 2a，而另一第一導線234之兩端可對應連接至晶片 22 0之另一接合墊22 6b以及被動元件23〇之鄰近晶片的 ，腳2 3 2b上或接地接點2丨4上（圖未示）。由於外層之第一 導線2 3 6不須拉長弧線以跨過被動元件23〇之上方，而是直 接銲接在被動元件23 0之接腳232a±，因此外層之第一導 ^2 3 6的長度將可有效的縮短，而訊號行經第一導線23 6之 :j路徑縮短，將使晶片220的電氣性能提高，且增加鄰 接=H佈設空間°此外’第二導線238之兩端可對應連 曰曰 之又一接合墊226c以及承載器21〇最外圍之訊號 (6) 1236112 五 接點218，且第二導線238還可橫跨於被動元件23〇之上 方，而不會接觸到被動元件23 0之任一接腳232a、232b。 由上述之說明可知，本發明之晶片封裝結構係先跨 一被動兀件於承載器之電源接點以及接地接點之間， 且被動元件之二接腳分別電性連接電源接點以及接地接， 發明說明 至少 ^ α疋设电妳按點以及接地接 11 "、、亡？ 接著對應連接—第—導線至晶片之一接合墊以及被 元件之^接腳上，接著再對應連接一第二導線至晶片之 一接合蛰以^訊號接點’之後可再形成一封膠將晶片 動元件以及第一、第二導線包覆，用以保護晶片以及第 —、第二導線，如此即可完成—晶片封裝結構。 综上所述，本發明之晶片封裝結構具有下列優點. 因此匕導線之：端可直接連接至被動元件之-接腳上， c長^將可有效的縮短，而訊號行 w k、％紐，將使晶片的雷氧w、1寻氣 佈線空間。 5的⑽生牝“ ’並增加鄰近導線之 栽哭(最2)/線之一端可橫跨於被動元件之上方而鲜接在承 腳。圍之接點上’且不會接觸到被動元件之任一接 以限：：本發明已以-較佳實施例揭露如±，然其並非用 K發明丄任何熟習此技藝者，“ = 二圍”，當可：些許之更動與潤飾，因此本發0 = 乾圍*視後附之中請專利範圍所界定者為準。g之保 11476twf.ptd 第11頁 1236112 圖式簡單說明 第1 A圖繪示習知一種打線接合型態之晶片封裝結構的 局部剖面圖。 第1 B圖繪示習知一種打線接合型態之晶片封裝結構的 俯視示意圖。 第2A圖繪示本發明一較佳實施例之一種打線接合型態 之晶片封裝結構的局部剖面圖。 第2 B圖繪示本發明一較佳實施例之一種打線接合型態 之晶片封裝結構的俯視示意圖。 【圖式標示說明】 I 0 0 :晶片封裝結構 II 0 :承載器 I 1 2 :晶片接合區 II 4 :接地接點 11 6 :電源接點 11 8 :訊號接點 1 2 0 :晶片 1 2 2 :背面 124 :主動表面 1 2 6 :接合墊 1 3 0 :被動元件 1 3 2 a、1 3 2 b :接腳 134、136、138 :導線 2 0 0 :晶片封裝結構
11476twf.ptd 第12頁 1236112 圖式簡單說明 210 承 載 器 212 晶 片 接 合 214 接 地 接 點 216 電 源 接 點 218 訊 號 接 點 220 晶 片 222 背 面 224 主 動 表 面 226a、2 2 6b、2 2 6c :接合墊 2 3 Ο :被動元件 232a、232b :接腳
234 、236 :第一導線 238 第二 導線 240 銲罩 層 242 金屬 層 11476twf.ptd 第13頁

Claims (1)

1236112 六、申請專利範圍 1. 一種晶片封裝結構，至少包括： Λ 一承載器，具有一表面、一電源接點以及一接地接 點，且該表面具有一晶片接合區，而該電源接點以及該接 地接點均配置於該表面，且該電源接點以及該接地接點係 位於該晶片接合區之外的同一側； 一晶片，配置於該承載器之該表面，而該晶片具有一 主動表面以及對應之一背面，且該晶片係以該背面貼附至 該晶片接合區，且該晶片更具有複數個接合墊，其配置於 該主動表面； . 至少一被動元件，跨置於該承載器之該電源接點以及 該接地接點之間，該被動元件具有至少二接腳，其分別電 性連接至該電源接點以及該接地接點； 至少一第一導線，電性連接該晶片之該些接合墊之一 以及該些接腳之一；以及 一封膠，包覆該晶片、該被動元件以及該第一導線。 2. 如申請專利範圍第1項所述之晶片封裝結構，其中 該承載器還具有一訊號接點，而該訊號接點係位於該電源 接點以及該接地接點之較遠離該晶片接合區的外侧。 3. 如申請專利範圍第2項所述之晶片封裝結構，更包 括至少一第二導線，其兩端分別連接至該晶片之該些接合4 墊之另一以及該訊號接點，且該第二導線係橫跨於該被動 元件之上方。 4. 如申請專利範圍第3項所述之晶片封裝結構，其中 該封膠還覆蓋於該第二導線。
11476twf.ptd 第14頁 1236112 六、申請專利範圍 5. 如申請專利範圍第1項所述之晶片封裝結構，其中 該些接腳之表面具有一金屬層，而該金屬層之材質係選自 於由錄、金及該等合金所組成群組之一種材質。 6. 如申請專利範圍第1項所述之晶片封裝結構，其中 該被動元件係為電感元件以及電容元件其中之一。 7. —種打線接合封裝結構，適於將一晶片電性連接至 一承載器，其中該承載器之表面具有一晶片接合區，而該 晶片具有一主動表面以及對應之一背面，且該晶片係以該 背面而貼附至該晶片接合區上，該打線接合封裝結構至少 包括： 一電源接點’，配置在該承載器之表面； 一接地接點，配置在該承載器之表面； 一訊號接點，配置在該承載器之表面，其中該電源接 點以及該接地接點係位於該晶片接合區之外的同一側，且 該訊號接點係位於該電源接點以及該接地接點之較遠離該 晶片接合區的外側； 一被動元件，跨置於該承載器之該電源接點以及該接 地接點之間，且該被動元件具有至少二接腳，其分別電性 連接至該電源接點以及該接地接點； 複數個接合墊，配置於該晶片之該主動表面； 一第一導線，電性連接該些接合墊之一以及該些接腳 之一；以及 一第二導線，電性連接該些接合墊之另一以及該訊號 接點，且該第二導線係橫跨於該被動元件之上方。
11476twf.ptd 第15頁 1236112 六、申請專利範圍 8. 如申請專利範圍第7項所述之打線接合封裝結構， 其中該些接腳之表面具有一金屬層，而該金屬層之材質係 選自於由鎳、金及該等合金所組成群組之一種材質。 9. 如申請專利範圍第7項所述之打線接合封裝結構， 其中該被動元件係為電感元件以及電容元件其中之一。 1 0. —種打線接合製程，適於將一晶片電性連接至一 承載器，其中該承載器之表面具有一晶片接合區，且該承 載器之表面更配置至少一電源接點以及至少一接地接點， 而該晶片具有一主動表面以及一背面，且該晶片係以該背 面貼附至該晶片接合區，且該晶片具有複數個接合墊，其 配置於該主動表面，該打線接合製程至少包括： 跨接一被動元件於該承載器之該電源接點以及該接地 接點之間，其中該被動元件具有至少二接腳，其分別電性 連接該電源接點以及該接地接點；以及 連接一導線之兩端分別至該晶片之該些接合墊之一以 及該些接腳之一。 1 1 .如申請專利範圍第1 0項所述之打線接合製程，其 中該被動元件係為電感元件以及電容元件其中之一。
11476twf.ptd 第16頁
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