TWI227556B - Chip structure - Google Patents

Chip structure Download PDF

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Publication number
TWI227556B
TWI227556B TW092119227A TW92119227A TWI227556B TW I227556 B TWI227556 B TW I227556B TW 092119227 A TW092119227 A TW 092119227A TW 92119227 A TW92119227 A TW 92119227A TW I227556 B TWI227556 B TW I227556B
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wafer
arc
line
protective layer
pad
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TW092119227A
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TW200503220A (en
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Min-Lung Huang
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Advanced Semiconductor Eng
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Priority to TW092119227A priority Critical patent/TWI227556B/zh
Priority to US10/710,401 priority patent/US7049705B2/en
Publication of TW200503220A publication Critical patent/TW200503220A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1227556 五、發明說明（1) m所屬之枯術頷城 本發明是有關於一種晶片結構，且特別是有關於一種 保護層開口之改良結構。 先前技術 在半V體產業中’積體電路（integrated Circuits， ic)的生產，主要分為三個階段··晶圓（Wafer)的製造、積 體電路（1C)的製作以及積體電路的封裝（Package)等。其 中’裸晶片（d i e )係經由晶圓（W a f e r)製作、電路設計、電 路製作以及切割晶圓等步驟而完成，而每一顆由晶圓切割 所形成的裸晶片，經由裸晶片上之銲墊（B〇nding pad)與 外部訊號電性連接後，再將裸晶片加以封裝，其封裝之目 的在於防止裸晶片受到濕氣、熱量、雜訊的影響，並提供 裸晶片與外部電路，比如與印刷電路板（Printed circuit Board，PCB)或其他封裝用基板之間電性連接的媒介，如 此即完成積體電路的封裝製程。 、請參考第1圖，其繪示習知一種保護層之開口結構的 俯視示意圖。每一顆由晶圓切割所形成之晶片丨〇〇，且有 多個銲墊110，而銲墊110排列於晶片1〇〇之主動表面f〇2 上’以作為晶片1 〇 〇連接外部訊號之接點。此外，為了避 免晶片100最外層之圖案化線路層116遭受外來雜質及機械 f生的，在阳片1〇〇之主動表面102上可形成一保護層 L〇4(Passivation Layer)，此保護層1〇4例如為一有機保 濩材料或一無機保護材料所沉積而成，其覆蓋於晶片丨〇 〇 之主動表面102上，且保護層104覆蓋於銲墊11〇之局部表 1227556 五、發明說明（2) 面以及傳輸線1 1 4之表面上，而未被保護層丨〇 4覆蓋之銲墊 11 0的上表面11 2則形成一開口 1 〇 β，以作為後續凸塊製程 或打線製程所需之接點窗口。 、 值得注意的是，習知保護層1 〇 4所形成之開口丨〇6，一 般為圓形開口。然而，當晶片丨〇 〇之運作速度加快時，常 會形成大量的電流由傳輸線丨14流向銲墊11()上方之開口 106，並集中在圓形開口1〇6靠近於傳輸線114之輪廓表面 1 0 8J使得此輪廓表面丨08的電流密度大於其周圍表面之電 流密度，進而導致電流擁擠的現象。更嚴重者，位於銲墊 110 上方之一球底金屬層（Under Bump Metaiiurgic’ |JBM)，其金屬原子在長時間的電流作用下因電致遷移 屬E1:3〇:lg;ati〇n)而流失，以至於在銲墊110與球底金 J層（未繪不）之間造成開路，而影響晶片1〇〇之使用壽 發明内！ 因此，本發明的目的就是在提 電流通過保護層開口之密度能夠八：3曰^卞 擠的現象。 J。勺刀佈，並改善電流擁 =本發明之上述目的’本發明提出 日日片具有至少一銲墊以及連接該銲日日片、、、口構。 與傳輸線係位於晶片之表面。此外墊：線，而銲塾 表面上，且保護層具有一開口， 山、^ 9覆盍於晶片之 輪廓#由 ^ ith 々路出銲墊，里中開σ之 铷郇係由一直線以及連接直線之 、中開口之 直線靠近於傳輸線連接至銲墊之一端。、囫弧所構成，且 11571twf.ptd 第6頁
1227556
晶片=發明之上述目的’本發明提出-種晶片結構， 曰片具有至少一銲墊以及連接該銲墊之一 線係:立：晶片之表面。此外，㈣覆蓋於晶：之 且保護層具有一開口，暴露出銲墊，其中開口之 兩邪係由一弧線以及連接弧線之兩端的一圓弧2 2凹陷於圓弧之中，1弧線靠近於傳輸線連接至鮮塾之 依知本發明的較佳實施例 近於傳輸線連接至銲墊之一端 墊上方之開口時，由於開口的 之圓形，因此電流密度可避免 表面上，而是均勻分佈在直線 擁擠的現象。 為讓本發明之上述和其他 顯易懂，下文特舉一較佳實施 細說明如下： 所述，上述之直線或弧線靠 ，而電流經由傳輸線流向銲 輪廓為直線或弧線而非習知 集中在習知圓形開口之輪廓 或孤線上，因此可改善電流 目的、特徵、和優點能更明 例，並配合所附圖式，作詳
^ 請參考第2圖，其繪示本發明一較佳實施例之一種保 羞層之開口結構的俯視示意圖。晶片2 〇 〇具有多個銲墊 2 1 〇 ’而銲墊2 1 0例如以面陣列型態排列於晶片2 〇 〇之主動 表面202上，以作為晶片200連接外部訊號之接點。此外， 為了避免晶片200最外層之圖案化線路層216遭受外來雜質 ，機械性的傷害，在晶片2 0 0之主動表面202上可形成一保 瘦層204 (Passivati〇n Layer)，此保護層204例如為一有
1227556 五、發明說明（4) 機保護材料或一無機保護材料所沉積而成，其覆蓋於曰 2〇〇之主動表面20 2上，且保護層2〇4覆蓋於銲墊21〇 =片
表面以及傳輸線214之表面上，而未被保護層2〇4覆:部 墊2 1 〇的上表面2 1 2則形成一開口 2 〇 6，以作為後續凸杯 程或打線製程所需之接點窗口。 、 鬼I 、在本實施例中，保護層之開口 206輪廓係由一直錄 以及連接直線2 08之兩端的一圓弧2 〇8a所構成。如此》〇8 知圓形開口 106之部分輪廓經過適當的處理而改變其疋習 狀。請參考第2圖，在開口 20 6之處理上，例如利用、; 方式，使其開口 2 0 6靠近於傳輸線2 1 4之輪廓係為一 1的 2 〇 8 ,此直線2 〇 8比如是習知圓形開口丨〇 6之一弦，其、、、 延伸於傳輸線214連接至銲墊210之一端。因此，者 傳輸線214流向銲墊210上方之開口2〇6時，由於開田流由 近於傳輸線214的輪廓為直線而非習知之圓形，因靠 密度可避免集中在習知圓形開口之輪廓表面1〇8上，=流 均句分佈在開口 206之直線2〇8上，故可改善電流擁而是 象。當然，在本實施例中，為了不影響習知圓形開口 、現 的面積，直線2 0 8的長度可小於等於習知圓形開口丨〇 〇 6 徑R ,最為適當。然而，在不考慮開口面積之情況下，的半 線2 08的長度亦可介於圓弧2〇8a之半徑與直徑之間，直 口之形狀將趨近於半圓形。 3 而開 另外’除了利用直線形開口 2 0 6之外，本發明提 一種保護層之開口結構的俯視示意圖。請參考第3圖，， 片2 0 0具有多個銲墊21〇，而未被保護層2〇4覆蓋之銲墊^曰
1227556
的上表面2 1 2則形成一開口 2 〇 7。在本實施例中，保護層 204之開口 20 7係由一弧線209以及連接弧線20 9之兩端的一 圓弧2 0 9a^所構成，其中弧線2〇9凹陷於圓弧2〇ga之中，且 孤線2 0 9靠近於傳輸線214連接至銲墊210之一端。因此， 當電流由傳輸線214流向銲墊21〇上方之開口 20 7時，由於 開口 2 0 7罪近於傳輸線2 1 4的輪廓為弧線2 〇 9而非習知之圓 形，因此電流密度可避免集中在習知圓形開口丨〇6之表面 上’而是均勻分佈在開口 2 〇 7之弧線2 〇 9上，故可改善電流 擁擠的現象。 當然’在最佳情況下，弧線2 〇 9上任一點與傳輸線2 1 4 連接至銲墊21 0之一端的距離D係可等距分佈，如此弧線 20 9上任一點的電流密度亦將達到均勻分佈的效果。此 外，為了不影響開口 2 0 7的面積，此弧線2 〇 9的長度可小於 等於圓弧20 9a的半徑R為宜，且此弧線2〇9的曲率可小於等 於圓弧2 0 9a的曲率。當然，在不考量開口面積之情況下， 此狐線2 0 9的長度可加長，且其曲率可大於等於圓狐2 〇 9 a 的曲率。如此，開口 2 0 7之形狀將趨近於彎月形。 綜上所述’本發明之保護層開口之改良結構係利用略 呈一圓形輪廓之開口，而開口靠近於傳輸線之輪廓係為一 直線或一弧線’以使電流通過此開口時其密度均勻分彳布在 直線或弧線上，進而改善電流擁擠的現象。此外，藉由改 良後之開口結構’銲墊與球底金屬層（UBM)之間因電致、f 移所造成之開路’亦可獲得改善，以提高晶片之使 ^ 命。 可
U57ltwf .ptd 第9頁 1227556 五、發明說明（6) 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。
11571twf.ptd 第10頁 1227556 圖式簡單說明 第1圖繪示習知一種保護層之開口結構的俯視示意 圖。 第2圖繪示本發明一較佳實施例之一種保護層開口之 改良結構的俯視示意圖。 第3圖繪示本發明一較佳實施例之另一種保護層開口 之改良結構的俯視不意圖。 【圖式標示說明】 1 0 0 ·晶片 102 :主動表面 104 :保護層 _ 106 ··開口 1 0 8 :輪麼表面 11 0 :銲墊 112 :上表面 11 4 :傳輸線 11 6 :圖案化線路層 200 :晶片 202 :主動表面 2〇4 :保護層 b 206、2 0 7 :開口 208 :直線 2 0 9 :弧線 208a 、 209a :圓弧 2 1 0 :銲墊
11571twf.ptd 第11頁 1227556
11571twf.ptd 第12頁

Claims (1)

1227556 六、申請專利範圍 1 •一種晶片結構，至少包栝·· 晶片，具有至少一銲墊以及連接該銲墊之一傳輸 線，=於該晶片之表面上；以及 得输 pa 保《又層復蓋於該晶片之表面上，該保護層具有一 接訪^露出該銲墊’其中該開口之輪廓係由-直線以及 4線之兩端的一圓弧所構成，且該直線靠近於該傳 輸線連接至該銲墊之一端。 吁 其中該直 其中該直 其中保護 其中保護 2·如申請專利範圍第1項所述之晶片結構 線之長度小於等於該圓弧之半徑。 如申請專利範圍第丨項所述之晶片結構 备 又度係介於該圓弧之半徑與直徑之間。 % & &如申請專利範圍第1項所述之晶片結構 層係為一有機保護層。 ^如申請專利範圍第丨項所述之晶片結構 層你為一無機保護層。 •種晶片結構，至少包括： 線 晶片’具有至少一銲墊以及連接該銲墊之一傳輸 =該鲜塾與該傳輸線係位於該晶片之表面：以及 复保$層’覆蓋於該晶片之表面，該保護層具有一開 接該^暴路出邊銲墊，而該開口之輪廓係由一弧線以及連 狐^ ^線之兩端的一圓弧所構成，其中該弧線凹陷於該圓 ^ ? ’且該孤線靠近於該傳輸線連接至該銲墊之一端。 線上任^申請專利範圍第6項所述之晶片結構’其中該孤 、’ * —點與該傳輪線連接至該銲墊之該端的距離係等距 ll571twf.Ptd 第13頁 1227556 六、申請專利範圍 分布。 8. 如申請專利範圍第6項所述之晶片結構，其中該弧 線之曲率小於等於該圓弧的曲率。 9. 如申請專利範圍第6項所述之晶片結構，其中該弧 線之曲率大於等於該圓狐的曲率。 1 0.如申請專利範圍第6項所述之晶片結構，其中保護 層係為一有機保護層。 11.如申請專利範圍第6項所述之晶片結構，其中保護 層係為一無機保護層。
11571twf.ptd 第14頁
TW092119227A 2003-07-15 2003-07-15 Chip structure TWI227556B (en)

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TW092119227A TWI227556B (en) 2003-07-15 2003-07-15 Chip structure
US10/710,401 US7049705B2 (en) 2003-07-15 2004-07-08 Chip structure

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TW200503220A TW200503220A (en) 2005-01-16
TWI227556B true TWI227556B (en) 2005-02-01

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