TW477047B - Method for forming bumps by using copper as solder pads - Google Patents

Method for forming bumps by using copper as solder pads Download PDF

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Publication number
TW477047B
TW477047B TW090111075A TW90111075A TW477047B TW 477047 B TW477047 B TW 477047B TW 090111075 A TW090111075 A TW 090111075A TW 90111075 A TW90111075 A TW 90111075A TW 477047 B TW477047 B TW 477047B
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Taiwan
Prior art keywords
copper
protective layer
bump
pad
opening
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TW090111075A
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Chinese (zh)
Inventor
Yan-Ming Chen
Guo-Wei Lin
Jeng-Yu Ju
Yang-Tung Fan
Fu-Jie Fan
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Taiwan Semiconductor Mfg
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Priority to TW090111075A priority Critical patent/TW477047B/en
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Publication of TW477047B publication Critical patent/TW477047B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The method comprises: forming a copper pad on a wafer, and depositing a passivation layer on the copper pad, wherein the passivation layer is stacked by two or more individual layers; next, etching the passivation layer without exposing the metal pad, and forming an under bump metallurgy layer by sputtering deposition before performing the sputtering deposition of the in-situ ion milling on the under bump metallurgy layer and after exposing the copper pad; next, forming a photoresist pattern with an opening on the copper pad and under bump metallurgy layer by photolithography process; plating tin and removing the photoresist pattern to form a tin bump; using the tin bump as an etching mask to etch the exposed under bump metallurgy layer; then, performing a reflow to form a ball structure due to the surface tension of the tin bump, thereby completing the manufacture of the tin bump.

Description

477047477047

五、發明說明(1) 發明領域: 本發明與一種積體電路製程有關,特別是有關於_種應用 銅為銲墊於凸塊形成製程(bumping process)中之方法。 發明背景: 在極大型積體電路(ULSI)趨勢中,半導體元件的尺寸不 地縮小,用以不斷地提昇晶圓上元件之積集度。隨著 = 元件尺寸的縮小化後,在積體電路的製造過程上出 2戰。a外’由於電腦以及通訊技術之蓬勃發展,伴: =要的是更多不同種類與應用之電子元件。例如, ^ 操作之電腦界面或其他通訊之界面均需要許 :1 二不同類型之半導體元件。…積體電路之趨 會朝向高積集度發展、然而’近幾年來 3仍:V. Description of the invention (1) Field of the invention: The present invention relates to an integrated circuit manufacturing process, and particularly relates to a variety of applications. Copper is a method for bonding pads in a bumping process. BACKGROUND OF THE INVENTION: In the ultra-large integrated circuit (ULSI) trend, the size of semiconductor components is constantly shrinking to continuously increase the accumulation of components on wafers. With the reduction of the component size, there are two battles in the manufacturing process of integrated circuits. awai ’Because of the rapid development of computer and communication technology, the following: = What we need is more electronic components of different types and applications. For example, ^ operating computer interface or other communication interface needs to allow: 1 2 different types of semiconductor components. … The trend of integrated circuits will develop towards a high degree of integration, but ’in recent years 3 still:

發展又階進導Z 不但越來越多密度亦越來趟古,:π ic+導體的J/0數目 隨之越來越多,速度的要长7 仔封裝70件的引腳數亦 越來越大,所以增進封J來越快,導致元件耗功率 前,封裝也越做越小以勢則曰趨重要。@ 封裝也伴隨球矩陣排列封震 3 m高數量I/O之 BGA封裝)技術之發展而有所* 1 grid array ;簡稱 責I / 0的引腳為球狀較導線竿 A構裝的特點是’負 且不易受損變形,i封鞋/、構裝70件之細長引腳距離短 裝疋件之電性的傳輸距離短速度 4//U4/The development and advanced guidance Z is not only more and more dense, but also more and more ancient: the number of π ic + conductors J / 0 is increasing, and the speed is longer. The number of pins of 70 pieces is increasing. The larger the size, the faster the increase of the package J, leading to component power consumption before the package is getting smaller and smaller. @ Package is also accompanied by the development of the ball matrix array to seal the 3 m high number of I / O BGA packages) technology development * 1 grid array; I / 0 pins for short are more spherical than the structure of the wire rod A It is' negative and not easy to be damaged and deformed. I seal shoes /, the length of the 70-piece slender pins and the short transmission distance are short. 4 // U4 /

快 可符合目前及未來數位系統迷度的需求 時覆晶封裝(flip chip)亦為 , 滅 勢,此技術是利用導俨Λ/新一代封裝技術之趨·贫 體錫凸塊的製^ 為輪入/輸出。對於形成導 刻製程Hilt異ϊ!ΐ銘金屬焊塾一,利用你 層之組合戶於丄-、路焊墊。再分別沈積阻障層與導電 後,利用! 一般的組成包含Cr/Cu、Ti/Cu。之 在鋁焊墊上且古„ ^ , 成圖案,形成的光阻圖案 導電声接Μ '、Ϊ 一 電鍍法形成錫於開窗之中與 等電層接觸’‘然後去除光阻圖案形成錫凸一 :用=塊作為蝕刻罩幕去除未被遮住‘電.、、' 二而元成錫凸塊製·,之後錫凸塊經熱流形】;電::。 …、、而,文限於鋁材質的種種限制,元件之尺 :突破。為符合各類元件在製程至〇.13微米及小 米以下之需[因&目前内連線使用銅製程代替㈣ 成為一種趨勢。這是源自於銅金屬本身在電性物性上 有的種種先天優勢,像是(丨)低電阻特性,(2) 二 ^電子遷移性(ant i— electr〇ffligrat i〇n),比鋁高四個數、 里級(3)良好的抗應力所致之空洞形成性質 (anti-stress induced void formation)等,可賦予元件 較佳的特性如速度較快,可降低c r 0 s s t a 1 k,及具有較小 的RC時間常數。 〃 χ ” 但銅金屬雖在電性物性上有較佳之表現,如低阻值,作有 不易蝕刻和易氧化矽化的缺點。因銅有易氧化之缺點, 477047 五、發明說明(3) 在1C前段製程完成,欲進行凸塊形成製程之前,銅羯基板 之表面情形不易控制。尤其在南溫J衣境下,銅金屬的氧化 非常快速,不同於鋁材質可能在數百埃之厚度便停止氧 化;而銅金屬表面形成氧化銅之後顯然不利於其作為導線 或其他電性物性之表現因為,氧化膜,除了造成凸塊下金 屬(under bump metal lurgy,UBM)和金屬墊的點著性變差 外,更增加了阻值。如何克服銅金屬在製程應用上的困 是目前業界所努力的目標之一。 發明目的: 種以銅為銲墊之凸塊形Flip chip packaging is also dying when it can meet the needs of current and future digital systems. This technology is a trend that uses lead-in / new-generation packaging technology to produce lean tin bumps. In / Out. For the formation of the conductive process Hilt different! Welding metal welding first, use your layer of the user in the welding pad. After depositing the barrier layer and conductive separately, use! The general composition includes Cr / Cu, Ti / Cu. ^ ^ On the aluminum pad, forming a pattern, forming a photoresist pattern conductive acoustic contact M ′, 电镀 a plating method to form tin in the window opening to contact the isoelectric layer '', and then removing the photoresist pattern to form a tin bump One: Use = block as an etching mask to remove the unshielded 'electricity ,,', and then make a tin bump. After that, the tin bump undergoes a thermal manifold.]; Electricity ::... The various limitations of aluminum materials, the scale of components: breakthrough. In order to meet the needs of various components in the process to 0.13 microns and millet [because & the current use of copper instead of ㈣ has become a trend in interconnects. This is derived from Copper metal itself has various inherent advantages in electrical properties, such as (丨) low-resistance characteristics, (2) two electron mobility (ant i-electr〇ffligrat i〇n), four numbers higher than aluminum The third level (3) has good anti-stress induced void formation properties, which can give the device better characteristics such as faster speed, can reduce cr 0 ssta 1 k, and has a smaller RC time constant. 〃 χ ”But copper has better electrical properties Performance, such as low resistance, has the disadvantages of being difficult to etch and easy to oxidize and silicify. Due to the shortcomings of copper, 477047 V. Description of the invention (3) Before the 1C process is completed, it is difficult to control the surface condition of the copper substrate before the bump forming process is performed. Especially in the South Wen J clothing environment, the copper metal oxidizes very quickly, unlike aluminum, it may stop oxidizing at a thickness of hundreds of angstroms; and the copper metal surface is obviously not conducive to its use as a wire or other electrical properties. This is because the oxide film, in addition to causing the poor bumping of the under bump metal lurgy (UBM) and the metal pad, also increases the resistance value. How to overcome the difficulty of copper metal in process application is one of the goals of the industry. Purpose of the invention: a bump shape with copper as the solder pad

本發明之主要目的,即是在提供一 成的方法。 本發明之另一目的可解決銅墊於排隊尊 生之問題(queue time issue),一般倍、下站製私所衍 控制queue time,不可放置過久,否:銅塾之產品必須 題,本發明因為在銅墊上有氮化層因、5墊將遭遇氧化問 氮化層在凸塊製作前應先被移除。 ’銅塾被保護’但 本發明之又一目的,在於使製程較 外的光罩蝕刻過程。 °支藝精簡,不需額 本發明提供一種以銅為銲塾之几^ 包含:形成一銅金屬墊於一晶圓之上,、取万凌,該方法 墊之上。接著,移除位於銅墊上之禺沈積護層於銅金屬 第一開口 ,但銅墊未自第一開口最噹二的°卩分護層以形成 恭露出,隨後於形成凸塊The main object of the present invention is to provide a method. Another object of the present invention is to solve the queue time issue of copper pads. Generally, the queue time is controlled by a private station, and it cannot be left for too long. It is invented that because there is a nitride layer on the copper pad, the 5 pad will encounter an oxide layer. The nitride layer should be removed before the bumps are made. 'Copper is protected'. Yet another object of the present invention is to make the mask etching process outside the process. ° Simplified support technology, no amount required The present invention provides a method for using copper as a soldering pad. The method includes: forming a copper metal pad on a wafer, taking Wanling, and using the method on the pad. Next, remove the yttrium deposited protective layer on the copper pad to the first opening of the copper metal, but the copper pad is not separated from the first opening to form a protective layer, and then form a bump, and then form a bump.

477047 五、發明說明(4) 下金屬層之前將第一開口内殘留之護層移除,以暴露銅 墊。然後形成凸塊下金屬層於第一開口内但不填滿該第_ 開口,及形成具有第二開口之光阻圖案使得第一開口内之 凸塊下金属層自第二開口暴露出。形成錫凸塊於第一及第 一開口之中’接著去除光阻圖案及以熱回流錫凸塊。 發明之詳細說明:477047 V. Description of the invention (4) Remove the remaining protective layer in the first opening before lowering the metal layer to expose the copper pad. Then, a metal layer under the bump is formed in the first opening without filling the first opening, and a photoresist pattern having a second opening is formed so that the metal layer under the bump in the first opening is exposed from the second opening. Forming a tin bump in the first and first openings' followed by removing the photoresist pattern and reflowing the tin bump with heat. Detailed description of the invention:

本發明揭露一種新的製作之方法,係利用銅為銲墊於導電 凸塊製程中。詳細說明如下,所述之較佳實施例只做一說 明非用以限定本發明。 參閲圖一,首先提供一完成1C前段製程之半導體基板2,The present invention discloses a new manufacturing method, which uses copper as a solder pad in a conductive bump manufacturing process. The detailed description is as follows. The described preferred embodiments are only used for illustration and are not intended to limit the present invention. Referring to FIG. 1, a semiconductor substrate 2 that completes the 1C front-end process is first provided.

該半導體基板2上形成一金屬焊墊(pad)4,之後沈積第一 護層6’沈積方式可用化學氣相沈積(CVD),如電襞增強 式化學氣相沈積法(P E C V D)。第一護層6材質之選擇可用任 何阻絕性佳之材質如氮化矽,碳化矽;在較佳實施例中使 用P E C V D法沈積氮化石夕’厚度約4 0 0 - 6 0 0埃之間。沈積第一 護層8於第一護層6之上,沈積方式可用化學氣相沈積等 法’第一護層8材質之選擇需和第一護層6不同,以取得車* 佳之餘刻選擇性,例如二氧化矽,旋塗玻璃S0G;在較f佳Λ 實施例中使用PECVD法沈積二氧化矽。之後,沈積第=二 層10於第二護層8之上,沈積方式可用化學氣^沈積^善 厚度約為3000-4000埃。第三護層1〇材質之選擇較無阳 制,選擇不同於第二護層8材質較佳;在較佳實施^A metal pad 4 is formed on the semiconductor substrate 2, and then a first protective layer 6 'is deposited. A chemical vapor deposition (CVD) method, such as an electro-enhanced chemical vapor deposition method (PEC VD), may be used as a deposition method. The material of the first protective layer 6 can be selected from any material with excellent barrier properties such as silicon nitride and silicon carbide; in a preferred embodiment, the thickness of the nitrided stone is about 400-600 angstroms by using the P EC V D method. Deposit the first protective layer 8 on the first protective layer 6. The deposition method can be chemical vapor deposition. The material selection of the first protective layer 8 should be different from that of the first protective layer 6 in order to obtain a car. Properties, such as silicon dioxide, spin-on glass SOG; in a better embodiment, PECVD is used to deposit silicon dioxide. After that, the second layer 10 is deposited on the second protective layer 8. The deposition method can be deposited using chemical gas, and the thickness is about 3000-4000 angstroms. The material of the third protective layer 10 is more non-yang, and it is better to choose a material different from the second protective layer 8; in a better implementation ^

477047 五、發明說明(5) 使用PECVD法沈積氮化矽,厚度約為5 0 0 0-6 0 0 0埃。以上厚 度僅做為舉例,非用以限定本發明。 參閱圖二,利用微影製程曝光光阻將光罩圖案轉移至光阻 之中(未圖示),以光阻圖案做為蝕刻罩幕,將第三護層 1 〇、第二護層8餘刻至第一護層6為止,保留第一 ^層;繼 續做為護層避免暴露銅墊4。上述保留之第一護層以防 止晶圓在轉移製程站時或是等待下一製程過程時θ,避^底 層同材質4因暴露於大氣中而發生氧化現象。 一 請參見圖三,下一步驟係為形成凸塊下堆疊金屬; UBM(under bump metallurgy ; UBM),所使用方 /、, (sputtering)。賤鍍之前以同步(in_situ)離 (ion milling)銅墊4上部分之第一護層6, 二 以利後續在銅墊4上濺鍍UB歸如鎳層。恭路出銅墊4 第三護層Π之部分去除。上述所舉之材/ =過程亦將 式:做為一實施例用以說明’非用以限定本二=積T 故本發明之範圍包含均等功能材質之替換。 1中疋 參閱圖四,利用微影製程形成一具有 該凸塊下金屬12之上1後以習知=:光:圖案"於 成,可使用printing或電鍍法形成錫 丁錫凸塊形 用電鑛法。之後去除光阻圖案14形成錫=,本實施例, 示。-般在製作錫凸塊時所使 )丄6’如圖五所 ^ ^ j以摻雜鉛,依照477047 V. Description of the invention (5) The silicon nitride is deposited by PECVD with a thickness of about 5 0 0-6 0 0 0 Angstroms. The above thicknesses are merely examples, and are not intended to limit the present invention. Referring to FIG. 2, a photoresist is used to expose a photoresist to a photoresist pattern (not shown) by using a photolithography process. The photoresist pattern is used as an etching mask, and the third protective layer 10 and the second protective layer 8 are used. Until the first protective layer 6 is left, the first ^ layer is retained; continue to be used as a protective layer to avoid exposing the copper pad 4. The above-mentioned reserved first protective layer prevents the wafer from θ when transferring the processing station or waiting for the next process, and avoids the oxidation of the bottom layer with the same material 4 due to exposure to the atmosphere. 1 Please refer to FIG. 3. The next step is to form an under bump metallurgy (UBM), which is used by / ,, (sputtering). Before base plating, the first protective layer 6 on the copper pad 4 is ion-milled in-situ. Secondly, it facilitates subsequent sputter plating of the UB on the copper pad 4 as a nickel layer. The third protective layer Π of the copper pad 4 is removed from the road. The above-mentioned materials / = process also uses the formula: as an embodiment to illustrate the 'not to limit this two = product T, so the scope of the present invention includes replacement of equal functional materials. 1 中 疋 Referring to Figure 4, a lithography process is used to form a metal 1 with the bump under the bump 12. The conventional method is: = light: pattern " Yu Cheng, and a tin or tin bump can be formed using printing or electroplating. Use electricity mining method. After that, the photoresist pattern 14 is removed to form tin. This embodiment is shown in FIG. -Generally used when making tin bumps) 丄 6 ’as shown in Figure 5 ^ ^ j to doped lead, according to

第10頁 477047Page 10 477047

五、發明說明(6) 需求設定混合之比例用以調整熔點。接著,以錫凸塊16做 為钱刻罩幕,將暴露之U Β Μ金屬層1 2去除。之後經過助嫁 劑之塗佈(flux coating)以及熱流(refi〇w),將錫凸塊16 因内聚力等因素形成球狀結構完成錫球之製作,如圖六所 示。而在製作錫凸塊過程中,所述之開口 一般對 於金屬 墊4。 心、、 本發明之優點如下: I,供取代鋁銲墊以銅為銲墊之方法,並控制銅之氧化問 使製程過於複雜。痛、略舊有方式中,銘銲塾所需 時間早^ :層’因此可減少光罩蝕刻次數,縮短等候 于間,達到高效能量產之目的。 之半综導上體?構本該發: 基板中ui : 構包含:銅金屬塾,形成於- 於該第一護層之I該鋼金屬塾之上;$二護層,形 中’該第一護層自該開護!包含開口形成於其 避免該銅金屬塾氧^路,/、中上述之余一護層可 上述第二護層包:=中該第二護層為複層結構,其中 層。 3乳化層、氮化層。第-護層包含氮化 於完成凸塊後之主道μ ^ ‘基板中;第導體結構包含:銅金屬塾,形成於 弟遵層’形於銅金屬墊之上;第二護層,形 477047 五、發明說明(7) 於第一護層之上,其中第一護層、第二護層包含開口形成 於其中;凸塊下金屬層,形成於開口内但不填滿該開口; 錫凸塊,形成於該開口之中。 以上所述係利用一較佳實施例詳細說明本發明,而非限制 本發明之範圍,而且熟知此類技藝人士皆能明瞭,適當而 作些微的改變及調整,仍將不失本發明之要義所在,亦不 脫離本發明之精神和範圍。V. Description of the invention (6) The mixing ratio is required to adjust the melting point. Next, the tin bump 16 is used as a mask for money engraving, and the exposed BM metal layer 12 is removed. After the flux coating and heat flow (refiow), the solder bumps 16 are formed into spherical structures due to cohesion and other factors to complete the production of solder balls, as shown in Figure 6. In the process of making a tin bump, the opening is generally directed to the metal pad 4. The advantages of the present invention are as follows: I. It is a method for replacing the aluminum pad with copper as the pad, and controlling the oxidation of copper makes the process too complicated. In the painful and slightly old method, the time required for the soldering process is as early as ^: layer ', which can reduce the number of mask etchings, shorten the waiting time, and achieve the purpose of efficient energy production. Half of the integrated upper body? The structure should be: ui in the substrate: the structure contains: copper metal 塾, formed on-the steel metal I on the first protective layer; $ two protective layers, in the shape of 'the first protective layer from the opening Protect! Containing openings formed in the copper metal to prevent oxygen oxidation, the other protective layer mentioned above may be the second protective layer package: the second protective layer is a multi-layer structure, in which a layer is formed. 3Emulsified layer and nitrided layer. The first protective layer includes nitrided in the main channel μ ^ 'substrate after the bump is completed; the second conductor structure includes: copper metal 形成 formed on the bottom layer' on the copper metal pad; the second protective layer, shaped 477047 V. Description of the invention (7) On the first protective layer, wherein the first protective layer and the second protective layer include an opening formed therein; a metal layer under the bump is formed in the opening but does not fill the opening; tin A bump is formed in the opening. The above description uses a preferred embodiment to describe the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will understand that appropriate changes and adjustments will still be made without departing from the spirit of the present invention. It does not depart from the spirit and scope of the present invention.

第12頁 477047 圖式簡單說明 圖式之簡單說明: 本發明的較佳實施例將於下列之說明文字中輔以下列圖形 做更詳細的闡述: 圖一所顯示為本發明沈積護層之半導體晶圓截面圖。 圖二所顯示為本發明蝕刻護層後形成凸塊前之半導體晶圓 截面圖。 圖三所顯示為本發明以濺鍍法形成凸塊下金屬層之半導體 晶圓截面圖。 圖四所顯示為本發明以電鍍形成導電錫凸塊之半導體晶圓 截面圖。 圖五所顯示為本發明蝕刻凸塊下金屬層之半導體晶圓截面 圖。 圖六所顯示為本發明形成錫球之半導體晶圓截面圖。 圖號說明: 基板2 銅墊4 第一護層6 ' 第二護層8 第三護層1 0 凸塊下金屬12 光阻圖案1 4 錫凸塊1 6Page 477047 Brief description of the drawings Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail with the following figures in the following explanatory text: Figure 1 shows the semiconductor deposited by the coating of the present invention Wafer cross section. FIG. 2 is a cross-sectional view of a semiconductor wafer before a bump is formed after the protective layer is etched according to the present invention. FIG. 3 is a cross-sectional view of a semiconductor wafer in which a metal layer under the bump is formed by a sputtering method according to the present invention. FIG. 4 is a cross-sectional view of a semiconductor wafer in which conductive tin bumps are formed by electroplating according to the present invention. FIG. 5 is a cross-sectional view of a semiconductor wafer with an under-bump metal layer according to the present invention. FIG. 6 is a cross-sectional view of a semiconductor wafer forming a solder ball according to the present invention. Description of drawing number: substrate 2 copper pad 4 first protective layer 6 'second protective layer 8 third protective layer 1 0 metal under bump 12 photoresist pattern 1 4 tin bump 1 6

Claims (1)

477047 六、申請專利範圍 申請專利範圍: 1. 一種以銅為鲜墊之凸塊形成方法,該方法包含·· 形成一銅金屬墊於一晶圓之上; 沈積護層於該銅金屬墊之上; 移除位於該銅墊上之護層的部分護層以形成第一開口,但 該銅塾未自該第一開口暴露出; 於形成凸塊下金屬層之前將該第一開口内殘留之該護層移 除,以暴露銅墊; 形成凸塊下金屬層於該第一開口内但不填滿該第一開口; 形成具有第二開口之光阻圖案使得該第一開口内之凸塊下 金屬層自該第二開口暴露出; 形成錫凸塊於該第一及第二開口之中; 去除該光阻圖案;及 以熱回流該錫凸塊。 2. 如申請專利範圍第1項之以銅為銲墊之凸塊形成方 法,其中以濺鍍形成該凸塊下金屬層。 ' 3. 如申請專利範圍第1項之以銅為銲墊之凸塊形成方法, 其中該第一開口内殘留之護層係藉同步離子束移除。 4. 如申請專利範圍第1項之以銅為銲墊之凸塊形成方法, 其中該護層至少包含第一絕緣層及第二絕緣層。477047 VI. Scope of patent application Patent scope: 1. A bump forming method using copper as a fresh pad, the method includes: forming a copper metal pad on a wafer; depositing a protective layer on the copper metal pad Part of the protective layer on the copper pad is removed to form a first opening, but the copper cymbal is not exposed from the first opening; before the metal layer under the bump is formed, the remaining part of the first opening remains The protective layer is removed to expose the copper pad; a metal layer under the bump is formed in the first opening but does not fill the first opening; a photoresist pattern having a second opening is formed so that the bump in the first opening is formed A lower metal layer is exposed from the second opening; a tin bump is formed in the first and second openings; the photoresist pattern is removed; and the tin bump is reflowed with heat. 2. The method for forming a bump using copper as a solder pad as described in item 1 of the application, wherein the metal layer under the bump is formed by sputtering. '3. For example, the method for forming bumps using copper as a bonding pad in item 1 of the scope of the patent application, wherein the protective layer remaining in the first opening is removed by a synchronous ion beam. 4. The method for forming a bump using copper as a solder pad according to item 1 of the scope of the patent application, wherein the protective layer includes at least a first insulating layer and a second insulating layer. 477047 六、申請專利範圍 5. 如申請專利範圍第4項之以銅為銲墊之凸塊形成方法, 其中該第一開口内殘留之護層係為位於該銅墊上之第一絕 緣層。 6. 如申請專利範圍第4項之以銅為銲墊之凸塊形成方法, 其中該第一絕緣層包含氮化矽層且第二絕緣層包含氧化 ^ 〇 7.—種以銅為鲜塾之凸塊形成方法,該方法包含: 形成一銅金屬墊於一晶圓之上; 形成第一護層於該銅金屬墊之上; 形成第二護層於該第一護層之上; 移除位於該銅墊上之第二護層的部分以形成第一開口,但 該第一護層自該第一開口中暴露出; 於形成凸塊下金屬層之前將該第一開口内該第一護層移 除,以暴露銅墊; 形成凸塊下金屬層於該第一開口内但不填滿該龛一開口; 形成具有第二開口之光阻圖案使得該第一開口内之凸塊下 金屬層自該第二開口暴露出; 形成錫凸塊於該第一及第二開口之中; 去除該光阻圖案;及 以熱回流該錫凸塊。477047 6. Scope of patent application 5. For the method for forming bumps using copper as a solder pad in item 4 of the scope of patent application, wherein the protective layer remaining in the first opening is a first insulating layer on the copper pad. 6. The method for forming bumps using copper as a solder pad as described in item 4 of the scope of patent application, wherein the first insulating layer includes a silicon nitride layer and the second insulating layer includes an oxide ^ 〇7.—A kind of fresh copper A bump forming method, the method comprising: forming a copper metal pad on a wafer; forming a first protective layer on the copper metal pad; forming a second protective layer on the first protective layer; A portion of the second protective layer on the copper pad is removed to form a first opening, but the first protective layer is exposed from the first opening; the first opening in the first opening is formed in the first opening before the metal layer under the bump is formed. The protective layer is removed to expose the copper pad; a metal layer under the bump is formed in the first opening but does not fill the first opening; a photoresist pattern having a second opening is formed so that the bump under the first opening is under the bump A metal layer is exposed from the second opening; a tin bump is formed in the first and second openings; the photoresist pattern is removed; and the tin bump is reflowed with heat. 477047 六、申請專利範圍 8. 如申請專利範圍第7項之以銅為銲墊之凸塊形成方 法,其中該第二護層為複層結構。 9. 如申請專利範圍第8項之以銅為銲墊之凸塊形成方法, 其中上述第二護層包含氧化層、氮化層。 1 0.如申請專利範圍第7項之以銅為銲墊之凸塊形成方 法,其中該第一護層包含氮化層。 11.如申請專利範圍第7項之以銅為銲墊之凸塊形成方 法,其中以濺鍍形成該凸塊下金屬層。 1 2.如申請專利範圍第7項之一種以銅為銲墊之凸塊形成方 法,其中在濺鍍形成該凸塊下金屬層前,以同步離子束移 除該第一護層以暴露出該銅金屬墊。 1 3. —種利於以銅為銲墊製作凸塊之半導體結構,該半導 體結構包含: 銅金屬墊,形成於一基板中; ' 第一護層,形於該銅金屬墊之上; 第二護層,形於該第一護層之上,其中該第一護層包含開 口形成於其中,該第一護層自該開口中暴露; 其中上述之第一護層可避免該銅金屬墊氧化。 1 4.如申請專利範圍第1 3項之利於以銅為銲墊製作凸塊之477047 VI. Scope of patent application 8. For the bump formation method using copper as a solder pad in item 7 of the scope of patent application, the second protective layer is a multi-layer structure. 9. The method for forming bumps using copper as a solder pad according to item 8 of the scope of patent application, wherein the second protective layer includes an oxide layer and a nitride layer. 10. The method for forming bumps using copper as a bonding pad according to item 7 of the scope of the patent application, wherein the first protective layer includes a nitride layer. 11. The method for forming a bump using copper as a bonding pad according to item 7 of the scope of the patent application, wherein the metal layer under the bump is formed by sputtering. 1 2. A method for forming a bump using copper as a bonding pad as described in item 7 of the scope of the patent application, wherein before the metal layer under the bump is formed by sputtering, the first protective layer is removed by a synchronous ion beam to expose The copper metal pad. 1 3. —A semiconductor structure that facilitates the production of bumps using copper as a solder pad. The semiconductor structure includes: a copper metal pad formed in a substrate; a first protective layer formed on the copper metal pad; a second A protective layer formed on the first protective layer, wherein the first protective layer includes an opening formed therein, and the first protective layer is exposed from the opening; wherein the first protective layer described above can prevent the copper metal pad from being oxidized . 1 4. If item 13 of the scope of patent application is beneficial to the production of bumps with copper as the solder pad 第16頁 477047 六、申請專利範圍 半導體結構,其中該第二護層為複層結構。 1 5.如申請專利範圍第1 4項之利於以銅為銲墊製作凸塊之 半導體結構,其中上述第二護層包含氧化層、氮化層。 1 6.如申請專利範圍第1 3項之利於以銅為銲墊製作凸塊之 半導體結構,其中該第一護層包含氮化層。 1 7. —種利於以銅為銲墊製作凸塊之半導體結構,該半導 體結構包含: 銅金屬墊,形成於一基板中; 第一護層,形於該銅金屬墊之上; 第二護層,形於該第一護層之上,其中該第一護層、該第 二護層包含開口形成於其中; 凸塊下金屬層,形成於該開口内但不填滿該開口; 錫凸塊,形成於該開口之中。 1 8.如申請專利範圍第1 7項之利於以銅為銲墊製'作凸塊之 半導體結構,其中該第二護層為複層結構。 1 9.如申請專利範圍第1 8項之利於以銅為銲墊製作凸塊之 半導體結構,其中上述第二護層包含氧化層、氮化層。 2 0.如申請專利範圍第17項之利於以銅為銲墊製作凸塊之Page 16 477047 6. Scope of patent application Semiconductor structure, wherein the second protective layer is a multi-layer structure. 1 5. According to item 14 of the scope of the patent application, a semiconductor structure which is advantageous for making bumps by using copper as a bonding pad, wherein the second protective layer includes an oxide layer and a nitride layer. 16. According to claim 13 of the scope of the patent application, a semiconductor structure is advantageous for making bumps by using copper as a bonding pad, wherein the first protective layer includes a nitride layer. 1 7. —A semiconductor structure that facilitates the production of bumps using copper as a solder pad. The semiconductor structure includes: a copper metal pad formed in a substrate; a first protective layer formed on the copper metal pad; a second protective layer Layer formed on the first protective layer, wherein the first protective layer and the second protective layer include openings formed therein; a metal layer under the bump is formed in the opening but does not fill the opening; A block is formed in the opening. 1 8. According to claim 17 of the scope of patent application, a semiconductor structure made of copper as a bonding pad is advantageous for the semiconductor structure, wherein the second protective layer is a multi-layer structure. 1 9. According to claim 18 of the scope of the patent application, a semiconductor structure which is advantageous for making bumps by using copper as a bonding pad, wherein the second protective layer includes an oxide layer and a nitride layer. 2 0. If item 17 of the scope of patent application is beneficial to the production of bumps with copper as the pad 477047 六、申請專利範圍 半導體結構,其中該第一護層包含氮化層 1^· 第18頁477047 6. Scope of patent application Semiconductor structure, wherein the first protective layer includes a nitride layer 1 ^ · page 18
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108857612A (en) * 2018-07-21 2018-11-23 苏州三骏工具科技有限公司 The production method of milling cutter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108857612A (en) * 2018-07-21 2018-11-23 苏州三骏工具科技有限公司 The production method of milling cutter

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