TWI227509B - Semiconductor device and the manufacturing method thereof - Google Patents

Semiconductor device and the manufacturing method thereof Download PDF

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Publication number
TWI227509B
TWI227509B TW092118351A TW92118351A TWI227509B TW I227509 B TWI227509 B TW I227509B TW 092118351 A TW092118351 A TW 092118351A TW 92118351 A TW92118351 A TW 92118351A TW I227509 B TWI227509 B TW I227509B
Authority
TW
Taiwan
Prior art keywords
film
aforementioned
insulating film
semiconductor device
region
Prior art date
Application number
TW092118351A
Other languages
English (en)
Chinese (zh)
Other versions
TW200414273A (en
Inventor
Toshihiko Iinuma
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of TW200414273A publication Critical patent/TW200414273A/zh
Application granted granted Critical
Publication of TWI227509B publication Critical patent/TWI227509B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H10D64/0112—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW092118351A 2002-07-10 2003-07-04 Semiconductor device and the manufacturing method thereof TWI227509B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002201127A JP2004047608A (ja) 2002-07-10 2002-07-10 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
TW200414273A TW200414273A (en) 2004-08-01
TWI227509B true TWI227509B (en) 2005-02-01

Family

ID=30112550

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092118351A TWI227509B (en) 2002-07-10 2003-07-04 Semiconductor device and the manufacturing method thereof

Country Status (4)

Country Link
US (2) US6770942B2 (enExample)
JP (1) JP2004047608A (enExample)
CN (1) CN1248317C (enExample)
TW (1) TWI227509B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005005510A (ja) * 2003-06-12 2005-01-06 Toshiba Corp 半導体装置及びその製造方法
US7023059B1 (en) * 2004-03-01 2006-04-04 Advanced Micro Devices, Inc. Trenches to reduce lateral silicide growth in integrated circuit technology
US20060040481A1 (en) * 2004-08-17 2006-02-23 Bor-Wen Chan Methods and structures for preventing gate salicidation and for forming source and drain salicidation and for forming semiconductor device
JP2006128605A (ja) * 2004-09-29 2006-05-18 Toshiba Corp 半導体装置の製造方法
JP2008071890A (ja) * 2006-09-13 2008-03-27 Toshiba Corp 半導体装置及びその製造方法
KR100809335B1 (ko) 2006-09-28 2008-03-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
JP2008103465A (ja) * 2006-10-18 2008-05-01 Toshiba Corp 半導体装置及びその製造方法
US20080116521A1 (en) 2006-11-16 2008-05-22 Samsung Electronics Co., Ltd CMOS Integrated Circuits that Utilize Insulating Layers with High Stress Characteristics to Improve NMOS and PMOS Transistor Carrier Mobilities and Methods of Forming Same
US7534678B2 (en) * 2007-03-27 2009-05-19 Samsung Electronics Co., Ltd. Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
US7902082B2 (en) 2007-09-20 2011-03-08 Samsung Electronics Co., Ltd. Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers
US8134208B2 (en) * 2007-09-26 2012-03-13 Globalfoundries Inc. Semiconductor device having decreased contact resistance
US7923365B2 (en) 2007-10-17 2011-04-12 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon
TWI462294B (zh) * 2010-09-21 2014-11-21 Toshiba Kk Semiconductor element and manufacturing method thereof
JP5687582B2 (ja) 2010-09-21 2015-03-18 株式会社東芝 半導体素子およびその製造方法
US20120119302A1 (en) 2010-11-11 2012-05-17 International Business Machines Corporation Trench Silicide Contact With Low Interface Resistance
CN103855023A (zh) * 2012-12-04 2014-06-11 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法及半导体器件
JP6178118B2 (ja) * 2013-05-31 2017-08-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10428931B2 (en) * 2017-02-27 2019-10-01 Toyota Motor Engineering & Manufacturing North America, Inc. Braze preform for powder metal sintering

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545581A (en) * 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
JPH11204791A (ja) * 1997-11-17 1999-07-30 Toshiba Corp 半導体装置及びその製造方法
US5915199A (en) * 1998-06-04 1999-06-22 Sharp Microelectronics Technology, Inc. Method for manufacturing a CMOS self-aligned strapped interconnection
US6323103B1 (en) * 1998-10-20 2001-11-27 Siemens Aktiengesellschaft Method for fabricating transistors
JP3205306B2 (ja) * 1998-12-08 2001-09-04 松下電器産業株式会社 半導体装置およびその製造方法
JP4010724B2 (ja) 1999-12-28 2007-11-21 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
US20040007745A1 (en) 2004-01-15
JP2004047608A (ja) 2004-02-12
CN1472820A (zh) 2004-02-04
US7049222B2 (en) 2006-05-23
TW200414273A (en) 2004-08-01
US6770942B2 (en) 2004-08-03
CN1248317C (zh) 2006-03-29
US20040241936A1 (en) 2004-12-02

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees