TW586192B - A method of fabricating a semiconductor package - Google Patents

A method of fabricating a semiconductor package Download PDF

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TW586192B
TW586192B TW091124154A TW91124154A TW586192B TW 586192 B TW586192 B TW 586192B TW 091124154 A TW091124154 A TW 091124154A TW 91124154 A TW91124154 A TW 91124154A TW 586192 B TW586192 B TW 586192B
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adhesive
wafer
film
chinese
application
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TW091124154A
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Xiping He
Christopher J Dominic
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Nat Starch Chem Invest
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

586192 玖、發明說明 【發明領域】 本發明有關一種用於製作半導體封裝之黏著劑及黏接 方法〇其特別有用於製作晶片規模及堆疊晶片封裝〇 【發明背景】 晶片規模封裝（CSP)在半導體封裝內提供重量輕、印 子小、密度高、及電性能提升之優點〇包括一或更多彼此 堆疊之積合半導體晶片之CSP進一步提升電性能，且將空 間及重量減小。 半導體係以機械方式及電連接至基質，後者依次連接 至其他裝置或外來電源。基質可爲剛性譬如金屬線框、陶 瓷或層合板，或者可爲可撓譬如聚醯亞胺帶〇 一種將半導體連接至其基質之方法稱爲線黏接，其中 半導體晶片先用糊狀或膜狀黏著劑黏著於基質，然後用一 細金屬線將晶片..t之有效端子黏接於基質上之有效端子〇 以往，糊狀黏著劑較膜狀黏著劑常被使用〇然而，一 些CSP更成功使用膜狀黏著劑加以製作，因爲膜能更精確 配合晶片構形（x-y公差），黏著劑滲開少或無，且黏接 線厚度及黏接線傾斜更容易控制〇 然而，在生產晶片規模及堆疊晶片規模封裝時，膜方 法及設備添加成本及增加處理時間〇半導體組件係用通常 稱爲a揀放〃設備之置放機置於其等之適當基質上〇此種 設備對於可靠且準確置放組件至足以以成本效益方式符合 通量要求爲屬重要。 在一使用膜狀黏著劑製作CSP之方法中，自膜切出-- ΙΖί續次頁 發明說明頁不敷使丨a時，請註記並使闬續頁） 586192 發明說明_胃 花樣，揀拾並置於基質上，再以壓力及熱予層合〇然後揀 拾一半導體晶片並置於黏著劑上，再以壓力及/或熱層合 於黏著劑〇除揀放設備外，此方法需要特殊之膜處理及層 合設備◦ 在另一使用膜狀黏著劑之方法中，沖出一花樣並用壓 力及/或熱層合於基質上，然後揀拾一半導體晶片並置於 黏著劑上，再以壓力及/或熱層合於黏著劑。此方法需要 一單獨之沖床組用於各別形狀之所需花樣、以及特殊之沖 床與膜層合設備。 堆疊晶片CSP亦可使用上述二方法及設備製作，雖然 所需之膜材料可能需爲不同厚度及顯現不同之流動特性0 堆疊晶片用程序伴隨揀放膜狀黏著劑之花樣於基質上、施 加熱與壓力、揀放該晶片於該黏著劑上、以及施加熱與壓 力◦重複該程序，但黏著劑花樣在此情況下係置於第一（ 母）晶片頂部並層合，繼而將一相同或不同幾何形狀之第 二（子）晶片置於母晶片上〇然後將子晶片層合。通常’ 對於母及子二者晶片之置放及層合均可能需要特殊之膜層 合設備〇 在另一方法中，將黏著劑膜直接層合於半導體晶圓之 背側，然後用典型晶片切割設備切成個別之晶片（單一化 )〇黏著劑保持層合於個別晶片，於是揀拾晶片並置於基 質上，或晶片堆疊情況F之另一晶片上◦晶片用壓力及/ 或熱層合於基質或第一晶片0此方法需要特殊之膜層合設 備以及特殊之膜晶片黏接設備0 586192 發明說明 儘管CSP及堆疊晶片CSP用膜狀黏著劑有優點，但半 導體封裝工業中較重要之部門則因塗施糊狀黏著劑所用程 序及設備之較低成本、使用容易性、及此設備在工業中之 可利用性而偏好之〇 使用糊狀黏著劑將半導體晶片黏接於基質之標準揀放 設備先將糊狀黏著劑分配於基質上，然後揀拾晶片並將該 晶片置於黏著劑上。於置放期間基質所停放之置放臺可予 加熱或不加熱，但由揀放工具施加之壓力可用以將晶片黏 附之品質最佳化〇此類型之設備通常不具備後層合能力， 且目前較使用薄膜所需之設備廉價〇 使用此類型設備之揀放、加熱、及壓力組件以膜黏著 劑生產半導體封裝（具有單一晶片或堆疊晶片）之潛勢將 成爲時間及成本上之優點〇昂貴之沖床組及層合組件被免 除，且操作本身使用較少時間〇此外，典型之半導體封裝 程序需要晶圓切割能力，而經由正確選擇膜之物理性質， 切割設備可用以將膜狀黏著劑切成適當之構形0 【本發明綜述】 今發現，C S P或堆疊晶片C S P之製作可使用所建構供 用於糊狀黏著劑之標準晶片黏附設備以一無支承之膜狀黏 著劑或一支承於剛性載體上之黏著劑予以完成0本發明係 一種使用無支承之膜狀黏著劑或支承於剛性載體上之黏著 劑製作半導體之方法ο 【本發明詳述】 該無支承黏著劑可爲任何模數高於12ϋ MPa且對晶圓 586192 發明說明_頁 切割帶黏性小於ϋ · 1 Μ P a之熱塑性、熱固性、或熱塑性加 熱固性黏著劑〇合宜之黏著劑爲環氧樹脂、m酸酯、聚醯 亞胺、矽氧烷聚醯亞胺、順丁烯二醯亞胺、矽酮或其等之 任何組合形式〇 有支承黏著劑由一剛性載體層構成，後者在一或二側 上塗覆之顯現小於0 · 1 MPa之對晶圓切割帶黏性之熱塑性 或熱固性黏著劑〇若二側均予塗覆，則各側上之黏著劑可 爲相同或不同之組成〇剛性層之存在便利切割及揀放期間 之處理，亦且在二黏接表面間需要特別厚且經控制之距離 之情況下作用如間隔物〇 剛性載體可爲無機材料譬如陶瓷、矽或金屬，或有機 材料譬如聚醯亞胺或聚酯，或任何組合形式之無機與有機 材料譬如FK及BT層合板，若總複合體顯現高於120 MPa之 模數及小於0 · 1 MPa之對切割帶黏性〇 在此等物理參數內，黏著劑不論有無支承均可藉用以 te理半導體晶圓之標準設備予以處理，譬如晶圓切割帶用 塗敷器、切割踞、及揀放設備（晶片黏接器與加熱器單位 )〇黏著劑係用標準晶圓切割帶層合設備塗敷於晶圓切割 帶0然後在切割矽晶圓之同一程序內將黏著劑鋸成個別之 K樣0 (此方法因免除對極薄、脆弱晶圓之超量處理及層 合而具有優於晶圓背側層合法之優點〇 ) 黏著劑黏附係以相同於使用典型糊狀黏合劑之晶片黏 附之方式執行。自晶圓切割帶揀拾黏著劑花樣並置於選定 基質上，且以壓力及/或熱層合於基質〇然後揀拾半導體 586192 發明說明 晶片並置放於該黏著劑上，並以壓力及/或熱層合〇 對於堆疊晶片規模封裝，將先前黏著之半導體晶片用 作基質依待疊合半導體晶片之數目所需多次重複該步驟ο 【實例】 以下實例1及2中，該膜狀黏著劑所具模數高於i 2 〇 Μ P a且對晶圓切割帶黏性小於〇 . 1 μ P a 〇實例3中之載體 不符合此等標準〇 實例1 :將一以1 2吋X 1 2吋X 1 2密耳厚片料提供之膜 狀熱固性環氧樹脂黏著劑（A b 1 e s t i k實驗室之R P 5 7 1 - 1 0 ) 在下列條件下用層合設備層合於BT層合板（Mitsubishi氣 體化學公司，8吋X 8吋X 8密耳厚）之二側上： 速率： 3 ϋ . 5厘米/分鐘
溫度： 1 3 5 °F 壓力： 4 ϋ p s i 然後將層合之黏著劑安裝於切割帶（Nitto SPV2 2 4 ) 上並用設定成下列參數之Disc〇 DAD 32ϋ切割機切割成4 毫米X 6毫米花樣：
刀片： NBC-ZH27HEEE 心軸速率： 3 0，0 0 0 r p m 進料速率： 2·54厘米/秒 切割模式： 向下切割 測試經切割之黏著劑以具有於二次試驗中設定成下列 參數之揀放能力之ESEC Die Bonder 2007 L0C晶片黏接器 處理之能力： 5- 586192 發明說明 試驗 #1 #2 揀拾Z高度（密耳） 177 177 揀拾時間（毫秒） 50 50 觸箔時間（毫秒） 60 0 針頂部高度（密耳） 45 45 注射器高度偏移（密耳） 9 . 8 9.8 針速（毫米/秒） 30 30 成功次數/測試次數 10/10 10/10 g式驗就二次觸滔時間中之每 一次測試十次 ，且對二 次觸箔時間中之每一次均成功十次〇此一實例顯示該黏著 劑能用標準揀放設備揀離晶圓切割帶〇 實例2 :將一單層之聚乙烯（America塑膠，30 · 48 厘米Χ3ϋ,48厘米χ3密耳厚）安裝於Nitto SPV-2 2 4切 割帶上，並用配有NBC-ZH27HEEE刀片、心軸速率爲30，〇ϋ〇 Γ P m 、而進料速率爲2 . 5 4厘米/秒之D 1 s c 0 D A D 3 2 0切割 機切割成4毫米X 6毫米大小◦切割條件爲： 切割模式： A 切割形狀： 正方形 心軸速率： 32,〇〇〇 rpn (1 工作厚度： 7密耳 帶厚度： 3密耳 刀片厚度： 2密耳 進料速率： ϋ . 5厘米/ 秒 Y指數： CH1 〇 · 4 塵米 586192 測試經切 力之 ESEC Die 揀拾z 揀拾時 觸箔時 針頂部 注射器 針速 黏接臂: 注射器: 針狀態. 黏接臂: 晶片厚j 針類型 成功次! 實例3 :: 密耳矽酮◦揀; 發明說明_胃 CH2 0 . 6厘米 割之聚乙烯以具有設定成下列參數之揀放能 Bonder 2 00 7 LOC晶片黏接器處理之能力： f度（毫米） 3曰1 (毫秒） 3曰1 (毫秒） 高度（毫米） 6·00至 5 · 52 600 至 6000 200 0 至 1 · 80 度偏移（毫米） 米/秒） 能 能 0 30 至 110 停放態位 校準態位 底態位 態位（毫米） 2.17 (毫米） 〇·17 圓頭 /測試次數 1 ϋ /1 ϋ 10/10 行與實例2相同之試驗，唯基質材料爲5 十次中失敗十次0 _7一

Claims (1)

  1. 586192 申請專利範圍 1 · 一種製作半導體封裝之方法，其中用一黏著劑膜將 --半導體晶片黏著於一基質，該方法包含： a ·提供一在晶圓切割帶上之膜狀黏著劑，其中該膜 狀黏著劑所具模數高於120 MPa而對該晶圓切割帶黏性小 於（K 1 MPa ; b .將該在晶圓切割帶上之膜狀黏著劑切割成一花樣 c .自該切割帶揀拾該黏著劑花樣並將該黏著劑花樣 置於一基質上； d.用壓力及/或熱將該黏著劑花樣層合於該基質上 9 e .將一半導體晶片揀放於該黏著劑上；以及 f .用壓力及/或熱將該晶片層合於該黏著劑上。 2 . —種製作半導體封裝之方法，其中一數量之半導體 晶片予以疊合，該方法包含先執行申請專利範圍第1項之 方法，然後將先前黏著之半導體晶片用作基質依待fi合半 導體晶片之數目所需多次重複申請專利範圍第1項之方法 〇 3 .如申請專利範圍第丨或2項之方法，其中該膜狀黏 著劑係一無支承之熱塑性或熱固性膜、或一支承於剛性載 體上之熱塑性或熱固性膜0 [D續次頁 (申請專利範圍頁+敷使用時’請註記並使用續頁）
    586192 (塡寫本書件時請先行詳閱申請書後之申請須知，作※記號部分請勿塡寫） ※申請案號：尹" >《/’jy ^PC分類："0 / L ※申請曰期：7/r // 7^ ^ ^- 壹、發明名稱 (中文）製作半導體封裝之方法_ (英文）A METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE Λ、發明人（共人） _ k 1 (如發明人超過一人，請塡說:明書發明人續頁) 姓名：(中文）希齊平_ (英文）He, Xiping__ 住居所地址：(中文）美國加州伽利多賽莫拉廣場13531號 (英文）13531 Semora Place, Cerritos, California 90703, USA 國籍：(中文）大陸人士_ (英文)_ 參、申請人（共丄人） 'I 申請人(如發明人超過一人，請塡說明書申請人續頁） · 姓名或名稱：(中文）阈民澱粉及化學投杳控股公司_ X National Starch and Chemical Investment _He444ng Corporation-- 住居所或營業所地址：(中文）羔阈裨衍瓦州新保侉砭吉女道1 ο ο 〇號 - (英文）1000 Uniqema Boulevard, New Castle. Delaware 19720. USA_ 蔵I籍：（中文）笔 m_—(英文) usa_ 代表人：(中文） 威廉哈金生_ (英文） Hutchinson, William J·_ 續發明人或申請人續頁（發明人或申請人欄位不敷使用時，請註記並使用續頁）
TW091124154A 2001-10-23 2002-10-18 A method of fabricating a semiconductor package TW586192B (en)

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WO2003036715A3 (en) 2003-11-13
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US20030087479A1 (en) 2003-05-08

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