TW584929B - Semiconductor device and dummy pattern placing method - Google Patents
Semiconductor device and dummy pattern placing method Download PDFInfo
- Publication number
- TW584929B TW584929B TW090109122A TW90109122A TW584929B TW 584929 B TW584929 B TW 584929B TW 090109122 A TW090109122 A TW 090109122A TW 90109122 A TW90109122 A TW 90109122A TW 584929 B TW584929 B TW 584929B
- Authority
- TW
- Taiwan
- Prior art keywords
- pattern
- dummy pattern
- dummy
- area
- mentioned
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims description 64
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000011295 pitch Substances 0.000 claims description 35
- 238000000926 separation method Methods 0.000 claims description 24
- 238000009826 distribution Methods 0.000 claims description 8
- 230000009466 transformation Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 238000012545 processing Methods 0.000 description 33
- 239000002184 metal Substances 0.000 description 31
- 229910052751 metal Inorganic materials 0.000 description 31
- 230000015572 biosynthetic process Effects 0.000 description 20
- 238000005498 polishing Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004513 sizing Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000117629 | 2000-04-19 | ||
| JP2001012789A JP4756746B2 (ja) | 2000-04-19 | 2001-01-22 | 半導体装置およびその製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW584929B true TW584929B (en) | 2004-04-21 |
Family
ID=26590372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW090109122A TW584929B (en) | 2000-04-19 | 2001-04-17 | Semiconductor device and dummy pattern placing method |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4756746B2 (enrdf_load_stackoverflow) |
| KR (1) | KR100429111B1 (enrdf_load_stackoverflow) |
| TW (1) | TW584929B (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI758408B (zh) * | 2018-02-09 | 2022-03-21 | 聯華電子股份有限公司 | 半導體結構 |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3479052B2 (ja) | 2001-04-23 | 2003-12-15 | 沖電気工業株式会社 | 半導体装置のダミー配置判定方法 |
| JP4620942B2 (ja) | 2003-08-21 | 2011-01-26 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク |
| JP4599048B2 (ja) | 2003-10-02 | 2010-12-15 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク |
| JP4284202B2 (ja) | 2004-02-04 | 2009-06-24 | パナソニック株式会社 | 面積率／占有率検証プログラム及びパターン生成プログラム |
| US7269818B2 (en) | 2005-01-06 | 2007-09-11 | International Business Machines Corporation | Circuit element function matching despite auto-generated dummy shapes |
| JP4322839B2 (ja) | 2005-04-11 | 2009-09-02 | エルピーダメモリ株式会社 | 半導体装置 |
| KR100650870B1 (ko) | 2005-08-08 | 2008-07-16 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자 및 그의 제조방법 |
| JP2007299898A (ja) | 2006-04-28 | 2007-11-15 | Matsushita Electric Ind Co Ltd | 半導体装置および半導体装置のレイアウト設計方法 |
| JP2008066716A (ja) * | 2006-08-10 | 2008-03-21 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| KR100789614B1 (ko) * | 2006-08-11 | 2007-12-27 | 동부일렉트로닉스 주식회사 | 더미 패턴 및 그 형성방법 |
| KR20080096215A (ko) * | 2007-04-27 | 2008-10-30 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
| US7771901B2 (en) | 2007-05-02 | 2010-08-10 | Dongbu Hitek Co., Ltd. | Layout method for mask |
| JP5184003B2 (ja) | 2007-08-28 | 2013-04-17 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路およびダミーパターンの配置方法 |
| JP6262060B2 (ja) * | 2014-04-03 | 2018-01-17 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3249317B2 (ja) * | 1994-12-12 | 2002-01-21 | 富士通株式会社 | パターン作成方法 |
| JP3128205B2 (ja) * | 1996-03-14 | 2001-01-29 | 松下電器産業株式会社 | 平坦化パターンの生成方法、平坦化パターンの生成装置及び半導体集積回路装置 |
| JPH1050843A (ja) * | 1996-07-30 | 1998-02-20 | Toshiba Microelectron Corp | 半導体集積回路及びその製造方法 |
| US5885856A (en) * | 1996-08-21 | 1999-03-23 | Motorola, Inc. | Integrated circuit having a dummy structure and method of making |
| JP3555074B2 (ja) * | 1999-11-17 | 2004-08-18 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
-
2001
- 2001-01-22 JP JP2001012789A patent/JP4756746B2/ja not_active Expired - Fee Related
- 2001-04-17 TW TW090109122A patent/TW584929B/zh not_active IP Right Cessation
- 2001-04-18 KR KR10-2001-0020782A patent/KR100429111B1/ko not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI758408B (zh) * | 2018-02-09 | 2022-03-21 | 聯華電子股份有限公司 | 半導體結構 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002009161A (ja) | 2002-01-11 |
| KR20010098704A (ko) | 2001-11-08 |
| JP4756746B2 (ja) | 2011-08-24 |
| KR100429111B1 (ko) | 2004-04-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |