KR100429111B1 - 반도체 장치 및 더미 패턴의 배치 방법 - Google Patents

반도체 장치 및 더미 패턴의 배치 방법 Download PDF

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Publication number
KR100429111B1
KR100429111B1 KR10-2001-0020782A KR20010020782A KR100429111B1 KR 100429111 B1 KR100429111 B1 KR 100429111B1 KR 20010020782 A KR20010020782 A KR 20010020782A KR 100429111 B1 KR100429111 B1 KR 100429111B1
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KR
South Korea
Prior art keywords
pattern
dummy pattern
region
dummy
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2001-0020782A
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English (en)
Korean (ko)
Other versions
KR20010098704A (ko
Inventor
가와시마히로시
오까다마사까즈
기따니다께시
이가라시모또시게
Original Assignee
미쓰비시덴키 가부시키가이샤
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Publication of KR20010098704A publication Critical patent/KR20010098704A/ko
Application granted granted Critical
Publication of KR100429111B1 publication Critical patent/KR100429111B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR10-2001-0020782A 2000-04-19 2001-04-18 반도체 장치 및 더미 패턴의 배치 방법 Expired - Fee Related KR100429111B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000-117629 2000-04-19
JP2000117629 2000-04-19
JP2001012789A JP4756746B2 (ja) 2000-04-19 2001-01-22 半導体装置およびその製造方法
JP2001-012789 2001-01-22

Publications (2)

Publication Number Publication Date
KR20010098704A KR20010098704A (ko) 2001-11-08
KR100429111B1 true KR100429111B1 (ko) 2004-04-29

Family

ID=26590372

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0020782A Expired - Fee Related KR100429111B1 (ko) 2000-04-19 2001-04-18 반도체 장치 및 더미 패턴의 배치 방법

Country Status (3)

Country Link
JP (1) JP4756746B2 (enrdf_load_stackoverflow)
KR (1) KR100429111B1 (enrdf_load_stackoverflow)
TW (1) TW584929B (enrdf_load_stackoverflow)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3479052B2 (ja) 2001-04-23 2003-12-15 沖電気工業株式会社 半導体装置のダミー配置判定方法
JP4620942B2 (ja) 2003-08-21 2011-01-26 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク
JP4599048B2 (ja) 2003-10-02 2010-12-15 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク
JP4284202B2 (ja) 2004-02-04 2009-06-24 パナソニック株式会社 面積率／占有率検証プログラム及びパターン生成プログラム
US7269818B2 (en) 2005-01-06 2007-09-11 International Business Machines Corporation Circuit element function matching despite auto-generated dummy shapes
JP4322839B2 (ja) 2005-04-11 2009-09-02 エルピーダメモリ株式会社 半導体装置
KR100650870B1 (ko) 2005-08-08 2008-07-16 주식회사 하이닉스반도체 플래쉬 메모리 소자 및 그의 제조방법
JP2007299898A (ja) 2006-04-28 2007-11-15 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置のレイアウト設計方法
JP2008066716A (ja) * 2006-08-10 2008-03-21 Matsushita Electric Ind Co Ltd 半導体装置
KR100789614B1 (ko) * 2006-08-11 2007-12-27 동부일렉트로닉스 주식회사 더미 패턴 및 그 형성방법
KR20080096215A (ko) * 2007-04-27 2008-10-30 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
US7771901B2 (en) 2007-05-02 2010-08-10 Dongbu Hitek Co., Ltd. Layout method for mask
JP5184003B2 (ja) 2007-08-28 2013-04-17 川崎マイクロエレクトロニクス株式会社 半導体集積回路およびダミーパターンの配置方法
JP6262060B2 (ja) * 2014-04-03 2018-01-17 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TWI758408B (zh) * 2018-02-09 2022-03-21 聯華電子股份有限公司 半導體結構

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6099992A (en) * 1994-12-12 2000-08-08 Fujitsu Limited Method for designing reticle, reticle, and method for manufacturing semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3128205B2 (ja) * 1996-03-14 2001-01-29 松下電器産業株式会社 平坦化パターンの生成方法、平坦化パターンの生成装置及び半導体集積回路装置
JPH1050843A (ja) * 1996-07-30 1998-02-20 Toshiba Microelectron Corp 半導体集積回路及びその製造方法
US5885856A (en) * 1996-08-21 1999-03-23 Motorola, Inc. Integrated circuit having a dummy structure and method of making
JP3555074B2 (ja) * 1999-11-17 2004-08-18 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6099992A (en) * 1994-12-12 2000-08-08 Fujitsu Limited Method for designing reticle, reticle, and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP2002009161A (ja) 2002-01-11
KR20010098704A (ko) 2001-11-08
JP4756746B2 (ja) 2011-08-24
TW584929B (en) 2004-04-21

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