TW518619B - Integrated circuit - Google Patents

Abstract

An integrated circuit comprises an inductor path (17) formed in a metal layer located in a surface structure on top of a substrate (7) that is electrically well conducting. Trenches (1) filled with an electrically isolating material are located under the inductor path and are arranged in a meshlike or grid pattern. In order to improve the shielding of the inductor path and to simultaneously improve the Q-value of the inductor, in the islands (5) of material formed in the surface structure between the meshes of the pattern deep substrate contacts (11) are located. The substrate contacts or contact pins extend down into the substrate and the substrate and the substrate contacts or contact pins are intended to be connected to ground potential. Electrically conducting areas (13) can cover the islands and are then connected to the substrate contacts.

Description

518619 _Case No. 90103022_ Year Month Amendment _ V. Description of the invention (1) Technical scope The present invention relates to a shielded inductor with an integrated circuit and an integrated circuit with a shielded inductor. BACKGROUND OF THE INVENTION Silicon diodes, CMOS and BiCMOS integrated circuits are currently used in high-speed applications in the frequency range of 1-3 GHz, which has replaced materials that could only previously be used in Group I I I and V of the periodic table. Inductor components are often required in high-frequency circuit building blocks, such as resonators and filters. The common problem for all integrated circuits is how to make the inductor have a sufficiently high quality factor or Q value, and a sufficiently high operating frequency, which is obviously limited by this resonance frequency. At present, the progress of the silicon process for the production of integrated circuits has allowed inductors to be arranged with a higher inductance value per unit area, and has lower losses due to reduced feature sizes, while multi-level metallization structures contain thick The oxide can assist the insulation of the inductor from the substrate. However, due to the electrical resistance of the metallization layer, electrical coupling with the substrate, and losses in the substrate, there will still be considerable losses. Therefore, it is difficult to obtain an inductor element in the range of 2 to 10 nH, which can have a Q-value higher than 10 in the frequency range of 1-2 GHz when an electronic integrated circuit is manufactured from a shixi material. . The integrated inductor usually has a square or octagonal strip configuration, but is set to a spiral shape. This Q-value decreases due to the conductive properties of the silicon substrate. By selectively removing the silicon located below the conductor forming the inductor, a higher Q-value and a higher self-resonant frequency can be obtained. Therefore, the Q-value can be increased by two coefficients due to such removal, for example, proposed by J. Y. -C. Chang, Α · Α · Abidi, M. Gaitan et al.

0: \ 69 \ 69200-911016.ptc Page 5 518619 _Case No. 90103022_Year Month and Date 倐 正 _ V. Description of the invention (2)

Suspended Inductor on Silicon and Their Use in a 2 βm CMOS RF Amplifier ”, Trans. El. Dev., Vo 1. 14, No. 5, p. 246, May 1993, and U.S. Patent by Abidi et al. 5,539,241. This removal can be used to cut the broken layer to create hundreds of air gaps, but this method is not practical for mass production, or can be used to manufacture the stacked body on the stone layer The general process of the circuit is compatible. In CP Yue, SS Wong, n0n-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF 1C's, f, J. So lid-State Circuits, Vol. 33, No. 5, p. 743, May 1998, inventors CP Yue and SS

Wong's filed international patent application proposal WO 98/50956 discloses a patterned ground shield layer under the inductor and above the semiconductor substrate. This design is due to the shielding effect on the induced current in the substrate and reduces the eddy current induced in the ground shield, and because the ground shield is patterned, in this way, the current cannot be in the metal under the inductor Circulation, refer to Figure la, lb of this proposal. In Burghartz et al., "Progress in RF Inductors on Silicon-Understanding MMIC Inductors," IEDM Tech. Digest, 1998, pp. 523-526, compares several different methods to reduce substrate loss. These The structure refers to a paper by CP Yue et al. And a patent application proposal by Yue et al. Research into integrating inductors on silicon structures is still ongoing. The results of their reports present contradictory phenomena. The correct mechanism of its loss, and the structural model optimized by the equivalent circuit, can be described in a physical, but not too simplified way, which remains to be discussed. An inductor with good characteristics

O: \ 69 \ 69200-911016.ptc Page 6 518619 ----_ Case No. 卯 切 山 失 _ 年月 g___ V. Description of the invention (3) Device structure, when used in an application circuit, sometimes That is, it cannot have good characteristics when used in other different circuits. For example, the electrical behavior of the inductor structure is based on the actual circuit, or more specifically, the structure that is actually surrounded. Therefore, it is difficult to determine the optimal structure of an inductor based on theoretical discussion or calculation. In the paper and related patents proposed by c. P. Yue et al., It can improve the performance of inductors. However, the metallization pattern must be continuous and must be connected to a fixed potential at some points, preferably several points, so that it can function well, like a shield. However, it does not propose a method to improve the effect of the substrate under the metallization pattern. At the same time, the pattern has an opening towards the substrate, in which an electromagnetic field can pass. According to our experiments and papers cited by Burghartz et al., Grounding the substrate close to the electrical conductors that make up the inductor can improve the value of q because highly conductive substrates with a well-defined potential, such as Can be used as a shield and reduce eddy current effects in silicon. However, those who actually use it in manufacturing integrated circuits do not have a fairly good front-end contact. Those used still have relatively high resistance to this substrate. In the published international patent application WO 97/35344 relative to the U.S. patent application 0 8/82 1,8 8 0, the inventors Tomas Jarstad and Hans Norstrom have mentioned 丨 Semiconductor device shielded by an array of electrically conductive pins and a method to manufacture such a device ", a shield of a semiconductor element, or a conductor path on a semiconductor substrate, is disclosed, which shield includes separate substrate contacts arranged in a pattern and surrounds the element or

O: \ 69 \ 69200-911016.ptc Page 7 518619 __Case No. 90103022_Year Month Day Amendment_ V. Description of the invention (4) Each path has a relatively small cross-sectional area, and looks like Square cross section. In addition, in the published Japanese patent application 11-145386, it is disclosed an inductor having a groove extending parallel to the electrical conductor path of the inductor and located in an adjacent portion of the spiral conductor path . In U.S. Patent 5,742,091 to Francois Hebert, an inductor structure having a spiral metal conductor is disclosed. At the same time, a second continuous spiral groove can also be located directly in the space between the first grooves, that is, it can also be located between adjacent portions of the spiral conductor. In another specific embodiment, the groove has a mesh-shaped rectangular pattern, which is located under all the areas occupied by the conductor, and can be regarded as comprising two groups of intersecting groove sections. The combination is parallel to each other. In U.S. Patent No. 5,717,243, an inductor structure having a spiral metal conductor is disclosed, in which radial grooves are arranged in the spiral path. In the published international patent application WO 97/45873 corresponding to the U.S. patent application 08 / 865,130, the inventors Ted Johansson and Hans

Norstrom in "Conductors for integrated circuits" discloses an inductor structure having a spiral metal conductor, in which a groove of a mesh pattern is located under an area occupied by the metal conductor. The pattern may be a rectangular pattern including two groups of intersecting grooves, and the grooves in each group are parallel to each other. SUMMARY OF THE INVENTION An object of the present invention is to provide an inductor structure of an integrated circuit having improved electrical shielding. Another object of the present invention is to provide a product having an improved Q-value.

O: \ 69 \ 69200-911016.ptc Page 8 518619 _Case No. 90103022_year month_jii_ V. Description of the invention (5) An inductor in the body circuit. The problem to be solved by the present invention is generally how to improve the Q-value of an inductor included in an integrated circuit. In particular, how to shield the parasitic capacitance obtained by the substrate without reducing the inductance of such an inductor. Therefore, in general, a shielded inductor includes an electrical conductor set in an appropriate manner, such as a spiral pattern, and a large array of trenches formed in a pattern below the electrical conductor. The island between the openings of the trench contains the substrate and an epitaxial structure formed on a substrate. The substrate is well conductive and has a weaker or poorer doped layer thereon. A trench extending from the surface down to the stack has a doping of P + or η +. In these islands, the substrate contacts are configured to connect to the conductive area and cover the upper surface of the island, providing a separate conductive area for each substrate contact. The conductive areas are thus laterally spaced from each other, and they can cover the surface of all islands, preferably also extending over some of the adjacent trenches, and over their small border areas. The drawings briefly illustrate the present invention through non-limiting specific embodiments and in conjunction with the attached drawings, wherein: FIG. 1 a is a perspective view of a patterned ground shield according to the prior art, FIG. lb shows a top view of a rectangular spiral inductor with the patterned ground shield placed on FIG. 1a according to the prior art. FIG. 2a shows a structural cross-section of a part of an integrated circuit Diagram showing a surface structure containing an inductor path with a shield in another way,

O: \ 69 \ 69200-911016.ptc Page 9 518619 _Case No. 90103022_Year Month and Revise_ V. Description of the invention (6) Figure 2b shows a structure above the shielded part in Figure 2a Fig. 2c shows the structure of an inductor placed on the surface structure of Figs. 2a and 2b. Fig. 3 shows the structure of an inductor under an integrated circuit used in the prior art. A top view of a trench pattern. Fig. 4a is a structural cross-sectional view of a part of an integrated circuit, which shows a surface structure of an inductor path with a shield structure. Fig. 4b shows a diagram The architecture diagram above the shielded part in 4a, and FIG. 5 is an architecture diagram above an inductor path surrounded by an architecture. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 shows a partial top view of a substrate, in which a large array of trenches 1 is etched to form some suitable patterns. The trench pattern is used under a shielded inductor to reduce the loss of the inductor to the substrate, such as the US patent cited by Hebert and the international patent application WO 9 7/4 58 7 cited therein. 3. The illustrated pattern includes a plurality of straight identical grooves of the first group, which are parallel to each other and have the same interval, and also a second group of identical grooves, which are also parallel to each other and the same interval. The grooves of the two groups are perpendicular to those of the first group. In any selected pattern, the trench must be long enough and its location must pass through the outermost periphery of the inductor and into the material of the substrate surrounding the inductor. The groove pattern used may have any mesh shape, which includes connected short groove sections, which are separated from each other by relatively small islands. The island therefore has any suitably preferred convex shape, such as triangular, square, rectangular, diamond, hexagonal, octagonal, circular, etc. The groove is usually extended

O: \ 69 \ 69200-911016.ptc Page 10 518619 Case No. 90103022 Amended 5. Description of the invention (7) Extends deep and becomes a continuous recess extending from some surface layers of the structure down to the substrate Or groove. The islands 5 between the trenches are the remaining part of a substrate or substrate layer 7 and some hierarchical structures formed on the substrate. Please refer to the cross-sectional architecture diagram of FIG. 2a. The substrate 7 has a doped form of p + or n +, so it has fairly good conductivity, and as shown in this specific embodiment, a well layer 9 with a doped form of P- or η- is disposed thereon. The trench 1 extends from the surface of the p- or η-well layer 9 down to the substrate, or a plate or substrate layer 7 having a conductivity of the doped form P + or η +. The doping form of the substrate 7 and the well layers in the specific embodiment shown in FIG. 2 a are equal, that is, they are P-type or η-type, but they can also be different, that is, the The substrate may be a p-type and a well layer n-, or the substrate may be a n-type or a well layer p-type. In each island 5, a substrate contact or contact pin 1 1 is left between the trenches 1 from a suitably filled conductive material, such as using W metal, for example, cited from the international patent application WO 9 7 / 3 5 3 44 revealed form. These contact pins 11 can be connected to the conductive area 13 above each of the remaining islands 5 and extend into the substrate layer 7 as well as to their electrical connectables and can be connected to some constant potential, For example, a ground potential to shield the substrate from the electric field generated by the current flowing in the conductive path of the inductor. Therefore, only the electric field can be blocked, which can have a small effect on the inductor by the parasitic capacitance. The magnetic field is not blocked. For the entire shield without holes, this magnetic field can be blocked, whereby the inductance and Q-value of the inductor under consideration can be reduced. The substrate contact 1 1 generally has the shape of a narrow pin or rod, which is formed in an occlusion hole extending deep into the well layer 9 in the substrate layer 7. The pin or rod may suitably have a positive

O: \ 69 \ 69200-911016.ptc Page 11 518619 _Case No. 90103022_ ± V. Description of the invention (8) Month Revision Square cross section. The conductive region 1 3 is formed as an independent island in the remaining seconds in the mother island 5 and extends upward to the edge of the trench 1, which forms the boundary of the individual island, which also preferably extends some A short distance passes through these boundaries' and thus has a narrow edge strip located above the trench 1. The conductive region 1 3 passes through the substrate contact 11 and the substrate 7 is electrically connected to a ground potential. It does not have direct contact with any other conductive regions' as shown in Figure 2b. Thereby, the full current induced in the conductive region 13 can be reduced. The conductive region 13 may be a patterned first metal main layer M1 remaining in the structure or on the surface thereof. The first metal layer is formed on a passivation layer 13 ′, which is directly and sequentially Is above the well layer 9 and the trench 1. In the structure shown in Fig. 2b, it causes a top metal layer M 1 to have another pure state layer 1 4 'such as a monoxide layer. Additional patterned metal main layers M2, M3, ... can be provided on top of the passive layer 14. The other main metal layer can then be patterned and it can be separated by an electrically insulating layer, such as a silicon oxide layer. In these stacks, the spiral conductor path of an inductor is made using another metal layer well known in the art, see for example the cited international patent application. Therefore, a conductive path 15 may be formed in a lower metal layer like M3, and the inductor path 17 may be formed in a metal layer M4 immediately above it, see also FIG. 2C. The final structure viewed from above is shown. In this figure, the region 19 shown is located under all the inductor paths and can be completely filled in a trench array and substrate contacts, which can be referred to in Figures 2a and 2b.

O: \ 69 \ 69200-911016.ptc Page 12 518619 Cable No. 90103022 Amendment V. Description of the Invention (9) The entire inductor structure can be surrounded by a structure 21, which is composed of the same metal as the conductive area 13 The area of the layer is shown in FIG. 2b and FIG. 5. The metal frame 21 is electrically connected to a bottom frame-type contact pin 2 3 of the column frame ′, which is manufactured in the same manner as the substrate contact 丨 丨 and passes through the substrate 7. The metal frame 21 is a continuous strip, which has a notch or opening 25 to make it an open structure to avoid current flow. A typical value is that the width of the trench is, the island has a size of 3.5 \ 3.5 # 1112 'and the conductive region is 3.7 乂 3.7 # 1112. The above design includes that it is an insulated conductive region, which can reduce the loss from the substrate. Therefore, it can improve the Q_ value of the inductor. Furthermore, it usually does not require additional processing steps to provide the substrate contacts, and is based on published international patent application PCT / SE9 7/0 04 8 7 relative to US Patent Application 08/82 1,880. Revealed to use. In order to further enhance the effect that it is a highly conductive and grounded substrate 7, if necessary, can an additional one be used? The doped form of + or ^ extends from the surface of the well layer 9 into the stack some distance, as shown by the area 27 in Fig. 2 & These additional doped regions can be obtained by ion implantation or they can be in the same doped form as the well layer 9. Together with the substrate contact pins 11, it can be used as a surface-to-substrate contact. In order to further improve the shielding of the substrate, according to the paper by CPYue et al. And in the international patent application WO98 / 50956 cited above, an additional conductive region 29 'has a patterned layer having a conductive layer substantially similar to the aforementioned conductive region The position 13 is reversed 'and has some overlap, which can be placed above or below the conductive area 13' as shown in the cross-sectional architecture diagram of Fig. 4a and the view above Fig. 4b. The region 29 may be formed on a second metal main layer m2

O: \ 69 \ 69200-911016.ptc Page 13 518619 _Case No. 90103022_ Year, Month, and Revise Slightly wider or narrower than the groove. These areas of the additional conductive patterned layer can be basically connected to a ground potential. The main steps of the method of manufacturing the structure shown in Figs. 2a-2c will be briefly explained as follows. First, some substrates or substrate layers 7 having a good electrical conductivity are provided and therefore doped with P + or n + as shown in the figure. The well layer 9 is then added to the upper layer of the substrate, for example by epitaxial growth. It is moderately doped to have a relatively low conductivity, which is the doped form p-shown in the example, but it can also be doped to η-the same. Therefore, the deep and narrow recesses or cavities of the trench can first be created by applying a shield, and then the recesses are made by dry etching to extend to the surface of the substrate layer 7. The shielding layer is removed, and the recess is refilled with an electrically insulating material, such as silicon oxide, or an undoped polycrystalline silicon or other dielectric material, and any material having contact with the substrate layer 7 and Any material such as a low conductivity of the well layer 9 may be used. The sufficiently narrow trench surface produced during this refilling process will be approximately flat. The trench 1 thus produced may have a width of about 1-2 // m and a depth of about 5-2 0 # m. The surface structure and the width of the substrate material between adjacent trenches can be as small as practically possible, for example in the range of 2-4 / zm. If needed, an additional doping can be used to create the region 27, see Figure 2a, which is to improve the shielding effect and contains an additional implanted dopant in the form of a dopant, such as the well layer 9, which can be here Fabricated in stages, it uses a patterned photomask to implant only the area within the inductor structure to be formed.

O: \ 69 \ 69200-911016.ptc Page 14 518619 Case No. 90103022 Λ_η Revision V. Description of Invention (11) On the surface of the wafer, about 1 / zm of insulating material is deposited, which is preferably for The oxide stone can also be roughly planarized by a conventional method, so as to form the passivation layer 13 '. Then, a deep hole shielding layer is applied to the surface of the substantially flat insulating material, and then patterned. The shielding window and deep hole to be generated will have a size corresponding to the width of the trench, that is, it may have a width and a diameter in the range of 1-2 / zm. The deep hole is created by dry etching, and the shielding layer is removed. The depth given by the deep hole in the etching process is greater than the height of the passive layer 1 3 'and the well layer 9 so as to reach down to the substrate 7 which is highly doped. Therefore, the conventional contact holes are not shown in the figure and can be lowered to any active or passive device. Not shown in the figure, they need to be made into electrical contacts. Generally, they are applied to one of all contact holes. Layer, not shown in the figure, for example, it contains Ti, P t, Co, which is not attached to the upper insulating material of the passive layer 1 3 ′. Finally, the hole is filled with tungsten deposited by CVD, but other materials can also be used. Metal to form the substrate contact 11 and other contact plugs to fill the metal, the π plug π has the same size or diameter during the deposition process, the deep hole will be completely if the thickness of the deposition is related to the Laterally, other conductive layers, such as containing aluminum, can be deposited on all wafer surfaces. After patterning and etching through two conductive layers using a conventional method, the patterned W and A1 stack can be used as the first metal main layer M1. Then another passivation layer 14 is applied, a hole is etched in this layer, and an additional metal layer is applied on top of this insulating layer. This additional metal layer (layer M3 of Fig. 2a) is patterned to contain the conductive path 15 for connection to the internal endpoint of the inductor path. A further insulating oxide layer

O: \ 69 \ 69200-911016.ptc Page 15 518619 _Case No. 90103022_ Year Month Day__ V. Description of the invention (12) Next, the hole is created, and a third metal layer is applied on it. (Layer M4 of FIG. 2a), which is patterned to form the inductor path 17. The thickness of each main metal layer is basically in the range of 1-2 / zm. The width of the conductor road control that forms the conductor is about 5 / z m ′, the distance between adjacent parts of the path, which is the same as the width of the path. The upper metal layer may be generated by depositing a suitable metal material, and may also fill holes in the oxide layer to form a conductor electrically connected to the bottom metal layer. After deposition, the metal layer is etched using conventional methods to form the required conductor. The additional patterned metal layer (e.g., M2 of Fig. 4a) can be formed by conventional methods if necessary, such as those similar to those described for the upper metal layer.

O: \ 69 \ 69200-911016.ptc Page 16 518619 _Case No. 90103022_Year Month Day_Modified Illustration Brief Description of Schematic Element Symbol Description I Trench 5 Island 7 Substrate or Substrate Layer 9 Lightly Doped Well Layer II Substrate contacts or contact pins 13 Conductive area 13 'Passive layer 14 Passive layer 15 Conductive path 17 Inductor path 1 9 Region 2 1 Architecture 2 3 Contact pin 25 Notch or opening 2 7 Region 29 Conductive region

Ml, M2, M3, M4 metal main layer

O: \ 69 \ 69200-911016.ptc Page 17

Claims (1)

518619 _ Case No. 90103022 7 丨 year. Month A said to amend $ _ 6. Scope of patent application 1. A integrated circuit including an inductor, the inductor includes a metal conductor formed in a surface structure, the surface structure is located in a surface that is well conductive The substrate, especially on a doped substrate and a trench in the surface structure, extends downward into the substrate, is located below the metal conductor, and is filled with an electrically insulating material The groove is arranged in a mesh or grid pattern to form the surface structure and the island of the substrate material between the pattern grids between adjacent portions of the groove, and is characterized in that the substrate is connected to the substrate. The points are formed within the independent island in the grid. The substrate contacts are made of a conductive material and extend down to the substrate in the substrate structure. 2. The integrated circuit according to item 1 of the scope of patent application, characterized in that it covers the conductive area of the island, and the conductive area is connected to the individual independent substrate contacts and is electrically insulated from each other. 3. The integrated circuit of item 2 in the scope of patent application, characterized in that the conductive area is extended to cover a relatively narrow boundary portion of the adjacent trench. 4. The integrated circuit according to item 2 of the scope of patent application, characterized in that the conductive area is electrically insulated from the metal conductor by an electrical insulation layer applied to the first conductive area. 5. The integrated circuit of item 1 in the scope of patent application, characterized in that in the independent island, the material has a doping on its surface, so that the surface can conduct electricity well. 6. The integrated circuit of item 2 of the patent application, characterized in that the second conductive region covers the trench. 7 · The integrated circuit of item 6 in the scope of patent application, characterized in that O: \ 69 \ 69200-911016.ptc Page 18 518619 _Case No. 90103022_Year Month Amendment_ VI. Patent Application Scope The second conductive region has the same architectural pattern as the trench. 8. The integrated circuit according to item 6 of the scope of patent application, characterized in that the second conductive region is a region of a metallization layer, which is located on a plane above or below the conductive region. 9. The integrated circuit of item 1 in the scope of patent application, characterized in that a metal structure surrounds the metal conductor of the inductor. 10. The integrated circuit according to item 9 of the scope of patent application, characterized in that the metal structure is a structure electrically connected to a substrate contact located under the metal structure. 1 1. The integrated circuit of item 9 in the scope of patent application, characterized in that the metal structure is a continuous strip having at least one groove. 1 2. The integrated circuit according to item 2 of the scope of patent application, characterized by a metal structure, which surrounds the metal conductor of the inductor, and is made in a metal layer, and the conductive region is formed by the metal layer. Make up. O: \ 69 \ 69200-911016.ptc Page 19