TW518619B - Integrated circuit - Google Patents
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- TW518619B TW518619B TW090103022A TW90103022A TW518619B TW 518619 B TW518619 B TW 518619B TW 090103022 A TW090103022 A TW 090103022A TW 90103022 A TW90103022 A TW 90103022A TW 518619 B TW518619 B TW 518619B
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- 239000000758 substrate Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims description 26
- 238000001465 metallisation Methods 0.000 claims description 5
- 239000012777 electrically insulating material Substances 0.000 claims description 2
- 238000010292 electrical insulation Methods 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 76
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
518619 _案號90103022_年月曰 修正_ 五、發明說明(1) 技術範疇 本發明係關於一積體電路的屏蔽式電感器,及具有一屏 蔽式電感器的積體電路。 發明背景 矽二極體,CMOS及BiCMOS積體電路目前皆使用在頻率範 圍1-3 GHz的高速應用中,其取代了先前僅能用在使用該 週期表的第I I I及V族的材料。電感器元件時常為高頻電路 構建區塊中所需要,例如共振器及濾波器。對於所有積體 電路的共同問題是如何使得電感器具有足夠高的品質因子 或Q值,以及足夠高的運作頻率,其明顯地是受到該共振 頻率的限制。 目前對於生產積體電路的矽製程的進展,已經允許電感 器佈置在每單位面積中具有一較高的電感值,並由於降低 特徵尺寸而具有較小的損耗,而多層次金屬化結構包含厚 的氧化物,可以協助該電感器與基板的絕緣。但是,由於 該金屬化層的電阻,與該基板的電氣耦合,以及基板内的 損耗,其仍會有相當的損耗。因此,其很難得到在2- 1 0 nH範圍的電感器元件,其在當以石夕材料來製造電子積體電 路時,可在1-2 GHz頻率範圍中具有高於10的Q -值。 集成電感器通常的線路配置包含有正方形或八角形的長 條,但設定為螺旋狀。因為矽基板的導電特性,該Q-值會 降低。藉由選擇性地移除位在形成該電感器的導體之下的 矽,即可得到較高的Q -值及較高的自我共振頻率。因此, 該Q -值可以因為這樣的移除而增加兩個係數,例如由J. Y. -C. Chang, Α·Α· Abidi, M.Gaitan 等人所提出’'Large518619 _Case No. 90103022_ Year Month Amendment _ V. Description of the invention (1) Technical scope The present invention relates to a shielded inductor with an integrated circuit and an integrated circuit with a shielded inductor. BACKGROUND OF THE INVENTION Silicon diodes, CMOS and BiCMOS integrated circuits are currently used in high-speed applications in the frequency range of 1-3 GHz, which has replaced materials that could only previously be used in Group I I I and V of the periodic table. Inductor components are often required in high-frequency circuit building blocks, such as resonators and filters. The common problem for all integrated circuits is how to make the inductor have a sufficiently high quality factor or Q value, and a sufficiently high operating frequency, which is obviously limited by this resonance frequency. At present, the progress of the silicon process for the production of integrated circuits has allowed inductors to be arranged with a higher inductance value per unit area, and has lower losses due to reduced feature sizes, while multi-level metallization structures contain thick The oxide can assist the insulation of the inductor from the substrate. However, due to the electrical resistance of the metallization layer, electrical coupling with the substrate, and losses in the substrate, there will still be considerable losses. Therefore, it is difficult to obtain an inductor element in the range of 2 to 10 nH, which can have a Q-value higher than 10 in the frequency range of 1-2 GHz when an electronic integrated circuit is manufactured from a shixi material. . The integrated inductor usually has a square or octagonal strip configuration, but is set to a spiral shape. This Q-value decreases due to the conductive properties of the silicon substrate. By selectively removing the silicon located below the conductor forming the inductor, a higher Q-value and a higher self-resonant frequency can be obtained. Therefore, the Q-value can be increased by two coefficients due to such removal, for example, proposed by J. Y. -C. Chang, Α · Α · Abidi, M. Gaitan et al.
0:\69\69200-911016.ptc 第5頁 518619 _案號90103022_年月日 倐正_ 五、發明說明(2)0: \ 69 \ 69200-911016.ptc Page 5 518619 _Case No. 90103022_Year Month and Date 倐 正 _ V. Description of the invention (2)
Suspended Inductor on Silicon and Their Use in a 2 βm CMOS RF Amplifier” ,Trans. El. Dev. , Vo 1. 14, Ν〇·5, p.246, 1993年5月,及Abidi等人所提美國專利 5,539,241。該項移除可以措由钱刻該碎層來產生數百 的空氣間隙,但這種方法對大量生產並不實用,或能與用 於製造在石夕層上積體電路的一般製程相容。 在 C.P. Yue,S.S. Wong 所提,n0n-Chip Spiral Inductors with Patterned Ground Shields for Si- Based RF 1C’ s,f,J· So lid- State Circuits, Vol. 33, No. 5, p. 743, 1 9 9 8 年5 月,即發明人 C.P. Yue 及 S.S.Suspended Inductor on Silicon and Their Use in a 2 βm CMOS RF Amplifier ”, Trans. El. Dev., Vo 1. 14, No. 5, p. 246, May 1993, and U.S. Patent by Abidi et al. 5,539,241. This removal can be used to cut the broken layer to create hundreds of air gaps, but this method is not practical for mass production, or can be used to manufacture the stacked body on the stone layer The general process of the circuit is compatible. In CP Yue, SS Wong, n0n-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF 1C's, f, J. So lid-State Circuits, Vol. 33, No. 5, p. 743, May 1998, inventors CP Yue and SS
Wong所提已立案的國際專利申請提案WO 98/50956,其中 揭示了一種圖案化的接地屏蔽層,其位於該電感器之下, 及該半導體基板之上。此設計由於對於基板中感應電流的 屏蔽效應及降低了接地屏蔽中所感應的渦電流,且由於該 接地屏蔽係經過圖案化,依此方式,該電流並不能在該電 感器之下的金屬中流通,參考此提案的圖la, lb。 在Burghartz 等人所提,’'Progress in RF Inductors on Silicon -Understanding MMIC Inductors 丨丨,IEDM Tech· Digest, 1998, pp. 523-526 中,其比較了 降低基 板損耗的幾種不同的方法,這些結構係引用C. P. Yue等人 的論文,以及引用Y u e等人所提的專利申請提案。 對於將電感器集積在矽結構上的研究仍在進行中。其報 告結果呈現彼此矛盾的現象。其損耗的正確機制,及以同 等電路最佳化的結構模型,能夠以一物理上,但不會太過 簡化的方式之描述,仍待討論中。一具有良好特性的電感Wong's filed international patent application proposal WO 98/50956 discloses a patterned ground shield layer under the inductor and above the semiconductor substrate. This design is due to the shielding effect on the induced current in the substrate and reduces the eddy current induced in the ground shield, and because the ground shield is patterned, in this way, the current cannot be in the metal under the inductor Circulation, refer to Figure la, lb of this proposal. In Burghartz et al., "Progress in RF Inductors on Silicon-Understanding MMIC Inductors," IEDM Tech. Digest, 1998, pp. 523-526, compares several different methods to reduce substrate loss. These The structure refers to a paper by CP Yue et al. And a patent application proposal by Yue et al. Research into integrating inductors on silicon structures is still ongoing. The results of their reports present contradictory phenomena. The correct mechanism of its loss, and the structural model optimized by the equivalent circuit, can be described in a physical, but not too simplified way, which remains to be discussed. An inductor with good characteristics
O:\69\69200-911016.ptc 第6頁 518619 ----_案號卯切汕敗_年月 g___ 五、發明說明(3) 器結構,當使用在一應用電路中時,有時候即無法像是用 在其它不同電路時一般具有良好的特性,例如該電感器結 構的電氣行為係依據實際的電路,或更特定而言係依據實 際上所環繞的結構。因此,僅根據理論上的探討或計算, 是报難決定出一電感器的最佳化結構。 在c· P· Yue等人所提出的論文及相關的專利中,其可改 善電感器的效能。但是,該金屬化圖案必須為連續的,且 必須在一些點上連接到一固定的電位,較佳地是連接在數 個點上,使得其可運作良好,像是一個屏蔽。但是,其未 提出方法來在金属化圖案之下改善該基板的效應。同時, 該圖案具有朝向該基板的開口,其中電磁場可以穿過。根 據我們的實驗及引用自Burghar tz等人的論文,將該基板 接地靠近於構成電感器的電氣導體,可以改善q值,因為 具有一良好定義的電位的高度導電基板,例如該接地電 位’也可做為一屏蔽,並降低矽當中的渦電流效應。但 是’在製程中實際用來製造積體電路者,其沒有相當好的 前端接觸。那些所使用的仍然具有與·該基板間相當高的電 阻。 在相對於美國專利申請0 8/ 82 1,8 8 0的已公開國際專利申 睛WO 97/35344 中,發明者Tomas Jarstad 及Hans Norstrom 戶斤提丨丨 Semiconductor device shielded by an array of electrically conductive pins and a method to manufacture such a device” 當中,揭示了一種半導 體元件的屏蔽,或在一半導體基板上的導體路徑,該屏蔽 包含配置在一圖案中的分開的基板接點,並環繞該元件或O: \ 69 \ 69200-911016.ptc Page 6 518619 ----_ Case No. 卯 切 山 失 _ 年月 g___ V. Description of the invention (3) Device structure, when used in an application circuit, sometimes That is, it cannot have good characteristics when used in other different circuits. For example, the electrical behavior of the inductor structure is based on the actual circuit, or more specifically, the structure that is actually surrounded. Therefore, it is difficult to determine the optimal structure of an inductor based on theoretical discussion or calculation. In the paper and related patents proposed by c. P. Yue et al., It can improve the performance of inductors. However, the metallization pattern must be continuous and must be connected to a fixed potential at some points, preferably several points, so that it can function well, like a shield. However, it does not propose a method to improve the effect of the substrate under the metallization pattern. At the same time, the pattern has an opening towards the substrate, in which an electromagnetic field can pass. According to our experiments and papers cited by Burghartz et al., Grounding the substrate close to the electrical conductors that make up the inductor can improve the value of q because highly conductive substrates with a well-defined potential, such as Can be used as a shield and reduce eddy current effects in silicon. However, those who actually use it in manufacturing integrated circuits do not have a fairly good front-end contact. Those used still have relatively high resistance to this substrate. In the published international patent application WO 97/35344 relative to the U.S. patent application 0 8/82 1,8 8 0, the inventors Tomas Jarstad and Hans Norstrom have mentioned 丨 Semiconductor device shielded by an array of electrically conductive pins and a method to manufacture such a device ", a shield of a semiconductor element, or a conductor path on a semiconductor substrate, is disclosed, which shield includes separate substrate contacts arranged in a pattern and surrounds the element or
O:\69\69200-911016.ptc 第7頁 518619 __案號90103022_年月日 修正_ 五、發明說明(4) 路徑,每個接點皆具有相當小的橫截面面積,以及像是正 方形的橫截面。 另外,在已公開的日本專利申請11-145386中,其揭示 一種電感器,其具有一溝槽,平行延伸於該電感器的電氣 導體路徑,並位在該螺旋導體路徑的相鄰部份中。在 Francois Hebert的美國專利5,742, 091當中,揭示了一種 具有螺旋金屬導體的電感器結構。同時,一第二連續螺旋 溝槽也可直接地位在該第一溝槽之間的空隙中,也就是也 可位在該螺旋導體的相鄰部份之間。在另一具體實施例 中,該溝槽具有一網狀的長方形圖案,位在所有由該導體 佔據的區域之下,並可視為包含兩組相交的溝槽區段,這 些區段在每個組合中為彼此平行。在美國專利5, 717, 243 中,揭示一具有一螺旋金屬導體的電感器結構,其中配置 有在該螺旋路徑下的放射狀溝槽。 在對應於美國專利申請〇 8 / 8 6 5,1 3 0的已公開國際專利申 請W0 97/45873 中,由發明者Ted Johansson 及HansO: \ 69 \ 69200-911016.ptc Page 7 518619 __Case No. 90103022_Year Month Day Amendment_ V. Description of the invention (4) Each path has a relatively small cross-sectional area, and looks like Square cross section. In addition, in the published Japanese patent application 11-145386, it is disclosed an inductor having a groove extending parallel to the electrical conductor path of the inductor and located in an adjacent portion of the spiral conductor path . In U.S. Patent 5,742,091 to Francois Hebert, an inductor structure having a spiral metal conductor is disclosed. At the same time, a second continuous spiral groove can also be located directly in the space between the first grooves, that is, it can also be located between adjacent portions of the spiral conductor. In another specific embodiment, the groove has a mesh-shaped rectangular pattern, which is located under all the areas occupied by the conductor, and can be regarded as comprising two groups of intersecting groove sections. The combination is parallel to each other. In U.S. Patent No. 5,717,243, an inductor structure having a spiral metal conductor is disclosed, in which radial grooves are arranged in the spiral path. In the published international patent application WO 97/45873 corresponding to the U.S. patent application 08 / 865,130, the inventors Ted Johansson and Hans
Norstrom 在"Conductors for integrated circuits"中揭 示一種具有一螺旋金屬導體的電感器結構,其中一網狀圖 案的溝槽係位在由該金屬導體所佔據的區域之下。該圖案 可以為包含兩組相交溝槽的一長方形圖案,在每組中的溝 槽係彼此平行。 發明概述 本發明的一個目的在於提供一具有改良的電氣屏蔽的積 體電路之電感器結構。 本發明的另一個目的在於提供在一具有一改善Q -值的積Norstrom in "Conductors for integrated circuits" discloses an inductor structure having a spiral metal conductor, in which a groove of a mesh pattern is located under an area occupied by the metal conductor. The pattern may be a rectangular pattern including two groups of intersecting grooves, and the grooves in each group are parallel to each other. SUMMARY OF THE INVENTION An object of the present invention is to provide an inductor structure of an integrated circuit having improved electrical shielding. Another object of the present invention is to provide a product having an improved Q-value.
O:\69\69200-911016.ptc 第8頁 518619 _案號90103022_年月日_jii_ 五、發明說明(5) 體電路中的一電感器。 本發明所要解決的問題一般而言為如何改善包含在一積 體電路中的一電感器的Q-值。特別是,要如何屏蔽由該基 板所得到的該寄生電容,而不會降低這種電感器的電感。 因此一般而言,一屏蔽式電感器包含設定為一適當方式 的電氣導體,例如為一螺旋圖案,以及一大的溝槽陣列, 其係形成在該電氣導體之下的圖案中。在該溝槽的開口之 間的島則包含該基板及形成在一基板之上的磊晶結構。該 基板係為良好導電,並在其上具有較弱或較差的摻雜層。 由該表面延伸向下到該疊層的溝槽,具有一摻雜為P +或 η +。在這些島中,基板接點係配置成連接到導電區域,並 覆蓋的島的上表面,對於每個基板接點提供了一個別的導 電區域。該導電區域因此係橫向地彼此隔開,而其可以大 致地覆蓋所有的島的表面,較佳地是也延伸一些到該相鄰 的溝槽之上,並在其小的邊界區域上。 圖式簡單說明 本發明將藉由非受限性的具體實施例,並配合所附圖面 來加以說明,其中: 圖1 a所示為根據先前技藝的一圖案化接地屏蔽的透視 圖, 圖lb所示為根據先前技藝中,在圖la的放置上該圖案化 的接地屏蔽的一長方形螺旋電感器的上視圖, 圖2 a所示為一積體電路的一部份之架構性橫截面圖,其 顯示出以另外一種方式包含具有一屏蔽的電感器路徑的一 表面結構,O: \ 69 \ 69200-911016.ptc Page 8 518619 _Case No. 90103022_year month_jii_ V. Description of the invention (5) An inductor in the body circuit. The problem to be solved by the present invention is generally how to improve the Q-value of an inductor included in an integrated circuit. In particular, how to shield the parasitic capacitance obtained by the substrate without reducing the inductance of such an inductor. Therefore, in general, a shielded inductor includes an electrical conductor set in an appropriate manner, such as a spiral pattern, and a large array of trenches formed in a pattern below the electrical conductor. The island between the openings of the trench contains the substrate and an epitaxial structure formed on a substrate. The substrate is well conductive and has a weaker or poorer doped layer thereon. A trench extending from the surface down to the stack has a doping of P + or η +. In these islands, the substrate contacts are configured to connect to the conductive area and cover the upper surface of the island, providing a separate conductive area for each substrate contact. The conductive areas are thus laterally spaced from each other, and they can cover the surface of all islands, preferably also extending over some of the adjacent trenches, and over their small border areas. The drawings briefly illustrate the present invention through non-limiting specific embodiments and in conjunction with the attached drawings, wherein: FIG. 1 a is a perspective view of a patterned ground shield according to the prior art, FIG. lb shows a top view of a rectangular spiral inductor with the patterned ground shield placed on FIG. 1a according to the prior art. FIG. 2a shows a structural cross-section of a part of an integrated circuit Diagram showing a surface structure containing an inductor path with a shield in another way,
O:\69\69200-911016.ptc 第9頁 518619 _案號90103022_年月曰 修正_ 五、發明說明(6) 圖2b所示為圖2a中來自該屏蔽的部份之上的一架構圖, 圖2c所示為放置在圖2a及2b的該表面結構之上的一電感器 的架構圖, 圖3所示為根據先前技藝’所使用在一積體電路的一電 感器之下的一溝槽圖案的上視圖, 圖4a所示為一積體電路的一部份之架構性橫截面圖,其 顯示出具有一屏蔽結構的電感器路徑的一表面結構, 圖4b所示為圖4a中的該屏蔽的部份之上的架構圖,及 _圖5所示為由一架構包圍的一電感器路徑之上的架構 圖。 較佳具體實施例的說明 圖3所示為一基板的一部份之上視圖,其中一大的溝槽 陣列1係被蝕刻還形成一些適當的圖案。該溝槽圖案係使 用在一屏蔽式電感器之下,用以降低該電感器的損耗到該 基板,如其所引用之Hebert的U. S.專利,其所引用的國際 專利申請WO 9 7 /4 58 7 3。該所示的圖案包含第一組的數個 直線的同樣溝槽,其彼此平行,並具有一相同的間隔,也 有一第二組同樣的溝槽,其也彼此平行及相同的間隔,該 第二組的溝槽係垂直於第一組的那些溝槽。在任何選定的 圖案中,該溝槽必須足夠長,且其位置必須穿過該電感器 的最外圍,而進到包圍該電感器的該基板之材料。所使用 的溝槽圖案可以具有任何的網狀形狀,其包含相連接的短 溝槽區段,其區隔出相當小的島而彼此相隔開。該島因此 具有任何適當較佳的凸出形狀,例如三角形,正方形,長 方形,菱形,六角形,八角形,圓形等。該溝槽通常為延O: \ 69 \ 69200-911016.ptc Page 9 518619 _Case No. 90103022_Year Month and Revise_ V. Description of the invention (6) Figure 2b shows a structure above the shielded part in Figure 2a Fig. 2c shows the structure of an inductor placed on the surface structure of Figs. 2a and 2b. Fig. 3 shows the structure of an inductor under an integrated circuit used in the prior art. A top view of a trench pattern. Fig. 4a is a structural cross-sectional view of a part of an integrated circuit, which shows a surface structure of an inductor path with a shield structure. Fig. 4b shows a diagram The architecture diagram above the shielded part in 4a, and FIG. 5 is an architecture diagram above an inductor path surrounded by an architecture. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 3 shows a partial top view of a substrate, in which a large array of trenches 1 is etched to form some suitable patterns. The trench pattern is used under a shielded inductor to reduce the loss of the inductor to the substrate, such as the US patent cited by Hebert and the international patent application WO 9 7/4 58 7 cited therein. 3. The illustrated pattern includes a plurality of straight identical grooves of the first group, which are parallel to each other and have the same interval, and also a second group of identical grooves, which are also parallel to each other and the same interval. The grooves of the two groups are perpendicular to those of the first group. In any selected pattern, the trench must be long enough and its location must pass through the outermost periphery of the inductor and into the material of the substrate surrounding the inductor. The groove pattern used may have any mesh shape, which includes connected short groove sections, which are separated from each other by relatively small islands. The island therefore has any suitably preferred convex shape, such as triangular, square, rectangular, diamond, hexagonal, octagonal, circular, etc. The groove is usually extended
O:\69\69200-911016.ptc 第10頁 518619 案號 90103022 年 月 修正 五、發明說明(7) 伸到很深,並成為由該結構的一些表面階層延伸向下到該 基板的連續凹處或凹槽。 在該溝槽之間的島5,其為一基板或基板層7的剩餘部 份,及一些形成在該基板之上的一些階層結構,請參考圖 2a的截面架構圖。該基板7具有摻雜形式p+或n+,因此其 具有相當良好的導電性,並且如該具體實施例所示,其上 配置有一摻雜形式為P-或η -的井層9。該溝槽1延伸自該p-或η-井層9的表面向下到該基板,或具有由該摻雜形式為 Ρ+或η+的導電性的羞板或基板層7.。該基板7的摻雜形式及 圖2 a中所示的具體實施例中的井層皆為相等,也就是說其 為P-型或η-型,但其也可為不同者,也就是該基板可以為 ρ-型及井層η -、型,或該基板可為η_型或井層ρ -型。 在每個島5中,該溝槽1之間留有一基板接點或接點針腳 1 1,其來自一適當地填充導電材料,例如像是使用W金 屬,例如引用自國際專利申請WO 9 7/ 3 5 3 44所揭示的形 式。這些接點針腳1 1可以連接到為在每個剩餘島5之上的 導電區域1 3,並延伸到該基板層7中,以及連接到其可電 氣連接者,並且可以連接到一些恆定電位,例如一接地電 位,藉此來屏蔽該基板與流動在該電感器的導電路徑中的 電流所產生的電場。因此,僅有該電場可被阻隔,其可由 該寄生電容產生對於該電感器的較小影響。該磁場則未被 阻隔。對於整個沒有空洞的屏蔽,該磁場可被阻隔,藉此 所考慮的電感器的電感及Q-值即可降低。基板接點1 1 一般 具有狹窄的針腳或桿的形狀,其係形成在延伸到基板層7 中井層9内深的閉塞孔中。該針腳或桿可適當地具有一正O: \ 69 \ 69200-911016.ptc Page 10 518619 Case No. 90103022 Amended 5. Description of the invention (7) Extends deep and becomes a continuous recess extending from some surface layers of the structure down to the substrate Or groove. The islands 5 between the trenches are the remaining part of a substrate or substrate layer 7 and some hierarchical structures formed on the substrate. Please refer to the cross-sectional architecture diagram of FIG. 2a. The substrate 7 has a doped form of p + or n +, so it has fairly good conductivity, and as shown in this specific embodiment, a well layer 9 with a doped form of P- or η- is disposed thereon. The trench 1 extends from the surface of the p- or η-well layer 9 down to the substrate, or a plate or substrate layer 7 having a conductivity of the doped form P + or η +. The doping form of the substrate 7 and the well layers in the specific embodiment shown in FIG. 2 a are equal, that is, they are P-type or η-type, but they can also be different, that is, the The substrate may be a p-type and a well layer n-, or the substrate may be a n-type or a well layer p-type. In each island 5, a substrate contact or contact pin 1 1 is left between the trenches 1 from a suitably filled conductive material, such as using W metal, for example, cited from the international patent application WO 9 7 / 3 5 3 44 revealed form. These contact pins 11 can be connected to the conductive area 13 above each of the remaining islands 5 and extend into the substrate layer 7 as well as to their electrical connectables and can be connected to some constant potential, For example, a ground potential to shield the substrate from the electric field generated by the current flowing in the conductive path of the inductor. Therefore, only the electric field can be blocked, which can have a small effect on the inductor by the parasitic capacitance. The magnetic field is not blocked. For the entire shield without holes, this magnetic field can be blocked, whereby the inductance and Q-value of the inductor under consideration can be reduced. The substrate contact 1 1 generally has the shape of a narrow pin or rod, which is formed in an occlusion hole extending deep into the well layer 9 in the substrate layer 7. The pin or rod may suitably have a positive
O:\69\69200-911016.ptc 第11頁 518619 _案號 90103022_± 五、發明說明(8) 月 曰 修正 方形的橫截面。 該導電區域1 3係形成在母個島5中剩餘的秒上形成為獨 立的島,並向上延伸到該溝槽1的邊緣,其形成該個別島 的邊界,其也較佳地是延伸一些短距離通過這些邊界’因 此具有位在該溝槽1之上的狹窄邊緣長條。該導電區域1 3 係穿過該基板接點1 1,而該基板7電氣式地連接到一接地 電位。其並不與任何其它導電區域有直接的接觸’如圖2b 中所示。藉此,即可降低在該導電區域1 3中所感應的滿電 流。 該導電區域13可以為一圖案化的第一金屬主要層Ml在該 結構中或其表面上的剩餘區域,此第一金屬層係形成在一 鈍態層13’之上,其依序直接地為在該井層9及該溝槽1之 上。在圖2 b中所示的結構上,其使得一頂部金屬層Μ 1具有 另一個純態層1 4 ’例如一氧化石夕層。另外的圖案化的金屬 主要層Μ 2, M3,...可以提供在該鈍態層1 4之上。然後該另 一個金屬主要層也可圖案化,而其可由電氣絕緣層所隔 開,例如氧化矽層。在這些疊層 中,一電感器的該螺旋導體路徑係使用在本技藝中所熟知 的另外的金屬層來製造,請參見像是所引用的國際專利申 請案。因此,一導電路徑1 5可形成於像是Μ 3之一較低的金 屬層中,並且該電感器路徑17可形成於緊接其上之金屬層 Μ 4中,也請參見圖2 C,所示為由上所視的最後結構。在此 圖中,所示之區域19,其係位在所有的該電感器路徑之 下,並可完全地填充於一溝槽陣列及基板接點,其可參考 圖2a及2b所述。O: \ 69 \ 69200-911016.ptc Page 11 518619 _Case No. 90103022_ ± V. Description of the invention (8) Month Revision Square cross section. The conductive region 1 3 is formed as an independent island in the remaining seconds in the mother island 5 and extends upward to the edge of the trench 1, which forms the boundary of the individual island, which also preferably extends some A short distance passes through these boundaries' and thus has a narrow edge strip located above the trench 1. The conductive region 1 3 passes through the substrate contact 11 and the substrate 7 is electrically connected to a ground potential. It does not have direct contact with any other conductive regions' as shown in Figure 2b. Thereby, the full current induced in the conductive region 13 can be reduced. The conductive region 13 may be a patterned first metal main layer M1 remaining in the structure or on the surface thereof. The first metal layer is formed on a passivation layer 13 ′, which is directly and sequentially Is above the well layer 9 and the trench 1. In the structure shown in Fig. 2b, it causes a top metal layer M 1 to have another pure state layer 1 4 'such as a monoxide layer. Additional patterned metal main layers M2, M3, ... can be provided on top of the passive layer 14. The other main metal layer can then be patterned and it can be separated by an electrically insulating layer, such as a silicon oxide layer. In these stacks, the spiral conductor path of an inductor is made using another metal layer well known in the art, see for example the cited international patent application. Therefore, a conductive path 15 may be formed in a lower metal layer like M3, and the inductor path 17 may be formed in a metal layer M4 immediately above it, see also FIG. 2C. The final structure viewed from above is shown. In this figure, the region 19 shown is located under all the inductor paths and can be completely filled in a trench array and substrate contacts, which can be referred to in Figures 2a and 2b.
O:\69\69200-911016.ptc 第12頁 518619 索號 90103022 曰 修正 五、發明說明(9) 整個電感器結構可由一架構2 1所包圍,其構成係由與如 同導電區域13的相同金屬層之區域,請參見圖2b及圖5。 該金屬架構2 1係電氣式地連接到一底層架構式的接點針腳 2 3的列架構’其係與該基板接點丨丨相同的方式製造,並穿 過該基板7。該金屬架構21為一連續的長條,其具有一缺 口或開口 2 5來使其成為一開放結構,以避免流經電流。 典型的數值為該溝槽的寬度為,該島具有尺寸為 3.5\3.5#1112’及該導電區域為3.7乂3.7#1112。 以上的設計包含其為絕緣之導電區域,其可降低來自該 基板的損耗。因此,其可改善該電感器的Q_值。再者,其 通常不需要額外的處理步驟來提供該基板接點,其係根據 相對於美國專利申請案08 / 82 1,88 0的已公開國際專利申請 PCT/SE9 7 / 0 04 8 7所揭示的來使用。 為了進一步加強其為高導電性及接地之基板7的效應, 如果需要的話,可使用分別一額外的?+或^的摻雜形式, 其由該井層9的表面延伸進入此疊層一些距離,如圖2&中 的區域27所不。這些額外摻雜的區域可藉由離子植入來獲 得’也可為與該井層9相同的摻雜形式。連同該基板接觸 針腳1 1,其可做為表面到基板的接點。 為了進一步改善該基板的屏蔽,根據CPYue等人的論 文所述,以及以上引用的國際專利申請w〇 98/50956中, 一額外導電的區域29 ’其圖案化層具有一大致與前述該導 電區域13反向的位置’並具有一些重疊,其可以放置在該 導電區域13之上或之下’如圖4a的橫截面架構圖及圖4b之 上視圖所示。該區域29可以形成在一第二金屬主要層m2O: \ 69 \ 69200-911016.ptc Page 12 518619 Cable No. 90103022 Amendment V. Description of the Invention (9) The entire inductor structure can be surrounded by a structure 21, which is composed of the same metal as the conductive area 13 The area of the layer is shown in FIG. 2b and FIG. 5. The metal frame 21 is electrically connected to a bottom frame-type contact pin 2 3 of the column frame ′, which is manufactured in the same manner as the substrate contact 丨 丨 and passes through the substrate 7. The metal frame 21 is a continuous strip, which has a notch or opening 25 to make it an open structure to avoid current flow. A typical value is that the width of the trench is, the island has a size of 3.5 \ 3.5 # 1112 'and the conductive region is 3.7 乂 3.7 # 1112. The above design includes that it is an insulated conductive region, which can reduce the loss from the substrate. Therefore, it can improve the Q_ value of the inductor. Furthermore, it usually does not require additional processing steps to provide the substrate contacts, and is based on published international patent application PCT / SE9 7/0 04 8 7 relative to US Patent Application 08/82 1,880. Revealed to use. In order to further enhance the effect that it is a highly conductive and grounded substrate 7, if necessary, can an additional one be used? The doped form of + or ^ extends from the surface of the well layer 9 into the stack some distance, as shown by the area 27 in Fig. 2 & These additional doped regions can be obtained by ion implantation or they can be in the same doped form as the well layer 9. Together with the substrate contact pins 11, it can be used as a surface-to-substrate contact. In order to further improve the shielding of the substrate, according to the paper by CPYue et al. And in the international patent application WO98 / 50956 cited above, an additional conductive region 29 'has a patterned layer having a conductive layer substantially similar to the aforementioned conductive region The position 13 is reversed 'and has some overlap, which can be placed above or below the conductive area 13' as shown in the cross-sectional architecture diagram of Fig. 4a and the view above Fig. 4b. The region 29 may be formed on a second metal main layer m2
O:\69\69200-911016.ptc 第13頁 518619 _案號90103022_年月曰 修正_ 五、發明說明(10) 此具有一大致與溝槽1相同的架構,但是,其路徑明顯地 可以比該溝槽稍寬或稍窄。該額外的導電圖案化層的這些 區域,基本上可以連接到一接地電位。 示於圖2 a - 2 c中的製造該結構的方法之主要步驟,將簡 單說明如下。 首先,提供其具有一良好導電性之一些基板或基板層7 並且因此而要加重摻雜如圖所示的P+或n+。該井層9然後 即加到該基板的上層,例如藉由磊晶成長。其係中度摻雜 到具有一相當低的導電性,即為範例中所示的摻雜形式 p -,但也可以相同地摻雜到η -。因此,該溝槽的深且窄的 凹處或空洞,首先可以由施加一屏蔽來產生,然後以乾蝕 刻來製造凹處而延伸到該基板層7的表面。該屏蔽層被移 除,而該凹處以電氣絕緣的材料,像是氧化矽來重新充 填,或是像未摻雜的複晶矽或其它的介電材料,以及任何 具有與該基板層7及該井層9的導電性低的材料等皆可。在 該重新充填過程中所產生的足夠窄的溝槽表面,將大致為 平坦的。由此所產生的該溝槽1,可具有約1-2//m的寬 度,以及約5 - 2 0 # m的深度。該表面結構,與相鄰溝槽之 間的基板材料之寬度,可以儘可能實際上地小,例如在 2-4 /zm的範圍内。 如果需要的話,一額外的摻雜可用來產生區域27,參見 圖2 a,其是要改善遮蔽效果,並包含額外植入的摻雜形式 的摻雜劑,例如井層9,其可在此階段製造出來,其係使 用一圖案化的光罩來僅植入在將要形成的電感器結構之内 的區域。O: \ 69 \ 69200-911016.ptc Page 13 518619 _Case No. 90103022_ Year, Month, and Revise Slightly wider or narrower than the groove. These areas of the additional conductive patterned layer can be basically connected to a ground potential. The main steps of the method of manufacturing the structure shown in Figs. 2a-2c will be briefly explained as follows. First, some substrates or substrate layers 7 having a good electrical conductivity are provided and therefore doped with P + or n + as shown in the figure. The well layer 9 is then added to the upper layer of the substrate, for example by epitaxial growth. It is moderately doped to have a relatively low conductivity, which is the doped form p-shown in the example, but it can also be doped to η-the same. Therefore, the deep and narrow recesses or cavities of the trench can first be created by applying a shield, and then the recesses are made by dry etching to extend to the surface of the substrate layer 7. The shielding layer is removed, and the recess is refilled with an electrically insulating material, such as silicon oxide, or an undoped polycrystalline silicon or other dielectric material, and any material having contact with the substrate layer 7 and Any material such as a low conductivity of the well layer 9 may be used. The sufficiently narrow trench surface produced during this refilling process will be approximately flat. The trench 1 thus produced may have a width of about 1-2 // m and a depth of about 5-2 0 # m. The surface structure and the width of the substrate material between adjacent trenches can be as small as practically possible, for example in the range of 2-4 / zm. If needed, an additional doping can be used to create the region 27, see Figure 2a, which is to improve the shielding effect and contains an additional implanted dopant in the form of a dopant, such as the well layer 9, which can be here Fabricated in stages, it uses a patterned photomask to implant only the area within the inductor structure to be formed.
O:\69\69200-911016.ptc 第14頁 518619 案號 90103022 Λ_η 曰 修正 五、發明說明(11) 在該晶圓表面上,約沉積有1 /z m的絕緣材料,其較佳地 是為氧化石夕,其也可使用習用的方法來做大致的平坦化, 藉以形成該鈍態層1 3 ’ 。然後,一深孔的屏蔽層即應用到 該大致平坦的絕緣材料之表面,然後即進行圖案化。該將 要產生的屏蔽窗及深孔,將具有對應於該溝槽寬度的尺 寸,也就是說其可具有在l-2/zm範圍内的寬度及直徑。該 深孔係由乾蝕刻所產生,並移除該屏蔽層。該深孔在該蝕 刻程序中所給定的深度係大於該鈍態層1 3 ’及該井層9的高 度,以向下達到其為高度摻雜之基板7。因此,習用的接 點孔,圖中未示,可下到任何主動或被動的裝置,圖中未 示,其需要製成電氣接點,大致上並應用到所有的接點孔 之一底層金屬層,圖中未示,例如其包含Ti, P t, Co, 其 未附著於該鈍態層1 3 ’的上部絕緣材料,最後,該孔洞係 以C V D沉積鎢來充填,但也可使用其它的金屬來形成該基 板接點 1 1及其它的接點栓塞 填充該金屬,π栓塞π 尺寸或直徑相同大小 在該沉積過程中,該深孔將完全地 如果該沉積厚度係與該深孔的橫向 然後,其它的導電層,例如包含 鋁,其可沉積在所有的晶圓表面上。在使用習用方法經由 兩個導電層的圖案化及蝕刻之後,該圖案化的W及Α1堆疊 將可做為該第一金屬主要層Ml。 然後即應用另一個鈍態層1 4,在此層中蝕刻有洞,並在 此絕緣層上部施加有另外的金屬層。此另外的金屬層(圖 2 a的疊層Μ 3 ),其係圖案化來包含該導電路徑1 5,用以連 接到該電感器路徑的内部端點。一進一步絕緣的氧化物層O: \ 69 \ 69200-911016.ptc Page 14 518619 Case No. 90103022 Λ_η Revision V. Description of Invention (11) On the surface of the wafer, about 1 / zm of insulating material is deposited, which is preferably for The oxide stone can also be roughly planarized by a conventional method, so as to form the passivation layer 13 '. Then, a deep hole shielding layer is applied to the surface of the substantially flat insulating material, and then patterned. The shielding window and deep hole to be generated will have a size corresponding to the width of the trench, that is, it may have a width and a diameter in the range of 1-2 / zm. The deep hole is created by dry etching, and the shielding layer is removed. The depth given by the deep hole in the etching process is greater than the height of the passive layer 1 3 'and the well layer 9 so as to reach down to the substrate 7 which is highly doped. Therefore, the conventional contact holes are not shown in the figure and can be lowered to any active or passive device. Not shown in the figure, they need to be made into electrical contacts. Generally, they are applied to one of all contact holes. Layer, not shown in the figure, for example, it contains Ti, P t, Co, which is not attached to the upper insulating material of the passive layer 1 3 ′. Finally, the hole is filled with tungsten deposited by CVD, but other materials can also be used. Metal to form the substrate contact 11 and other contact plugs to fill the metal, the π plug π has the same size or diameter during the deposition process, the deep hole will be completely if the thickness of the deposition is related to the Laterally, other conductive layers, such as containing aluminum, can be deposited on all wafer surfaces. After patterning and etching through two conductive layers using a conventional method, the patterned W and A1 stack can be used as the first metal main layer M1. Then another passivation layer 14 is applied, a hole is etched in this layer, and an additional metal layer is applied on top of this insulating layer. This additional metal layer (layer M3 of Fig. 2a) is patterned to contain the conductive path 15 for connection to the internal endpoint of the inductor path. A further insulating oxide layer
O:\69\69200-911016.ptc 第15頁 518619 _案號90103022_年月日__ 五、發明說明(12) 接著被施加,其中的孔洞被產生,在其上施加有一第三金 屬層(圖2a的疊層M4),其經過圖案化來形成該電感器路徑 17。每個主要金屬層的厚度基本上皆為l-2/zm的範圍。形 成該導體的該導體路控的寬度則約為5 /z m ’在該路徑的相 鄰部份之間的距離,係與該路徑的寬度同等大小。該上部 金屬層可藉由沉積一適當的金屬材料來產生,並也可填充 在該氧化層中的孔洞來構成電性連接到該底層金屬層的導 體。在沉積之後,該金屬層即使用習用的方法來蝕刻,藉 以形成所需要的導體。 該額外的圖案化金屬層(例如圖4 a的Μ 2 ),如果需要的 話,可由習用方法來形成,例如類似於那些對於該上部金 屬層所描述的。O: \ 69 \ 69200-911016.ptc Page 15 518619 _Case No. 90103022_ Year Month Day__ V. Description of the invention (12) Next, the hole is created, and a third metal layer is applied on it. (Layer M4 of FIG. 2a), which is patterned to form the inductor path 17. The thickness of each main metal layer is basically in the range of 1-2 / zm. The width of the conductor road control that forms the conductor is about 5 / z m ′, the distance between adjacent parts of the path, which is the same as the width of the path. The upper metal layer may be generated by depositing a suitable metal material, and may also fill holes in the oxide layer to form a conductor electrically connected to the bottom metal layer. After deposition, the metal layer is etched using conventional methods to form the required conductor. The additional patterned metal layer (e.g., M2 of Fig. 4a) can be formed by conventional methods if necessary, such as those similar to those described for the upper metal layer.
O:\69\69200-911016.ptc 第16頁 518619 _案號90103022_年月日_修正 圖式簡單說明 圖式元件符號說明 I 溝槽 5 島 7 基板或基板層 9 淺摻雜井層 II 基板接點或接點針腳 13 導電區域 13’ 鈍態層 14 鈍態層 15 導電路徑 17 電感器路徑 1 9 區域 2 1 架構 2 3 接點針腳 25 缺口或開口 2 7 區域 29 導電的區域O: \ 69 \ 69200-911016.ptc Page 16 518619 _Case No. 90103022_Year Month Day_Modified Illustration Brief Description of Schematic Element Symbol Description I Trench 5 Island 7 Substrate or Substrate Layer 9 Lightly Doped Well Layer II Substrate contacts or contact pins 13 Conductive area 13 'Passive layer 14 Passive layer 15 Conductive path 17 Inductor path 1 9 Region 2 1 Architecture 2 3 Contact pin 25 Notch or opening 2 7 Region 29 Conductive region
Ml、M2、M3、M4 金屬主要層Ml, M2, M3, M4 metal main layer
O:\69\69200-911016.ptc 第17頁O: \ 69 \ 69200-911016.ptc Page 17
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SE0004614A SE520093C2 (en) | 2000-12-13 | 2000-12-13 | Shielded inductor |
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SE (1) | SE520093C2 (en) |
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US6833603B1 (en) | 2003-08-11 | 2004-12-21 | International Business Machines Corporation | Dynamically patterned shielded high-Q inductor |
KR101205115B1 (en) * | 2004-04-27 | 2012-11-26 | 엔엑스피 비 브이 | Semiconductor device and method of manufacturing such a device |
US7268409B2 (en) | 2004-05-21 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spiral inductor with electrically controllable resistivity of silicon substrate layer |
US7247922B2 (en) | 2004-09-24 | 2007-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductor energy loss reduction techniques |
US10217703B2 (en) * | 2017-01-03 | 2019-02-26 | Xilinx, Inc. | Circuits for and methods of implementing an inductor and a pattern ground shield in an integrated circuit |
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TW363278B (en) * | 1998-01-16 | 1999-07-01 | Winbond Electronics Corp | Preparation method for semiconductor to increase the inductive resonance frequency and Q value |
US6310387B1 (en) * | 1999-05-03 | 2001-10-30 | Silicon Wave, Inc. | Integrated circuit inductor with high self-resonance frequency |
US6140197A (en) * | 1999-08-30 | 2000-10-31 | Chartered Semiconductor Manufacturing Ltd. | Method of making spiral-type RF inductors having a high quality factor (Q) |
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