SE520093C2 - Shielded inductor - Google Patents

Abstract

An integrated circuit comprises an inductor path (17) formed in a metal layer located in a surface structure on top of an electrically well conducting substrate (7). Trenches (1) filled with an electrically isolating material are located under the inductor path and are arranged in a meshlike or grid pattern. In order to improve the shielding of the inductor path and to simultaneously improve the Q-value of the inductor, in the islands (5) of material formed in the surface structure between the meshes of the pattern deep substrate contacts (11) are located. The substrate contacts extend down into the substrate and the substrate and the contacts are intended to be connected to ground potential. Electrically conducting areas (13) can cover the islands and are then connected to the substrate contacts.

Description

520 093 2 leads to improved Q-values due to both a shielding effect against the induction of electric currents in the substrate and a reduction of the induced eddy currents in the grounded shield layer, since the grounded shield layer is patterned in such a way that the currents can not circulate in the metal under the inductor, see fi g. la, lb in this application.

In Burghartz et al., "Progress in RF Inductors on Silicon - Understanding MMIC Inductors", IEDM Tech. Digest, 1998, p. 523 - 526, a comparison is made of different procedures for reducing substrate losses, between the embodiments described in the cited article by C.P. Yue et al. and in the cited patent application with Yue et al. as up. nnare.

The research area including inductors integrated in silicon structures is still under development. Reported results may seem contradictory. The exact mechanisms of the losses and the best way to set up models using equivalent circuits, which describe how the losses occur, in a physical, not too simplistic way, are still discussed. An inductor structure, which has good properties when used in an application circuit, can sometimes not have as good properties when used in another type of circuit, i.e. the electrical properties of the inductor structure depend on the actual circuit or more specifically on it. exact physical surrounding structure. It is therefore difficult to determine the optimal structure for an inductor with the help of purely theoretical investigations or calculations.

The procedure described in the article by C.P. Yue et al. and in corresponding patents, improves the performance of inductors. However, the metallization pattern must be continuous and it must be associated with a fixed potential at some point, preferably at fl your points, in order to function well as a cutting edge. However, no means are indicated for improving the effect of the substrate underlying the metallization pattern. In addition, the pattern has openings towards the substrate, in which the electromagnetic field can penetrate. According to our experiments and the cited article by Burghartz et al. For example, a grounding of the substrate near the electrical conductor, which constitutes the inductor, can improve the Q value, since an electrically well-conducting substrate with well-potential nied potential such as ground potential also acts as a shield and reduces the effects of eddy currents in the silicon. In the processes currently used to manufacture integrated circuits, however, there is no completely good contact on the front. The contacts used still have significant electrical resistance to the substrate.

In published international patent application WO 97/35344 corresponding to U.S. patent application No. 08 / 821,880, "Semiconductor device shielded by an array of electrically conductive pins and a method of manufacturing such a device", with inventors Tomas J arstad and Hans Norström, shows a shielding of a semiconductor component or electrical connection path on a semiconductor substrate, which shielding comprises separate substrate contacts arranged in a pattern around the component or conduit path, each contact having a relatively small cross-sectional area and cross-section - the cut surfaces, for example, are square.

Furthermore, Japanese Patent Application Laid-Open discloses an inductor provided with a trench which extends parallel to the electrical lead path of the inductor and is located between adjacent portions of the helical lead path. U.S. Patent 5,742.09l to Francois Hébert discloses an embodiment of an inductor with a helical metal conductor in which a continuous deep trench is located immediately below the helical path. In addition, a second continuously spiral-shaped trench can be arranged in the spaces of the first trench, ie also between adjacent parts of the helical conductor. In an alternative embodiment, the ditch has a mesh or net-like rectangular pattern, which is located below the entire surface occupied by the conductor, and can be considered as comprising two sets of sections of ditches, which cross each other, the sections in each set being parallel together. U.S. Patent 5,71, 7,243 discloses a configuration of an inductor with a helical metal conductor in which radial trenches are provided below the helical conduit path.

In the published international patent application WO 97/45873, which corresponds to U.S. patent application 08/865, 1, "Conductors for integrated circuits", with inventors Ted Johansson and Hans Norström, an embodiment of an inductor with a helical metal conductor is shown. in which a mesh or net-like pattern formed by the ditches is located below the area occupied by the metal conductor. The pattern may be a right-angled pattern comprising two sets of intersecting ditches, the ditches in each set being parallel to each other.

DESCRIPTION OF THE INVENTION It is an object of the present invention to provide an invention of an inductor for an integrated circuit with improved electrical shielding.

It is another object of the invention to provide an inductor in an integrated circuit with improved Q-value.

Consequently, a problem which the invention intends to solve is generally how to improve the Q-value of an inductor in an integrated circuit. In particular, the problem relates to how to shield the parasitic capacitances arising from the substrate without impairing the inductance of such an inductor.

Thus, in general, a shielded inductor comprises a suitably shaped electrical conductor, for example in a helical pattern, and a large set of ditches arranged in a pattern below the electrical conductor. The islands between the trenches openings contain the silicon substrate and an epitaxial structure arranged on top of the substrate. The substrate has good conductivity and can have a low-doped or weakly doped layer arranged on its upper side. The ditches extend from the surface down to the layer by doping p + or n +. In the islands there are substrate contacts, which are connected to metal areas, which cover the upper side of the islands, so that a separate metal area is arranged for each substrate contact. The metal areas are thus separated from each other laterally and they can cover substantially the entire surface of the islands and preferably also extend slightly over adjacent ditches, over small edge areas of these.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described as non-limiting embodiments with reference to the accompanying drawings, in which: - Fig. 1a is a perspective view of a patterned grounded scan according to the prior art, - F in g. a right-angled helical inductor arranged over the patterned grounded shield in fi g. 1a according to the prior art, - Fig. 2a is a schematic cross-section of a part of an integrated circuit, showing a surface structure comprising a lead path of an inductor with shielding formed in an alternative manner, - Fig. 2b is a schematic view from above of it in fi g. 2a, - F in g. 2c is a schematic top view of an inductor arranged above the surface structure according to fi g. 2a and 2b, - F in g. 3 is a top view of a pattern of ditches used under an inductor of an integrated circuit according to the prior art, - Fig. Fig. 4a is a schematic cross-section of a part of an integrated circuit, showing a surface structure comprising a lead path of an inductor with a further shielding structure, Fig. 4b is a schematic view above that in Figs. 4a shows the part of the shield, and - Figs. 5 is a schematic top view of a lead path of an inductor surrounded by a frame.

DESCRIPTION OF PREFERRED EMBODIMENTS Fig. 3 is a top view of a portion of a substrate in which a large group of ditches 1 have been etched to form a suitable pattern. The pattern with the ditches is used under a shielded inductor to reduce losses from the inductor to the substrate, as proposed in the cited US patent for Hébert and the cited international patent application WO 97/45 873. The pattern shown comprises a first set of several straight similar ditches arranged parallel to each other and at equal distances and also a second set of similar ditches arranged parallel to each other and at equal distances, so that the ditches in the second set are perpendicular to the ditches included in the first set. In each selected pattern, the ditches should be so long and located that they pass past the outermost turns of the inductor into substrate material surrounding the inductor. The pattern used for the ditches can have any design with meshes or net shapes, comprising short sections of ditches, which are connected to each other and delimit relatively small islands, which are separated from each other. The islands may thus have any suitable, preferably convex, form, for example, triangular, square, rectangular, diamond-shaped, hexagonal, octagonal, circular, and so on. The ditches are generally deep and elongated, continuous recesses or grooves, which extend from some surface layer of the structure down into the substrate. The islands 5 between the ditches are remaining parts of a silicon substrate or substrate layer 7 and of some layer structure arranged on top of the substrate, see the schematic cross-section in fi g. 2a. The substrate 7 has doping type p + or n + and consequently has relatively good electrical conductivity and in the embodiment shown, a low-doped well layer 9 with doping type p- or n- is located on top of the same. The ditches 1 extend from the surface of the well layer 9 of type p- or n- down into the substrate or layer 7, which has good electrical conductivity with doping of type p + or n +. The substrate 7 and the doping types of the well are in the embodiments shown in Fig. 2a the same, i.e. they are both of p-type or n-type, but they can also be different, i.e. the substrate can be of p-type and the well of n- type or the substrate may be of the n-type and the well of the p-type.

In each remaining island 5 between the ditches there is a substrate contact or a contact path of a suitable filling, electrically conductive material, for example a metal such as W, for example of the type described in the cited international patent application WO 97/35344. These contact pins 11 may be connected to metal areas 13 arranged on the upper side of each remaining island 5 and they extend into the substrate layer 7, with which they are consequently electrically connected and which is intended to be connected to some constant potential such as earth potential, whereby the substrate is shielded from the electric field, which is generated by the electric current which flows in the electric conductor path of the inductor. Consequently, only the electric field is blocked, which leads to a lower impact on the inductor from the parasitic capacitances. The magnetic field is not blocked. With a complete scan without any hole, the magnetic field would be blocked and thereby the inductances and the Q-value of the conductor considered would be reduced. The substrate contacts 11 are generally in the form of narrow paths or rods arranged in deep bottom holes of the well 9 and extend into the substrate layer 7. The pins or rods may suitably have a square cross-section.

The metal areas 13 are formed as separate islands over the remaining silicon in each island 5 and extend to the ditches 1, which form boundaries of the respective islands, and they also preferably extend a small distance beyond these boundaries, so that they comprise narrow edge strips located above the ditches 1. The metal areas 13 are electrically connected to earth potential via the substrate contacts 11 and the substrate 7. They do not have direct contact with any other metal surface, as shown by the view from above in fi g. 2b. This reduces eddy currents induced in the metal areas 13. The metal areas 13 may be remaining areas of a patterned first metal main layer M 1 in or at the surface of the structure, this first metal layer being formed on top of a passivation layer 13 ', which in its tour is arranged immediately on top of well 9 and ditches l. On top of deni fi g. The structure shown in Fig. 2b comprising an upper metal layer M1 is another non-passivating layer or electrically insulating layer 14 such as a silicon oxide layer deposited. Additional patterned metal main layers M2, M3, may be arranged above the insulating layer 14. The additional metal main layers are then also patterned and they are separated by electrically insulating layers, for example of silica. In these layers, the helical lead path of an inductor is produced by utilizing the additional metal layers as is well known in the art, see for example the cited international patent applications. Thus, in a lower metal layer such as M3 a lower conductor path 15 can be formed and in the metal layer M4 immediately above it the conductor path 17 itself of the inductor can be formed, see also fi g. 2c, which shows the final structure seen from above. This figure shows an area 19, which is located under the entire conductor path of the inductor and is completely filled with a group of ditches and substrate contacts, as has been described with reference to fi g. 2a and 2b.

The entire inductor structure can be surrounded by a frame 21 comprising areas of the same metal layer as the metal areas 13, see fi g. 2b and fi g. 5. The metal frame 21 is electrically connected to an underlying frame-like structure comprising rows of contact path fi 23 formed in the same manner as the substrate contacts 11 and penetrating into the substrate 7. The metal frame 21 is a continuous strip with a gap or opening 25. , so that it becomes an open structure, in order to avoid circulating currents.

Typical values may be that the ditches have a width of 1 μm, the islands have dimensions of 3.5 x 3.5 umz and the metal islands 3.7 x 3.7 umz.

The structure described above comprising insulated metal islands reduces losses from the silicon substrate. Consequently, it improves the Q values of the inductors. In addition, no further processing steps are generally required, provided that substrate contacts as disclosed in published International Patent Application PCT / SE97 / 00487 corresponding to U.S. Patent Application 08/82 1,880 are used.

In order to further improve the effect of the highly conductive, grounded substrate 7, a further doping of type p + resp. n + be used, which extends from the surface of the well layer 9 and some distance into this layer, see areas 27 in fi g. 2a. These additional doped areas can be achieved by ion implantation and have the same type of doping as well 9. Together with the substrate contact pins 11, they function as surface-to-substrate contacts.

To further improve the shielding of the substrate, as described in the article by C.P. Yue et al. and in International Patent Application WO 98/50956, cited above, areas 29 of an additional electrically conductive patterned layer, which have a substantially inverted position relative to the metal islands 13 described above and have a certain overlap, is placed above or below the cutting islands 13, as illustrated by the schematic cross-sectional view in fi g. 4a and the top view in fi g. 4b. The grooves 29 may be formed in a second metal main layer M2 and thus have a shape which substantially corresponds to the shape of the ditches 1, but its conduit paths may obviously be slightly wider or narrower than the ditches. These areas of the additional conductive patterned layer may typically be associated with ground potential.

The main steps of a process for manufacturing it in fi g. 2a - 2c will now be briefly described.

First, a substrate or substrate layer 7 is provided which has good electrical conductivity and is consequently highly doped, with either p +, as shown, or n +. The well layer 9 is then applied on top of the substrate, for example by epitaxial culture. It is medium-high doped, so that it has a fairly low electrical conductivity, with doping of, for example, type p- in the example shown, but it can still be doped to n-. Then deep and narrow recesses or cavities for the ditches are made, by first applying a mask and then performing dry etching to make recesses which extend into the surface of the substrate layer 7. The mask layer is removed and recesses are filled with electrically insulating material, such as silica, undoped polysilicon or any other dielectric material, and in each case the material should have an electrical conductivity lower than the electrical conductivity of the substrate layer 7 and the well layer 9. . For sufficiently narrow holes, the surface provided on top of the substrate during the backfilling process becomes substantially flat. The ditches l obtained in this way can have a width of approximately 1 - 2 μm and a depth of approximately 5 - 20 μm. The width of the substrate structure and the substrate material between adjacent ditches can be as small as is practically possible, for example in the range 2 - 4 μm.

If desired, a further doping to provide the areas 27, see fi g. 2a, intended to improve the shielding and comprising further implanted doping agents of the same doping type as the well 9, can be performed in this step, by means of a patterned photomask to only implant areas within the inductor structure to be formed.

Approximately 1 μm of electrically insulating material, preferably silica, is deposited on the surface of the plate, and it can then be made substantially flat by conventional methods to form the insulating layer 13 '. Next, a mesh layer for deep holes is applied to the substantially flat surface of the insulating material and then patterned. The openings in the mask and the deep holes to be made may have dimensions corresponding to the width of the ditches, ie they may have widths / diaphragms within the range 1 - 2 μm. The deep holes are made by dry etching and the mask layer is removed. The deep holes are given in the etching process a depth greater than the height of the insulating layer 13 'and the well layer 9 to reach down to the highly doped substrate 7. Then conventional contact holes, not shown, down to all active or passive devices, not shown, which require electrical contact, and then applied to all contact holes in a lower metal layer, for example comprising Ti, Pt, Co, which do not adhere to the insulating material in the upper layer 13 ' . This lower metal layer is heated for a short period of time to form a good metal-to-semiconductor count. A barrier metal, not shown, for example TiN, is deposited in the holes on top of the lower metal layer and finally the holes are filled with CVD-deposited tungsten W, but other metals can also be used to form the substrate contacts 11 and other contact plugs. During deposition, the deep holes are completely filled with the metal, "plugged again", if the deposited thickness is of the same order of magnitude as the transverse seam or diameter of the deep holes. During the filling process, wool fi am W is also deposited on the surface of the plate. Next, another electrically conductive layer, for example comprising aluminum, is deposited over the entire surface of the plate. After patterning and etching through the two conductive layers by conventional methods, the adjacent, patterned W and Al layers serve as the first metal main layer M1.

Another electrically insulating oxide layer 14 is then applied, holes are etched in this layer and another metal layer is applied on top of this insulating layer. This second metal layer (layer M3 in Fig. 2a) is patterned so that it will comprise the electrical conductor 15 for connecting the inner end of the conductor path of the inductor. An additional electrically insulating oxide layer is then applied, holes are made therein and then a third metal layer (layer M4 in Fig. 2a) is applied and patterned to form the conductor path 7. The thickness of each of the main metal layers may typically be within area l - 2 pm. The width of the conduit path forming the inductor may be about 5 μm and the distance between adjacent portions of the conduit path may be of the same order of magnitude as the width of the conduit paths. The upper metal layers can be provided by depositing a suitable metal material to also fill the holes in the oxide layer, so that electrical connections to the members of the underlying metal layer are provided. After deposition, the metal layers are etched by conventional methods to form the required conductors.

The additional patterned metallization layers (for example M2 in fi g. 4a) are formed, if required, by means of conventional methods, for example those described for the upper metal layers.

Claims (12)

An integrated circuit comprising an inductor, which comprises a metal conductor arranged in a surface structure of a substrate with good electrical conductivity, in particular a doped silicon substrate, and further comprising ditches in the surface structure. , which extend into the substrate, are located below the metal conductor and are filled with electrically insulating material, the ditches being arranged in a mesh-like pattern with meshes or in a grid pattern, so that islands are formed by the substrate material in the surface structure between the meshes of the pattern between adjacent parts of the ditches, characterized by substrate contacts arranged inside the spaced apart islands formed by the meshes, the substrate contacts being made of electrically conductive material and extending through the surface structure down into the substrate. Integrated circuit according to claim 1, characterized by separate first electrically conductive areas covering the islands, the first electrically conductive areas being connected to respective separated substrate contacts and being electrically isolated from each other. Integrated circuit according to claim 2, characterized in that the first electrically conductive areas have an extension, so that they cover relatively narrow edge portions of adjacent ditches. Integrated circuit according to one of Claims 2 to 3, characterized in that the first electrically conductive regions are electrically insulated from the metal conductor by an electrically insulating layer arranged on top of the first electrically conductive regions. Integrated circuit according to one of Claims 1 to 4, characterized in that in the separated islands the material has a doping at its surface in order to give the surface a good electrical conductivity. Integrated circuit according to one of Claims 2 to 4, characterized by other electrically conductive areas which cover the ditches. Integrated circuit according to claim 6, characterized in! because the other electrically conductive areas are designed with substantially the same patterns as the ditches. Integrated circuit according to one of Claims 6 to 7, characterized in that the second electrical regions are regions of a metallised layer located in a plane above or below the first electrically conductive regions. Integrated circuit according to one of Claims 1 to 8, characterized by a metal tube which surrounds the metal conductor of the inductor. 10. lO. Integrated circuit according to claim 9, characterized in that the metal frame is electrically connected to a structure of substrate contacts located below the metal frame. Integrated circuit according to one of Claims 9 to 10, characterized in that the metal frame is designed as a continuous strip with at least one gap. 520 093/0 Integrated circuit according to one of Claims 2 to 4, characterized by a metal pipe which surrounds the metal conductor of the inductor and is formed in a metal layer in which the first electrically conductive regions are formed.