TW578282B - Thermal- enhance MCM package - Google Patents

Thermal- enhance MCM package Download PDF

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Publication number
TW578282B
TW578282B TW091137929A TW91137929A TW578282B TW 578282 B TW578282 B TW 578282B TW 091137929 A TW091137929 A TW 091137929A TW 91137929 A TW91137929 A TW 91137929A TW 578282 B TW578282 B TW 578282B
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Taiwan
Prior art keywords
wafer
substrate
chip
scope
patent application
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TW091137929A
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English (en)
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TW200411865A (en
Inventor
Su Tao
Chian-Chi Lin
Chih-Huang Chang
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Advanced Semiconductor Eng
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Priority to TW091137929A priority Critical patent/TW578282B/zh
Priority to US10/693,976 priority patent/US20040124512A1/en
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Publication of TW578282B publication Critical patent/TW578282B/zh
Publication of TW200411865A publication Critical patent/TW200411865A/zh

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    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
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Description

578282 五、發明說明（1) ()、【發明所屬之技術領域】 裝構造，且特別是有關 構造。 …、里傳遞至母板之加強散熱型多晶片封裝 (二）、【先前技術】 半導由於電子產品越來越輕薄短小，使得用以保護 及提供外部電路連接的封裝構造也同樣需要 槿'土，者微小化以及高運作速度需求的增加，乡晶片封裝 = ^mUUiihipSi〇dule; MCM)在許多電子裝置越來越 。多晶片封裝構造可藉由將兩個或兩個以上之晶 ^ 4 Jl ^(processor) > le, ^ ^(ineinory) a ^ ^ 位Uogic))組合在單一封裝構造中，來使系統運 2度之限制最小化。此外，多晶片封裝構造可減少晶片 曰’銲f =之長度而降低訊號延遲以及存取時間。 取常見的多晶片封裝構造分別為並排式（side-by-Slde)多晶片封裝構造及堆疊式（stacked)多晶片封裝構 U 並排式夕晶片封裝構造係將兩個以上之晶片彼此並排 地安裝於一共同基板之主要安裝面。晶片與共同基板上導 電線路間之連接一般係藉由打線接合之方式（wire bonding)或覆晶接合方式—chip b〇nding)達成。而 多晶片堆疊裝置（multichip stacked device)則是將兩個 以上之晶片依序堆疊在一基板上，再分別以導電線或導電
Ι·ϋ 第6頁 578282 五、發明說明（2) —- 凸塊（conductive bump)電性連結於該基板。 然而，當多晶片構造中包含_個具有高密纟、 數位電路之晶片時，由於其在運作中會產生高&，故 通常會傳遞至基板上，然而由於基板上係覆蓋銲罩層以 護其内部線路，故其與外界間之散熱性能不佳，如传 熱量傳遞至母板’π影響其他於母板上之電子元件之作使 動。 有鑑於此，需要一種加強散熱型多晶片封裝構造用以 服或至少改善前述先前技術中的難題，實為一重要的 名自 η ^ 〔三）、【發明概要】 刑夕Ϊ ^於上述課題，本發明之目的係提供一種加強散熱 =阳封裝構造，且特別是有關於一種降低晶片熱量傳 遞至母板之半導體封裝構造。 :，成本發明之上述目的，特提出一種加強散熱今 :片：裝構造，其至少包含一第一晶片、—第二晶片、 拉 …、兀件。該第一晶片及第二晶片係以覆晶戈
i、s t與基/反連接或以打線接合方式藉導電線與基板1 板=’本政查熱兀件係可藉導熱膠與第一晶片、第二晶片及 傳 ’、2妾。由於散熱元件與基板間之熱傳導係藉由招 界/六^乂散熱元件與外界（空氣）之散熱效果遠比基板與 私#'虱之散熱效果佳，故部份由晶片產生之熱量能箱 …、元件導出至外界，而不經由基板傳遞至母板，故喝
第7頁 578282 五、發明說明（3) 較不易累積大量熱能，也不會因此而影響其他於母板上之 電子元件之作動。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之加 強散熱型多晶片封裝構造。 如圖1 A及1 B所示，本發明第一較佳實施例之加強散熱 型多晶片封裝構造主要包括一基板1、第一晶片2、第二晶 片3及一散熱元件4。基板1具有一上表面12及一相對於上 表面12之下表面14。該基板1之上表面12係具有第一晶片 设置區122、第二晶片設置區124及散熱元件設置區126;下 表面14具有複數個銲球8，用以與母板（未標示於圖中）電 性連接。該第一晶片2及第二晶片3係以覆晶方式分別設置 於第一晶片设置區122及第二晶片設置區124上，並藉凸塊 5以使基板1與第一晶片2之主動面22及第二晶片主動面32 電性連接。散熱元件4係由第一晶片接合部4 2、第二晶片 接合部44、基板接合部46及連接部48所組成；而第一晶片 接合部4 2、第二晶片接合部4 4及基板接合部4 6係藉由連接 部48而連結。其中，散熱元件4之第一晶片接合部42、第 二晶片接合部4 4及基板接合部4 6係藉導熱膠7分別與第一 曰曰片背面2 4、第一晶片背面3 4連接及散熱元件設置區1 2 6 連接。 此外’違散熱元件设置區1 2 6形成有複數個孔洞丨2 8 (可為一貫孔或一盲孔），且其中填充有導熱膠，用以連接
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基板1之電路層129，使基板丨之熱量能經 接合部46向外界傳遞。又，該孔洞128可“1電之芦U 層)於其壁面，以使散熱元件4能與基板1之接 $電路層（未標示於圖中）電性連接，除可使基板i之故量 月匕經散熱元件4之基板接合部46向外界傳遞，更可提供第 一晶片2或第二晶片3 —較佳之屏蔽（51^61幻叫）。 再者，可於第一晶片主動面22或第二晶片主動表_ 與基板1間填充底膠6，以降低基板丨與第一或第二晶片間 之熱j力問題。此外，更可以一封膠體（未標示於圖中）至 夕覆蓋第一晶片2、第二晶片3及一散熱元件4並至少暴露 出該政熱元件之基板接合部46，以提供晶片熱量一較佳之 散熱介面，減少傳遞熱量至母板。 接著’請參照圖2，為本發明第二較佳實施例。與第 一較佳實施例不同的是，該散熱元件4之第一晶片接合部 4 2係具有複數個第一開口 4 2 2以暴露出第一晶片2主動面2 2 之該等第一銲墊2 5，而第二晶片接合部4 4係具有複數個第 二開口442以暴露出第二晶片3主動面32之該等第二銲墊 3 5。該第一晶片2及第二晶片3係以打線方式（w i re bonding)分別設置於第一晶片設置區122及第二晶片設置 區124上，並藉導電線9(如金線）以使基板1與第一晶片2之 主動面22及第二晶片3之主動面32電性連接。其中，該等 導電線9係經由該等第一開口 422及該等第二開口 442穿設 之以連接第一銲墊25與第一晶片設置區122及第二銲墊35 與第二晶片設置區1 2 4。
第9頁 578282 五、發明說明（5) 又，形成一射膠體1 〇以至少覆蓋第一晶片2、第二晶 片3、該基板1、該等導電線9及該散熱元件4之第一晶片接 合部4 2與第二晶片接合部4 4。惟’該散熱元件4之基板接 合部4 6係至少暴露出該封膠體1 〇以提供晶片熱量一較佳之 散熱介面，減少傳遞熱量至母板。 承上述，請參照圖3，如本發明第三較佳實施例所 示，第一晶片2及第二晶片3以打線方式（wire bonding)設 置於基板1上時，該散熱元件4之第一晶片接合部42及第二 晶片接合部44分別與第一晶片2及第二晶片3間設置一虛晶 片lUdummy die)，且該散熱元件4之上表面係暴露出該封 膠體1 0 ’以提供較佳之散熱能力。 另外’請參照圖4，如本發明第四較佳實施例所示， 第一晶片2及第二晶片3以打線方式（wire b〇nding)設置於 基板1上時’該散熱元件4之第一晶片接合部42及第二晶片 接合部44分別與第—晶片2及第二晶片3間設置一導熱銲球 或導熱凸塊4 ’且該散熱元件4之上表面係暴露出該封膠 體10，以提=較佳之散熱能力。 ^最後，請參照圖5，如本發明第三較佳實施例所示， 第日日片2及弟日日片3以打線方式（wire bonding)設置於 基板1上時，該散熱元件4之第一晶片接合部42及第二晶片 接合部44分別具有一第一突出部及第二突出部444，以 暴露出該封膠體1 0，以提供較佳之散熱能力。需說明的 是，圖2、3、4及5中各元件之參考符號係與圖丨中之各元 件之參考符號相對應。
第10頁 578282 五、發明說明（6) 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 578282 圖式簡單說明 (五）、【圖式之簡單說明】 圖1 A為一示意圖，顯示本發明第一較佳實施例之加強 散熱型多晶片封裝構造。 圖1 B為第一較佳實施例中基板構造之平面示意圖。 圖2為一示意圖，顯示本發明第二較佳實施例之加強 散熱型多晶片封裝構造。 圖3為一示意圖，顯示本發明第三較佳實施例之加強 散熱型多晶片封裝構造。
圖4為一散熱片剖面示意圖，顯示本發明第四較佳實 施例中之散熱片構造。 圖5為一散熱片剖面示意圖，顯示本發明第五較佳實 施例中之散熱片構造。 元件符號說明： 1 基板 12 基板上表面
122 第一晶片設置區 124 第二晶片設置區 126 散熱元件設置區 128 孔洞 129 電路層 14 基板下表面 142 銲球銲墊 2 第一晶片
第12頁 578282 圖式簡單說明 22 第一晶片 主 動 面 24 第一晶片 背 面 25 第一銲墊 3 第二晶片 32 第二晶片 主 動 面 34 第二晶片 背 面 35 第二銲墊 4 散熱元件 4， 導熱凸塊（導熱銲 42 第一晶片 接合部 422 第一開口 424 第一凸出 部 44 第二晶片 接合部 442 第二開口 444 第二凸出 部 46 基板接合部 48 連接部 5 凸塊 6 底膠 7 導熱膠 8 焊球 9 導電線 10 封膠體 11 虛晶片
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Claims (1)

  1. 578282 六、申請專利範圍 1. 一種加強散熱型多晶片封裝構造，其包含： 一第一晶片； 一第二晶片； 一基板，具有一上表面，該上表面具有一第一晶片設置 區、一第二晶片設置區及一散熱元件設置區，該第一晶 片係以覆晶接合的方式設於該基板之第一晶片設置區， 該第二晶片係以覆晶接合的方式設於該基板之第二晶片 設置區，以及
    一散熱元件，設於該基板之散熱元件設置區並覆蓋該第一 晶片及該第二晶片。 2. 如申請專利範圍第1項所述之加強散熱型多晶片封裝構 造，其中該散熱元件係由一第一晶片接合部、一第二晶片 接合部、一基板接合部及一連接部組成，該連接部係用以 連接該第一晶片接合部、該第二晶片接合部及該基板接合 部，該第一晶片接合部係與該第一晶片相連接，該第二晶 片接合部係與該第二晶片相連接，該基板接合部係與該基 板之散熱元件設置區相連接。
    3. 如申請專利範圍第1項所述之加強散熱型多晶片封裝構 造，其中該散熱元件係藉導熱膠與該基板之散熱元件設置 區相連接。 4.如申請專利範圍第3項所述之加強散熱型多晶片封裝構
    第14頁 578282 六、申請專利範圍 造，其中該基板更包含至少一電路層且該散熱元件設置區 更具有至少一孔洞，該孔洞係填充導熱膠且與基板之電路 層相連接。 5. 如申請專利範圍第2項所述之加強散熱型多晶片封裝構 造，其中該基板更包含至少一接地電路層且該散熱元件設 置區更具有至少一孔洞，該孔洞之孔壁係形成有一導電 層，該導電層係用以電性連接基板之接地電路層與該散熱 元件。
    6. 如申請專利範圍第5項所述之加強散熱型多晶片封裝構 造，其中該導電層係為一銅金屬層。 7. 如申請專利範圍第1項所述之加強散熱型多晶片封裝構 造，其中該第一晶片與該第二晶片係藉一凸塊分別與該基 板之第一晶片設置區及第二晶片設置區連接以使其與該基 板電性連接。
    8. 如申請專利範圍第7項所述之加強散熱型多晶片封裝構 造，其中該第一晶片與該第一晶片設置區之間係填充一底 膠0 9.如申請專利範圍第7項所述之加強散熱型多晶片封裝構 造，其中該第二晶片與該第二晶片設置區之間係填充一底
    第15頁 578282 六、申請專利範圍 膠。 1 0 ·如申請專利範圍第1項所述之加強散熱型多晶片封裝構 造，其中該散熱元件係由銅所組成。 1 1 ·如申請專利範圍第1項所述之加強散熱型多晶片封裝構 造，其中該基板更具有一下表面，該下表面更形成有複數 個銲球。 1 2. —種加強散熱型多晶片封裝構造，其包含： 一第一晶片； 一第二晶片， 一基板，具肴一上表面，該上表面具有一第一晶片設置 區、一第二晶片設置區及一散熱元件設置區，該第一晶 片係以打線接合的方式設於該基板之第一晶片設置區， 該第二晶片係以打線接合的方式設於該基板之第二晶片 設置區，以及 一散熱元件，設於該基板之上散熱元件設置區並覆蓋該第 一晶片及該第二晶片。 1 3.如申請專利範圍第1 2項所述之加強散熱型多晶片封裝 構造，其中該第一晶片與該第二晶片係分別具有第一主動 面與第二主動面，該第一主動面係具有複數個第一銲墊， 該第二主動面係具有複數個第二銲墊，該第一銲墊與該第
    第16頁 578282
    六、申請專利範圍 ^塾係藉一導電線分別與該基板之第一晶片設置區及第 晶片設置區連接以與該基板電性導接。
    1 4·如申請專利範圍第1 3項所述之加強散熱型多晶片封裝 構造’其中該散熱元件係由一第一晶片接合部、一第二晶 片接合部、一基板接合部及一連接部組成，該連接部係用 以連接δ亥第一晶片接合部、該第二晶片接合部及該基板接 合部，該第一晶片接合部係具有複數個第一開口以暴露出 該等第一銲墊且與該第一晶片相連接，該第二晶片接合部 係具有複數個第二開口以暴露出該等第二銲墊且與該第二 晶片相連接，該基板接合部係與該基板之散熱元件設置區 相連接，該等導電線係經由該等第一開口及該等第二開口 穿設之以連接第一銲墊與第一晶片設置區及第二銲墊與第 二晶片設置區。
    1 5.如申請專利範圍第1 4項所述之加強散熱型多晶片封裝 構造，更包含一封膠體，該封膠體係覆蓋該第一晶片、該 第二晶片、該基板、該等導電線及該散熱元件之第一晶片 接合部與第二晶片接合部。 1 6 ·如申請專利範圍第1 5項所述之加強散熱型多晶片封裝 構造，其中該散熱元件之基板接合部係暴露出該封裝膠 體0
    578282 六、申請專利範圍 1 7 ·如申請專利範圍第1 6項所述之加強散熱型多晶片封裝 構造，其中該散熱元件之連接部係暴露出該封裝膠體。 1 8 ·如申請專利範圍第1 4項所述之加強政熱型多晶片封裝 構造，其中該散熱元件之第/晶片接合部更具有一第—凸 出部以暴露出該封膠體。 1 9 ·如申請專利範圍第1 4項所述之加強散熱型多晶片封裝 構造，其中該散熱元件之第二晶片接合部更具有一第二凸 出部以暴露出該封膠體。 2 〇.如申請專利範圍第丨2項所述之加強散熱型多晶片封裝 構造，其中該散熱元件係由鈉所組成。 構造’其十該基板更具有 數個銲球 2 1 ·如申請專利範圍第丨2項所述之加強散熱型多晶片封裝 m ^表面，該下表面更形成有複 2 2.如申請專利範圍第丨2項所述之加強政熱型多晶片封裝 構造，其中該散熱元件係藉導熱膠與該基板之散熱元件設 置區相連接。 23·如申請專利範圍第22項所述之加強散熱^多晶片封裝 構造，其中該基板之散熱元件設置區具有複數個孔洞，該
    578282 六、申請專利範圍 孔洞係填充導熱膠。 2 4 ·如申請專利範圍第1 3項所述之加強散熱型多晶片封裝 構造，其中該基板更包含至少一接地電路層且該散熱元件 設置區更具有至少一孔洞，該孔洞之孔壁係形成有一導電 層，該導電層係用以電性連接基板之接地電路層與該散熱 元件。
    2 5·如申請專利範圍第24項所述之加強散熱型多晶片封裝 構造，其中該導電層係為一銅金屬層。 2 6.如申請專利範圍第1 3項所述之加強散熱型多晶片封裝 構造’其中該散熱元件係由一第一晶片接合部、一第二晶 片接合部、一基板接合部及一連接部組成，該連接部係用 以連接該第一晶片接合部、該第二晶片接合部及該基板接 合部，該第一晶片接合部及該第二晶片接合部係分別藉由 一虛晶片（d u m m y d i e )與第/晶片及第二晶片相連接，該 基板接合部係與該基板之散熱元件設置區相連接。 2 7.如申請專利範圍第1 3項所述之加強散熱型多晶片封裝 構造，其中該散熱元件係由一第一晶片接合部、一第二晶 片接合部、一基板接合部及一連接部組成，該連接部係用 以連接該第一晶片接合部、遠弟二晶片接合部及該基板接 合部，該第一晶片接合部及該第二晶片接合部係分別藉由
    第19頁 578282 六、申請專利範圍 複數個導熱凸塊與第一晶片及第二晶片相連接，該基板接 合部係與該基板之散熱元件設置區相連接。 2 8 ·如申請專利範圍第2 6項所述之加強散熱型多晶片封裝 構造，該虛晶片係藉由導熱膠與與第一晶片相連接。 2 9.如申請專利範圍第2 6項所述之加強散熱型多晶片封裝 構造，該虛晶片係藉由導熱膠與與第二晶片相連接。 3 0.如申請專利範圍第2 6項所述之加強散熱型多晶片封裝 構造，該虛晶片係藉由導熱膠與與散熱元件之第一晶片接 合部相連接。 3 1.如申請專利範圍第2 6項所述之加強散熱型多晶片封裝 構造’該虛晶片係措由導熱膠與與散熱元件之苐二晶片接 合部相連接。
    第20頁
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US7355289B2 (en) * 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
US7521793B2 (en) * 2005-09-26 2009-04-21 Temic Automotive Of North America, Inc. Integrated circuit mounting for thermal stress relief useable in a multi-chip module
US8946904B2 (en) 2010-08-27 2015-02-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Substrate vias for heat removal from semiconductor die
US8963334B2 (en) * 2011-08-30 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Die-to-die gap control for semiconductor structure and method
US9082633B2 (en) * 2011-10-13 2015-07-14 Xilinx, Inc. Multi-die integrated circuit structure with heat sink
US9881908B2 (en) * 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
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CN112786532A (zh) * 2021-01-12 2021-05-11 杰群电子科技（东莞）有限公司 一种功率模组制造方法及功率模组封装结构
TWI796694B (zh) * 2021-05-21 2023-03-21 矽品精密工業股份有限公司 電子封裝件及其製法
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