TW573324B - Dummy structures to reduce metal recess in electropolishing process - Google Patents

Dummy structures to reduce metal recess in electropolishing process Download PDF

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Publication number
TW573324B
TW573324B TW91118816A TW91118816A TW573324B TW 573324 B TW573324 B TW 573324B TW 91118816 A TW91118816 A TW 91118816A TW 91118816 A TW91118816 A TW 91118816A TW 573324 B TW573324 B TW 573324B
Authority
TW
Taiwan
Prior art keywords
patent application
semiconductor structure
dummy structures
scope
dummy
Prior art date
Application number
TW91118816A
Other languages
English (en)
Chinese (zh)
Inventor
Hui Wang
Peihaur Yih
Original Assignee
Acm Res Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acm Res Inc filed Critical Acm Res Inc
Application granted granted Critical
Publication of TW573324B publication Critical patent/TW573324B/zh

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW91118816A 2001-08-23 2002-08-20 Dummy structures to reduce metal recess in electropolishing process TW573324B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US31461701P 2001-08-23 2001-08-23

Publications (1)

Publication Number Publication Date
TW573324B true TW573324B (en) 2004-01-21

Family

ID=23220680

Family Applications (1)

Application Number Title Priority Date Filing Date
TW91118816A TW573324B (en) 2001-08-23 2002-08-20 Dummy structures to reduce metal recess in electropolishing process

Country Status (8)

Country Link
US (1) US20040253810A1 (https=)
EP (1) EP1419523A4 (https=)
JP (1) JP2005501412A (https=)
KR (1) KR101055564B1 (https=)
CN (1) CN100524644C (https=)
CA (1) CA2456301A1 (https=)
TW (1) TW573324B (https=)
WO (1) WO2003019641A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI382797B (zh) * 2009-04-16 2013-01-11 三星電機公司 溝槽基板及其製法
TWI852347B (zh) * 2022-04-13 2024-08-11 台灣積體電路製造股份有限公司 積體電路封裝及其形成方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1505653A1 (en) * 2003-08-04 2005-02-09 STMicroelectronics S.r.l. Layout method for dummy structures and corresponding integrated circuit
US20050045993A1 (en) * 2003-08-28 2005-03-03 Sanyo Electric Co., Ltd. Semiconductor device with concave patterns in dielectric film and manufacturing method thereof
US7074710B2 (en) * 2004-11-03 2006-07-11 Lsi Logic Corporation Method of wafer patterning for reducing edge exclusion zone
JP5401135B2 (ja) * 2009-03-18 2014-01-29 株式会社ニューフレアテクノロジー 荷電粒子ビーム描画方法、荷電粒子ビーム描画装置及びプログラム
US20130075268A1 (en) * 2011-09-28 2013-03-28 Micron Technology, Inc. Methods of Forming Through-Substrate Vias
CN103692293B (zh) * 2012-09-27 2018-01-16 盛美半导体设备（上海）有限公司 无应力抛光装置及抛光方法
US8627243B1 (en) * 2012-10-12 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for optimizing conductor patterns for ECP and CMP in semiconductor processing
WO2014082197A1 (en) * 2012-11-27 2014-06-05 Acm Research (Shanghai) Inc. Method for forming interconnection structures
WO2019066792A1 (en) * 2017-09-27 2019-04-04 Intel Corporation INTEGRATED CIRCUIT COMPONENTS WITH FACIAL STRUCTURES
JP2023183338A (ja) * 2022-06-15 2023-12-27 日本メクトロン株式会社 導電パターン形成方法

Family Cites Families (17)

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Publication number Priority date Publication date Assignee Title
JPS59182541A (ja) * 1983-04-01 1984-10-17 Hitachi Ltd 半導体装置の製造方法
US5677244A (en) * 1996-05-20 1997-10-14 Motorola, Inc. Method of alloying an interconnect structure with copper
US5885856A (en) * 1996-08-21 1999-03-23 Motorola, Inc. Integrated circuit having a dummy structure and method of making
US6017437A (en) * 1997-08-22 2000-01-25 Cutek Research, Inc. Process chamber and method for depositing and/or removing material on a substrate
US6309956B1 (en) * 1997-09-30 2001-10-30 Intel Corporation Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
US6052375A (en) * 1997-11-26 2000-04-18 International Business Machines Corporation High speed internetworking traffic scaler and shaper
TW396524B (en) * 1998-06-26 2000-07-01 United Microelectronics Corp A method for fabricating dual damascene
US6395152B1 (en) * 1998-07-09 2002-05-28 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US6232231B1 (en) 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6709565B2 (en) * 1998-10-26 2004-03-23 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
CN1264162A (zh) * 1999-02-13 2000-08-23 国际商业机器公司 用于铝化学抛光的虚拟图形
US6259115B1 (en) * 1999-03-04 2001-07-10 Advanced Micro Devices, Inc. Dummy patterning for semiconductor manufacturing processes
US6239023B1 (en) * 1999-05-27 2001-05-29 Taiwan Semiconductor Manufacturing Company Method to reduce the damages of copper lines
US6459156B1 (en) * 1999-12-22 2002-10-01 Motorola, Inc. Semiconductor device, a process for a semiconductor device, and a process for making a masking database
JP2002158278A (ja) * 2000-11-20 2002-05-31 Hitachi Ltd 半導体装置およびその製造方法ならびに設計方法
US6486066B2 (en) * 2001-02-02 2002-11-26 Matrix Semiconductor, Inc. Method of generating integrated circuit feature layout for improved chemical mechanical polishing
US6852630B2 (en) * 2001-04-23 2005-02-08 Asm Nutool, Inc. Electroetching process and system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI382797B (zh) * 2009-04-16 2013-01-11 三星電機公司 溝槽基板及其製法
TWI852347B (zh) * 2022-04-13 2024-08-11 台灣積體電路製造股份有限公司 積體電路封裝及其形成方法

Also Published As

Publication number Publication date
KR101055564B1 (ko) 2011-08-08
CN1547763A (zh) 2004-11-17
EP1419523A4 (en) 2007-12-19
CA2456301A1 (en) 2003-03-06
KR20040027990A (ko) 2004-04-01
WO2003019641A1 (en) 2003-03-06
JP2005501412A (ja) 2005-01-13
CN100524644C (zh) 2009-08-05
US20040253810A1 (en) 2004-12-16
EP1419523A1 (en) 2004-05-19

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MM4A Annulment or lapse of patent due to non-payment of fees