經濟部中央標準局貝工消費合作社印製 Λ7 ________^___ 五、發明説明（1) 發明技術箱媸 本發明係關於製造銅質連接線的方法，而更確切地説， 係有關於同時利用物理氣相沈積法（PVD)和化學氣相沈積法 (CVD)在渠道（trench)及/或金屬層間的介層（\%)(或在半導體 基禮和第一金屬層間的觸體，Contact)之中成長具強（I! ι)_織 構之銅的方法。 發明背景 電子製品有愈來愈小、更爲便宜、而且功能更強的趨 勢’因而加快了積體電路的微縮，也因此提升了積體電路 基體封裝密度的需求。對於高密度積體電路的需求是要在 裝置之間和各層之間的内接通路儘可能地小。因此，多重 金屬層次逐漸地變成ULSI電路裡製造高性能積體電路的主 流程序，此外，在減低介層（或觸體）互連線路與導線之寬 度方面的研究亦持續不墜。互連線路之傳導係數會随其表 面積減小而降低，所以會具有高電阻係數並進而導致嚴重 的阻容時間延遲（RC delay)，更會進一步造成不可靠的電壓 位準，以及在積體電路裡的元件之間冗長的訊號耽搁等問 題。 因此’不斷尋找新的金屬材料以滿足縮減阻容時間延 遲、改良電致遷移（electromigration，EM)之阻抗性，並允許使 用較高的驅動電流等需求係十分地急迫。但因爲普遍在積 體電路中所使用的鋁金屬線已經是一種良好的導體，所以 在電阻値上可得到的進步甚爲有限。銅，銀，金是僅存的 三個比鋁具有較高導電率的已知金屬。而在三者之中，由 P:VPTS\LAL\54731SP.D〇a LAL _ 4 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚) ----. -- - -- ^(v (請先閱讀背面之注意事項再填寫本頁)Printed by the Central Standards Bureau, Ministry of Economic Affairs, Shellfish Consumer Cooperative Λ7 ________ ^ ___ V. Description of the Invention (1) Invention Box The invention relates to a method for manufacturing copper connecting wires, and more specifically, to the simultaneous use of physics Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD) interposer (\%) between trench and / or metal layer (or contact between semiconductor substrate and first metal layer, Contact) Growing in the strong (I!) _ Texture of the copper method. BACKGROUND OF THE INVENTION Electronic products tend to be smaller, cheaper, and more powerful ', thus accelerating the miniaturization of integrated circuits and therefore increasing the demand for the packaging density of integrated circuits. The demand for high-density integrated circuits is to make the internal connections between devices and layers as small as possible. Therefore, the multi-metal layer has gradually become the main flow procedure for manufacturing high-performance integrated circuits in ULSI circuits. In addition, research on reducing the width of interlayer (or contact) interconnect lines and wires has continued. The conductivity of the interconnect will decrease as its surface area decreases, so it will have a high resistivity and cause serious RC delay, which will further cause unreliable voltage levels, and Problems such as lengthy signal delays between components in the circuit. Therefore, it is extremely urgent to continuously seek new metal materials to meet the requirements of reducing the resistance time delay, improving the resistance of electromigration (EM), and allowing the use of higher driving currents. However, because the aluminum metal wire commonly used in integrated circuits is already a good conductor, the progress that can be made in resistance 値 is very limited. Copper, silver and gold are the only three known metals with higher electrical conductivity than aluminum. Among the three, P: VPTS \ LAL \ 54731SP.D〇a LAL _ 4-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297). ----.--- ^ (v (Please read the notes on the back before filling this page)
、1T '發明説明（ 於銅的低電阻係數和優越的電致遷移阻抗性. :赫以減小電路中導線和介層(或觸體) ： 中最自然r選擇。近來，銅的金屬化製程已經得到= /王意並且疋到目前爲止受到最多研究之銘的替代。 然而在積體電路製程當中已經有—些與銅的使： 問題出現。銅會冷染用於積體電路製程中的許多材料= 以-定要小心防止銅的遷移。已有多種不同的方法 來解決銅在積體電路材料之内擴散的問題出 特別是对火金屬，已經被建議用來當作障蔽層=的 擴散。鶴、1目、和氮化鈦_可能是適於當作對銅擴散障 蔽層之耐火金屬的實例。然而，在建構互連線路時，、㈣ 這些屏蔽材料的附著性也是積體電路製程中的—大問題。 另-方面’當積體電路設計的尺寸變小時，介層（或觸 體）的大小也因此縮小，而且介層（或觸體）裡的電流密度 可能會像在渠道之金屬導體中一樣地高，且有時甚至更 高，因此電致遷移不但會在導線中發生，而且也可能會在 觸體和介層中出現。Tsuchiya等人曾於「使用原位化學氣相 π /絮法之超低電阻直接接點銅介層技術」（1997 研討會 技術文摘中之技術論文第59至60頁）中揭示一種於二銅層之 間形成雙重金屬鑲嵌式（dual damascene)的連接法。此連接是 穿過一介電層到其下的銅層而形成。對於雙重金屬鑲嵌式 的連接法而言，由於寬高比（aspect ratio)較一般的介層（或觸 體）更大，因而附著性與電致遷移的問題，將更顯著。 所以，附著性與電致遷移兩者都是在ULSI製程中所必須 P:\PTSU_AU54731SP.DOC' LAL 5 本紙張尺度逋用中國國家樣华（CNS ) M規格（210x297公银) 經濟部中央榡準局員工消費合作社印裝 Λ7 、-、______ B7 五、發明説明（3) … ^--- 解決的問題。爲了要沈積銅於障蔽層之上，工業界正有多 種不同的氣相沈積技術在發展當中。雖然物理氣相沈積， 例如離子化金屬電漿（Ionized Metal Plasma, IMP)，可於沈積表面 上產生比較好的織構成長性質，但是當所選之積體電路區 域的形體變得愈來愈小時，以離子化金屬電漿製程於渠道 中或進入介層（或觸體）之内沈積金屬將相當地不容易且會 造成不良的步階覆蓋。不幸地是，因爲在介層（或觸體）側 壁上銅薄膜的不良步階覆處會形成通量的發散而導致電致 遷移，所以利用濺鍍的物理氣相沈積充填介層（或觸體）凹 洞或狹窄的渠道變得不實際。做爲另一個選擇，化學氣相 沈積法（CVD)能形成良好的等形沈積，因而可得到較好的 步階覆蓋性；且銅能較快速地被化學氣相沈積法所沈積。 然而，化學氣相沈積法難以沈積具有優良的電流密度應力 抵抗性之具（111)-群集取向的銅，故於日益縮小尺寸之介層 (或觸體）和金屬線内，易於因高電流密度而導致電致遷 移0 D. Manger等人在一篇對「在ULSI金屬化過程中微觀結構 對單價銅化學氣相沈積法的影響」的檢閱中（第14屆國際 VLSI多層内接會議研討會，1997，p 107)指出鋁銅合金的微 觀結構已證明會因電致遷移和熱應力孔洞化之影響而降低 其可靠度；在純銅的金屬化過程中也觀察到了類似的結 果。其中更指出一（111)-織構與電致遷移壽命間相互依存 的關係，甚至因具有此（111)-織構而使其使用壽命增加了 四倍之多。而以化學氣相沈積法所沈積之銅一般得到的是 P:\PTS\LAL\54731SP DOa LAL - 6 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210χ297公浼） (請先閱讀背面之注意事項再填寫本頁)1T 'invention description (low copper resistivity and superior electromigration resistance .: to reduce the wire and interlayer (or contact) in the circuit: the most natural r choice. Recently, copper metallization The manufacturing process has been replaced by = / Wang Yi and has been replaced by the most studied research so far. However, there are already some in the integrated circuit manufacturing process: some problems with copper: the problem arises. Copper will be cold-stained and used in the integrated circuit manufacturing process. Many materials = must be careful to prevent copper migration. There are many different ways to solve the problem of copper diffusion in integrated circuit materials, especially for fire metals, which have been suggested as barrier layers = He, 1 mesh, and titanium nitride may be examples of refractory metals that are suitable as barriers to copper diffusion. However, when constructing interconnects, the adhesion of these shielding materials is also integrated circuits The big problem in the manufacturing process. On the other hand, when the size of the integrated circuit design becomes smaller, the size of the interposer (or contact) is also reduced, and the current density in the interposer (or contact) may be like Channel Metal Guide As high as medium, and sometimes even higher, electromigration occurs not only in the wires, but also in the contacts and interlayers. Tsuchiya et al. "Ultra-low-resistance direct-contact copper interposer technology by flocculation" (Technical Papers in Technical Digest of the 1997 Symposium, pages 59 to 60) discloses a dual metal damascene connection between two copper layers. This connection is formed by passing through a dielectric layer to the copper layer below it. For the dual metal damascene connection method, the aspect ratio is more than that of a general dielectric layer (or contact). Large, so the problems of adhesion and electromigration will be more significant. Therefore, both adhesion and electromigration are necessary in the ULSI process. P: \ PTSU_AU54731SP.DOC 'LAL 5 This paper uses China as the standard. Sample China (CNS) M specification (210x297 public silver) Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs Λ7,-, ______ B7 V. Description of the invention (3) ... ^ --- The problem to be solved. In order to deposit copper on Above the barrier layer, how much industry is Different vapor deposition technologies are under development. Although physical vapor deposition, such as ionized metal plasma (Ionized Metal Plasma, IMP), can produce good texture long properties on the deposition surface, but when selected The shape of the integrated circuit area is getting smaller and smaller, and it is not easy to deposit metal in the channel or into the interlayer (or contact body) by the process of ionizing metal plasma, and it will cause poor step coverage. Unfortunately, because of the formation of flux divergence at the poor step coverage of the copper thin film on the sidewall of the interposer (or contact), electromigration is caused, so the sputtered physical vapor deposition is used to fill the interposer (or contact). Body) dimples or narrow channels become impractical. As another option, the chemical vapor deposition (CVD) method can form a good isomorphic deposition, so that better step coverage can be obtained; and copper can be deposited more quickly by the chemical vapor deposition method. However, chemical vapor deposition is difficult to deposit copper with (111) -cluster orientation, which has excellent current density stress resistance. Therefore, it is easy to cause high currents in interlayers (or contacts) and metal wires that are shrinking in size. Density induced electromigration. 0 D. Manger et al. In a review of "Effects of Microstructure on Monovalent Copper Chemical Vapor Deposition during ULSI Metallization" (Discussion at the 14th International VLSI Multilayer Interconnection Conference (1997, p 107) pointed out that the microstructure of aluminum-copper alloys has been shown to reduce its reliability due to the effects of electromigration and thermal stress cavitation; similar results have been observed during the metallization of pure copper. It also points out that the interdependence between a (111) -texture and the electromigration life, even with this (111) -texture, has increased its service life by four times. The copper deposited by chemical vapor deposition is generally P: \ PTS \ LAL \ 54731SP DOa LAL-6-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 cm) (Please read the back first (Notes for filling in this page)
Λ 7 —__—_Β7 _ 五、發明説明（.4) (111)、（200)或是任意位向平面的織構。到現目前止，只有 分別以PVD法先沈積具（111)-織構的銅之晶種層，再於該晶 種層上用CVD法沈積之銅沈積層顯示出較明顯之（in)群集 取向。然而，這樣的方法不僅需要多加一個製程步驟，減 低了密集工具類型結構設計中的晶圓生產量，且所得之群 .集取向效果並不突出；再者，以PVD法得到之銅晶種層其 步階覆蓋性不良，不僅會造成之後的CVD製程上的障礙， 亦存有潛在性電致遷移上的問題，因此並不適用於微小尺 寸之銅質連接線的製造。 综上可知，目前業界需要的是一種可於渠道及/或介層 (或觸體）中之障蔽層上形成具（111)-織構之良好步階覆蓋 性的銅連接線的方法，以解決金屬線製程中附著性及電致 遷移等問題。 發明概述 本發明的目的是提供於渠道及/或介層（或觸體）的側壁 和底部具有良好步階覆蓋性以及強（m)·織構之銅連接線的 製造方法。 經濟部中央橾準局貝工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) Λ 本發明之方法不僅可提供兼具強（111)_織構及良好步階 覆蓋性的銅連接線’且不增加製程步驟，同時更能縮短製 程時間。 • J— 本發明的技術特點包括： 1 ·在未破眞空的條件下，交錯使用物理氣相沈積（PVD)法 (例如，離子化金屬電漿）及化學氣相沈積（CVD)法，以同 時沉積銅層作爲晶種層，來取代單獨使用離子化金屬電漿 P：\PTS\LAL\54731SP,D〇a LAL - 7 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公赴) '— Λ7 Λ7 經濟部中央標準局員工消費合作社印裝 B7 五、發明説明（5) 或化學氣相沈積法所形成之銅晶種層；藉此方法可同時獲 致強（111)-銅織構，且於側壁和底部步階上得到良好的覆蓋 層，此法在寬高比日益增加的積體電路上更顯其重要性。 2 .於上述具有良好步階覆蓋性的銅晶種層上，可藉電化 學沈積（Electrochemical Deposition, ECD)法填充銅，再以化學機 械式抛光法（Chemical Mechanical Polishing，CMP)做平坦化處理， 可得到較佳的晶相結構，有助於整個連接線路可靠度的維 持。 此外，由於ECD法可較PVD或CVD法更有效率地填充介層 (或觸體）及渠道，所以可縮短製程時間。 本發明之其它技術特點及技術内容可藉下述之實施例及 圖式作更充分地説明。 圖式之簡單説明 圖1至圖8係説明依據本發明在一積體電路（1C)之一絕緣層 中形成至少一個介層（或觸體），然後於其上方形成一條銅 導線之方法的步驟。 圖9至圖13是依據本發明製造積體電路中雙重金屬鑲嵌 式介層（或觸體）及渠道中之銅連接線的步驟。 代表符號説明 10 積體電路 12第一金屬層 14 第一障蔽層 16 第一層間介電層(或金屬間介電層） P:\PTS\LAL\54731SP.DOC\ LAL ~ 8 ~ 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210Χ 297公浼） ---------- (請先閱讀背面之注意事項再填寫本頁) 、\-° 經濟部中央標準局貝工消費合作社印裝 Λ7 B7 五、發明説明（’ 20 介層孔道 22 第一垂直侧壁表面 24 第一水平區域 26 第一頂面 28 第一光阻層 32 第二障蔽層 34 第一銅晶種層 40 介層 50 第二層間介電層(或金屬間介電層） 52 介層頂面 60 渠道 . 62 第二垂直侧壁表面 64 第二水平區域 66 第二頂面 68第二光阻層 69 第三水平區域 72 第三障蔽層 74 第二銅晶種層 80 銅導線 90 積體電路 92 第一金屬層 94 第一障蔽層 96 層間介電層 97 層間介電層第一厚度層 P:\PTS\LAL\54731SP.DOC\ LAL * 9 (請先閲讀背面之注意事項再填寫本頁) I飞裝--^*vΛ 7 —__—_ Β7 _ 5. Description of the invention (.4) (111), (200) or the texture of any orientation plane. Until now, only the seed layer of copper with (111) -texture has been deposited by the PVD method, and the copper deposited layer deposited by the CVD method on the seed layer has shown a more obvious (in) cluster. orientation. However, this method not only requires an additional process step, reduces the wafer production volume in the dense tool type structure design, and the obtained cluster orientation effect is not outstanding; further, the copper seed layer obtained by the PVD method Its poor step coverage not only causes obstacles in the subsequent CVD process, but also has potential electromigration problems. Therefore, it is not suitable for the manufacture of micro-sized copper connection wires. In summary, what the industry needs at present is a method that can form (111) -textured copper wire with good step coverage on the barrier layer in the channel and / or the interlayer (or contact body). Solve the problems of adhesion and electromigration during metal wire manufacturing. SUMMARY OF THE INVENTION The object of the present invention is to provide a method for manufacturing a copper connecting wire with good step coverage and strong (m) · textured texture on the sidewalls and bottom of channels and / or interlayers (or contacts). Printed by the Central Labor Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (please read the notes on the back before filling this page) Λ The method of the present invention can not only provide copper with strong (111) _ texture and good step coverage The connection line 'does not increase the process steps, and at the same time, it can shorten the process time. • J— The technical features of the present invention include: 1 · Under unbroken conditions, the physical vapor deposition (PVD) method (eg, ionized metal plasma) and chemical vapor deposition (CVD) method are used alternately to At the same time, a copper layer is deposited as a seed layer instead of using an ionized metal plasma P: \ PTS \ LAL \ 54731SP, Doa LAL-7-This paper size applies to China National Standard (CNS) A4 (210X 297 mm) Go) '— Λ7 Λ7 Printing of B7 by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. The copper seed layer formed by the invention description (5) or chemical vapor deposition method; this method can also obtain strong (111) -copper Texture, and good coverage on the side and bottom steps. This method is more important in integrated circuits with increasing aspect ratios. 2. On the above copper seed layer with good step coverage, copper can be filled by electrochemical deposition (ECD) method, and then planarized by chemical mechanical polishing (CMP) A better crystal phase structure can be obtained, which helps maintain the reliability of the entire connection line. In addition, since the ECD method can fill the interlayer (or contact) and channels more efficiently than the PVD or CVD methods, the process time can be shortened. Other technical features and technical contents of the present invention can be more fully explained by the following embodiments and drawings. Brief Description of the Drawings Figures 1 to 8 illustrate a method for forming at least one interlayer (or contact) in an insulating layer of an integrated circuit (1C) according to the present invention, and then forming a copper wire thereon. step. 9 to 13 are steps for manufacturing a double metal damascene interposer (or contact) in a integrated circuit and a copper connection line in a channel according to the present invention. Description of representative symbols 10 Integrated circuit 12 First metal layer 14 First barrier layer 16 First interlayer dielectric layer (or intermetal dielectric layer) P: \ PTS \ LAL \ 54731SP.DOC \ LAL ~ 8 ~ This paper Standards are applicable to China National Standards (CNS) Λ4 specifications (210 × 297 mm) ---------- (Please read the precautions on the back before filling this page), \-° Shellfish, Central Standards Bureau, Ministry of Economic Affairs Consumption cooperative printing Λ7 B7 V. Description of the invention ('20 vias 22 first vertical sidewall surface 24 first horizontal area 26 first top surface 28 first photoresist layer 32 second barrier layer 34 first copper seed Layer 40 dielectric layer 50 second interlayer dielectric layer (or intermetallic dielectric layer) 52 top surface of the interlayer 60 channels. 62 second vertical sidewall surface 64 second horizontal area 66 second top surface 68 second photoresist layer 69 Third horizontal area 72 Third barrier layer 74 Second copper seed layer 80 Copper wire 90 Integrated circuit 92 First metal layer 94 First barrier layer 96 Interlayer dielectric layer 97 Interlayer dielectric layer First thickness layer P: \ PTS \ LAL \ 54731SP.DOC \ LAL * 9 (Please read the precautions on the back before filling in this page) I Fly Pack-^ * v
、1T Λ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公f ) Λ7 B7 五、發明説明（7) 98 層間介電層第二厚度層 99 垂直侧壁表面 100水平表面 102渠道 104金屬鑲嵌式介層孔道 106垂直侧壁表面 108水平表面 112第二障蔽層 122銅晶種層 130銅導體 具體實施例説明 圖1至圖8是説明在一積體電路（1C)之一絕緣層中形成至少 一個介層（或觸體），然後於其上方形成一條銅導線的方法 之步驟。圖1是一積體電路10的部分剖面圖，其中包括第 一金屬層12、第一障蔽層14、以及第一層間介電層（ILD) 或金屬間介電層（IMD) 1 6。第一 ILD( IMD)層16的平面被指 定爲水平只是爲了清楚描述發明，所以可以是任意的。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 於圖2中，一介層孔道20被形成，其穿過第一 ILD(IMD)層 16中所選定的區域而形成，使得第一 ILD(IMD)層16中之第 一垂直側壁表面22以及第一金屬層12上所選定之第一水平 區域24暴露出來。基本上，介層孔道20的形成是藉由沈積 一層第一光阻層28於第一 ILD(IMD)層16之第一頂面26上， 並定義其圖案以決定介層孔道20將於何處形成。之後再以 P:\PTS\LAL\54731SP DOC\ LAL - 1 0 ~ 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 Λ7 B? 五、發明説明（8). 電漿蚀刻第一 ILD (IMD)層16以於所選定之區域形成介層孔道 20。在介層孔道20形成之後，第一光阻層28即被移除。 接著，於圖3中，藉由沈積屏蔽材料於整個暴露的表面 上，一第二障蔽層32被形成，其所覆蓋的表面包括第一 ILD (IMD)層16之第一頂面26、第一垂直側壁表面22、以及第 一金屬層12上所選定之第一水平區域24。緊接著，於第二 障蔽層32上，形成一第一銅晶種層34;此銅晶種層是在未 破眞空的條件下，交錯地運用物理氣相沈積（PVD)法（如離 子化金屬電漿（IMP)法）以及化學氣相沈積（CVD)法同時地（in-situ)沈積於第二障蔽層32之上；其中之交錯方式係需先使 用PVD法。如此形成之第一銅晶種層34可同時具有強（111) -織構及良好的步階覆蓋性。 隨後，於圖4，中介層孔道20被填充銅以形成介層40， 該填充係用電化學沉積（Electrochemical Deposition, ECD)來處 理，並使介層40經由第一金屬層12上所選定之第一水平區 域24，連接到該第一金屬層12之上。然後，可使用化學機 械式抛光法（CMP)平坦化介層40之表面，並除去在第一 ILD (IMD)層20之第一頂面26上的銅及障蔽層，使得此第一 頂面26暴露出來並且平坦化。由於已形成具有強（111)-織 構及良好步階覆蓋性的銅晶種層32，填充入介層孔道20之 中所形成的銅介層也具備有強（111)-織構和良好的步階覆蓋 性。織構可以X光繞射（XRD)法來對所沉積之銅薄膜加以研 究，而整體的粒度大小則可用XRD波峰變寬分析來決定。 根據X光繞射分析結果，以本發明所揭示之方法得到的銅 P:\PTS\LAL\S4731 SP D0C\ LAL - 1 1 - 本紙張尺度適用中國國家標準（CNS ) Ad規輅（2丨OX”7公釐） (請先閱讀背面之注意事項再填寫本頁)、 1T Λ This paper size applies Chinese National Standard (CNS) A4 specification (210 × 297 male f) Λ7 B7 V. Description of the invention (7) 98 Interlayer dielectric layer Second thickness layer 99 Vertical sidewall surface 100 Horizontal surface 102 Channel 104 Metal Mosaic via 106 vertical side wall surface 108 horizontal surface 112 second barrier layer 122 copper seed layer 130 copper conductor Description of specific embodiments FIG. 1 to FIG. 8 illustrate an insulating layer in a integrated circuit (1C) Steps of a method of forming at least one interposer (or contact) and then forming a copper wire thereon. FIG. 1 is a partial cross-sectional view of an integrated circuit 10 including a first metal layer 12, a first barrier layer 14, and a first interlayer dielectric layer (ILD) or an intermetal dielectric layer (IMD) 16. The plane of the first ILD (IMD) layer 16 is designated as horizontal only for clearly describing the invention, so it can be arbitrary. Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling this page). In Figure 2, a meso-channel 20 is formed and passes through the selected one in the first ILD (IMD) layer 16. The first vertical sidewall surface 22 in the first ILD (IMD) layer 16 and the selected first horizontal region 24 on the first metal layer 12 are exposed. Basically, the vias 20 are formed by depositing a first photoresist layer 28 on the first top surface 26 of the first ILD (IMD) layer 16 and defining its pattern to determine where the vias 20 will be located.处 形成。 Office formation. After that, P: \ PTS \ LAL \ 54731SP DOC \ LAL-1 0 ~ This paper size applies the Chinese National Standard (CNS > A4 size (210X297 mm)) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B? 5 Explanation of the invention (8). The first ILD (IMD) layer 16 is etched by plasma to form a via 20 in a selected area. After the via 20 is formed, the first photoresist layer 28 is removed. Next In FIG. 3, by depositing a shielding material on the entire exposed surface, a second barrier layer 32 is formed, and the covered surface includes the first top surface 26, the first ILD (IMD) layer 16, and the first The vertical sidewall surface 22 and the selected first horizontal region 24 on the first metal layer 12. Next, a first copper seed layer 34 is formed on the second barrier layer 32; the copper seed layer is Under broken conditions, physical vapor deposition (PVD) methods (such as ionized metal plasma (IMP) method) and chemical vapor deposition (CVD) methods are used to deposit in-situ on the second barrier staggered. Layer 32; the interleaving method requires PVD first. The first copper seed layer 34 thus formed At the same time, it has strong (111) -texture and good step coverage. Subsequently, as shown in FIG. 4, the interposer channel 20 is filled with copper to form an interlayer 40, and the filling is performed by Electrochemical Deposition (ECD). Processing, and the interposer 40 is connected to the first metal layer 12 through the first horizontal region 24 selected on the first metal layer 12. Then, the interposer can be planarized using a chemical mechanical polishing method (CMP). 40 and remove the copper and barrier layer on the first top surface 26 of the first ILD (IMD) layer 20, so that this first top surface 26 is exposed and flattened. Since it has been formed with a strong (111)- The copper seed layer 32 with texture and good step coverage, and the copper interlayer formed by filling in the interlayer via 20 also has strong (111) -texture and good step coverage. The texture can be The X-ray diffraction (XRD) method is used to study the deposited copper film, and the overall particle size can be determined by XRD peak broadening analysis. According to the X-ray diffraction analysis results, obtained by the method disclosed in the present invention Copper P: \ PTS \ LAL \ S4731 SP D0C \ LAL-1 1-This paper size applies National Standards country (CNS) Ad regulation chariot (2 Shu OX "7 mm) (Please read the back of the precautions to fill out this page)
、1T 浓 經濟部中央標準局員工消費合作社印製 Λ7 B7 五、發明説明（.3 僅呈現單一（111)主峰，其餘平面族之訊號強度均低於背景 値而可忽略不計。又因爲以本發明所沈積之晶種層具良好 的步階覆蓋性，所以接著以電化沈積所得之銅在化學機械 式抛光後其晶粒結構（大小、形狀、分佈）良好，有助於日 後於實際應用時的可靠度。 障蔽層材料可從包括鈦（Ti)，氮化鈦（TiN)，鈦/氮化钦 (Ti/TiN)，钽(Ta)，氮化钽(TaN)，钽/氮化钽(Ta/TaN)和氮化鎢(WN)等 耐火金屬和耐火金屬化合物中選擇。一般説來，介層（或 觸體）的的材料是鎢、鋁、鋁-銅合金或是銅等傳導性材 料。當然，如果有用到銅，則於介層（或觸體）表面上需要 額外的障蔽層。 於圖5中，沈積一第二ILD (IMD)層50於第一 ILD (IMD)層頂 面26之上；而此第二ILD (IMD )層下方至少包含一個介層40 之頂面52。 接著，如圖6中所示，一渠道60被形成，其穿過第二 ILD (IMD)層50中所選定的區域，使得第二ILD (IMD)層50中 之第二垂直侧壁表面62及第一 ILD (IMD)層16上所選定之第 二水平區域64暴露出來。此水平區域64至少包括一個介層 (或觸體）之頂面52。基本上，渠道60的形成是藉由沈積一 第二光阻層68於第二頂面66之上，並定義其圖案來決定渠 道60將於何處形成。之後再以電漿蝕刻第二ILD (IMD)層， 以於所選定之區域上形成渠道60。在渠道60形成之後，第 二光阻68即被移除。 在圖7之中，藉由沈積屏蔽材料於整個暴露的表面上， PAPTS\LAL\54731SP.D〇a LAL - 12 - 本紙張尺度通用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁), 1T printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. Description of the invention (.3 shows only a single (111) main peak, and the signal strength of the other plane families is lower than the background, and can be ignored. Also because of this The seed layer deposited by the invention has good step coverage, so the copper obtained by electrodeposition after chemical mechanical polishing has a good grain structure (size, shape, distribution), which is helpful for future practical applications. The reliability of the barrier layer material can include titanium (Ti), titanium nitride (TiN), titanium / nitride (Ti / TiN), tantalum (Ta), tantalum nitride (TaN), tantalum / tantalum nitride (Ta / TaN) and tungsten nitride (WN) and other refractory metals and refractory metal compounds. Generally speaking, the material of the interlayer (or contact) is tungsten, aluminum, aluminum-copper alloy or copper. Of course, if copper is used, an additional barrier layer is required on the surface of the interposer (or contact). In FIG. 5, a second ILD (IMD) layer 50 is deposited on the first ILD (IMD) layer. Above the top surface 26; and under the second ILD (IMD) layer, at least one top surface 52 of the interlayer 40 is included. As shown in FIG. 6, a channel 60 is formed that passes through a selected area in the second ILD (IMD) layer 50 such that the second vertical sidewall surface 62 and A selected second horizontal area 64 on the first ILD (IMD) layer 16 is exposed. This horizontal area 64 includes at least a top surface 52 of an interposer (or contact body). Basically, the channel 60 is formed by deposition A second photoresist layer 68 is on the second top surface 66 and defines its pattern to determine where the channel 60 will be formed. Then, the second ILD (IMD) layer is etched by plasma to select the selected area A channel 60 is formed on the top. After the channel 60 is formed, the second photoresist 68 is removed. In FIG. 7, by depositing a shielding material on the entire exposed surface, PAPTS \ LAL \ 54731SP.D〇a LAL- 12-The paper size is in accordance with the Chinese National Standard (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling this page)
經濟部中央標準局貝工消费合作社印装 Λ7 B7 五、發明.説明（巧 以形成一第三障蔽層72，其所覆蓋的表面包括有第二 ILD (IMD)層50上方之第二頂面66、第二垂直側壁表面62、以 及第一 ILD (IMD)層16上所選定之第二水平區域64»緊接 著，於第三障蔽層72上，形成一第二銅晶種層74 ;此銅晶 種層同樣是在未破眞空的條件下，交錯地運用離子化金屬 電漿（IMP)法以及化學氣相沈積（CVD)法同時地（in-situ)沈積於 第三障蔽層72之上。如此形成之第二銅晶種層74可同時具 有強（111)-織構及良好的步階覆蓋性。 随後’於圖8中渠道60被填充形成銅導線80，該填充係 用電化學沉積（Electrochemical Deposition, ECD)來處理’並使銅 導線80經由第一 I L D ( I M D )層16上所選定之第二水平區域 64，連接到介層40之頂面52之上。然後，使用化學機械式 抛光法（CMP)平坦化渠道60之表面，並除去在第二ILD (IMD) 層5〇之頂面66上的銅及障蔽層，使得此第二頂面66暴露出 來並且平坦化。若渠道中之金屬導線與介層材料同屬銅質 材料’則介層頂面52上之第三障蔽層7 2可以移除以增加導 電性。由於已形成具有強（111) _織構及良好步階覆蓋性的 第二銅晶種層74 ’填充入渠道60之中所形成的銅導線也具 備有強（111)-織構和良好的步階覆蓋性。織構可以X光繞射 (XRD)法來對所沉積銅薄膜加以研究，而整體的粒度大小則 可用XRD波峰變寬分析來決定。根據X光繞射分析結果， 以本發明所揭示之方法得到的銅僅呈現單一（111)主峰，其 餘平面族之訊號強度均低於背景値而可忽略不計。又因爲 以本發明所沈積之晶種層具良好的步階覆蓋性，所以接著Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Λ7 B7 V. Invention. Explanation (It is a coincidence to form a third barrier layer 72, and the surface covered by it includes a second top surface above the second ILD (IMD) layer 50 66. The second vertical sidewall surface 62 and the second horizontal region 64 »selected on the first ILD (IMD) layer 16 are then formed on the third barrier layer 72 to form a second copper seed layer 74; The copper seed layer is also deposited in-situ on the third barrier layer 72 simultaneously using the ionized metal plasma (IMP) method and the chemical vapor deposition (CVD) method under the condition that the copper seed layer is not broken. The second copper seed layer 74 thus formed may have both strong (111) -texture and good step coverage. Subsequently, the channel 60 in FIG. 8 is filled to form a copper wire 80, which is used for filling. Electrochemical Deposition (ECD) is used to process the copper wires 80 through the second horizontal region 64 selected on the first ILD (IMD) layer 16 to the top surface 52 of the interlayer 40. Then, The surface of the channel 60 is planarized using a chemical mechanical polishing method (CMP), and The copper and barrier layer on the top surface 66 of the second ILD (IMD) layer 50 make this second top surface 66 exposed and flattened. If the metal wires in the channel and the interlayer material are copper materials, then the medium The third barrier layer 72 on the top surface 52 of the layer can be removed to increase the conductivity. Since a second copper seed layer 74 having a strong (111) texture and good step coverage has been formed, it is filled into the channel 60 The copper wire formed therein also has strong (111) -texture and good step coverage. The texture can be studied by X-ray diffraction (XRD) method on the deposited copper film, and the overall grain size It can be determined by XRD peak broadening analysis. According to the results of X-ray diffraction analysis, the copper obtained by the method disclosed in the present invention only presents a single (111) main peak, and the signal strength of the other plane families is lower than the background and can be ignored No. Because the seed layer deposited by the present invention has good step coverage,
P：\PTS\LAL\54731SPD〇a LAL 本紙張尺度賴巾關家縣（⑽…題（2lQx297公疫 -9 /ί^ (，請先閲讀背面之注意事項再填寫本頁)P ： \ PTS \ LAL \ 54731SPD〇a LAL The paper size is Laijia Guanguan County (⑽ ... question (2lQx297public epidemic -9 / ί ^, please read the precautions on the back before filling this page)
經濟部中央標準局員工消費合作社印製 Λ7 B? Λ、發明説明（1) 以電化沈積所得之銅在化學機械式抛光後其晶粒結構（大 小、形狀、分佈）良好，有助於日後於實際應用時的可靠 度。 第一 ILD(IMD)層16及/或第二ILD(IMD)層50之材料可由下列 中選出：氧化物（oxide)、氮化物（nitride)、低介電常數材料 (low-k materials)、氧氮化物（oxynitride)、以及上述任意二者或 二者以上之组合。 在雙重金屬鑲嵌式.製程中，介層（或觸體）和渠道係藉使 用二個微影和一個蝕刻步驟而定義出來，而介層孔係與金 屬線渠道在相同的步骤中被填滿。雙重金屬鑲嵌式製程減 少障蔽層與銅層沈積處理步驟的數目從二減少爲一，因而 顯著地減少了製程步驟。雙重金屬鑲嵌式之一特別的利益 是介層插頭的材料相同於金屬線的材料而且介層因電致遷 移而失效的風險被減少。 圖9至圖13是説明在積體電路裡形成雙重金屬鑲嵌式互 連方法的步驟。圖9是積體電路90的一個部分剖面圖，包 含一水平第一金屬（或金屬珍化物，silicide)層92，一第一障 蔽層94覆蓋於該第一金屬層92之上，以及一 ILD(IMD)層96 覆蓋於該第一障蔽層94之上。用「水平」一詞僅是爲了清 楚表達，所以並不表示該表面必須完全平坦。該ILD(IMD) 層66具有第一厚度層97和覆蓋於第一厚度層97上之第二厚 度層68。 積體電路90中包含一金屬鑲嵌式渠道102，其是穿過 ILD(IMD)層96之第二厚度層98中所選區域而形成，使 P:\PTS\LAL\S4731SPOOa LAL -14- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公t ) (請先閱讀背面之注意事項再填寫本頁) 衣 ，1Τ 經濟部中央標準局貝工消費合作社印裝 Λ7 一^—____ B? 五、發明説明（1弓 — ILD(IMD)層96之第二厚度層98中的垂直側壁表面99以及 ILD(IMD)層96之第一厚度層97上所選定的水平表面1〇〇暴 露出來。本發明於某些情況，例如當第一金屬層92不是銅 時，不包括第一障蔽層94。當第一金屬層92屬於不污染周 園基體區域的金屬時，不必需加入障蔽層94。當沒有第— 障蔽層94時’則構成第一金屬層92之材料可從鋁、鋁_銅合 金、鶴和金屬碎化物（silicide)之中選擇。 , 於圖10中，一金屬鑲嵌式介層1〇 4穿過ILd(IMD)層96之第 一厚度層97和第一障蔽層94上所選區域而形成，進而使 ILD(IMD)層96之第一厚度層97中之垂直側壁表面106及第一 金屬層92上所選水平區域1〇8暴露出來。 接著，於圖11中，形成一第二障蔽層112，其形成是沈 積障蔽材料於ILD(IMD)層96之第一厚度層97和第二厚度層 98的垂直侧壁表面和99以及於水平表面1 〇 8和水平表面 100之上。而第二障蔽層112通常是具傳導性的。 隨後’於圖1.2中，銅晶種層122係.交錯地以離子化金屬電 漿法和化學氣相沈積法在第二障蔽層112上等形地沈積。 金屬鑲嵌式介層104和渠道102現在具有了 一銅晶種層層 122 ’該銅晶種層具有強織構及良好的步階覆蓋性， 並已經爲在其上直接地電化學沉積（ECD)銅做好準備。 最後，於圖13中，將銅導體130充填於介層104和渠道1〇2 内’該填充可以ECD法實行，並和第一金屬層92上所選區 域108相連接。此後，可使用化學機械式抛光法（CMp)平坦 化渠道102之表面，並除去在所有在第二厚度層98上的銅 P:\PTSU-AL\54731SP.DOC\ LAL -15· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公' (請先閲讀背面之注意事項再填寫本頁) 衣· *?τ . Λ7 B7 五、發明説明（” 及障蔽層。填充入介層104和渠道102内所形成的金屬銅具 有強（111)-織構和良好步階覆蓋性。 在本發明中，第一障蔽層94是非傳導性的而第二障蔽層 112之材料可由傳導性材料中選出。傳導性障蔽層材料可 選自於由耐火材料和耐火金屬化合物所成的組，其中包括 鈦（Ti)，氮化鈦(TiN)，鈦/氮化鈦(Ti/TiN)，钽(Ta)，氮化钽(TaN)， 鉅/氮化钽(Ta/TaN)和氮化鎢（WN)。第一金屬層92之材料則可 從銘、銘-銅合金、銅、鶴和金屬珍化物（silicide)之中加以選 擇。 ILD(IMD)層96之材料可爲氧化物（oxide)、氮化物（nitride)、 低介電常數材料（low-k materials)、氧氮化物（oxynitride)、以及 上述任意二者或二者以上之組合。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之士仍可基於本發明之敎示及揭示而作種種不背離 本發明精神之替換及修飾；因此，本發明之保護範圍應不 限於實施例所揭示者，而應包括各種不背離本發明精神之 替換及修飾。 --------「裝-- (請先閲讀背面之注意事項再填寫本I) 、11 泉 經濟部中央標準局員工消費合作社印製 P:\PTS\LAL\54731SP DOC\ LAL 16 _ 本紙張尺度適用中國國家標準（〇奶）六4規格（210/297公浼）Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B? Λ, invention description (1) After chemical mechanical polishing of the copper obtained by electrodeposition, its grain structure (size, shape, distribution) is good, which will help in the future Reliability in practical applications. The material of the first ILD (IMD) layer 16 and / or the second ILD (IMD) layer 50 may be selected from the following: oxide, nitride, low-k materials, An oxynitride, and any two or more combinations thereof. In the dual metal damascene process, the interposer (or contact) and channel are defined by using two lithography and one etching step, and the via hole system and the metal line channel are filled in the same step. . The dual metal damascene process reduces the number of barrier and copper layer deposition processing steps from two to one, thereby significantly reducing the number of process steps. One particular benefit of the dual metal inlay is that the material of the dielectric plug is the same as that of the metal wires and the risk of dielectric failure due to electromigration is reduced. Figures 9 to 13 illustrate the steps of a method for forming a dual metal damascene interconnection in a integrated circuit. FIG. 9 is a partial cross-sectional view of the integrated circuit 90, including a horizontal first metal (or silicide) layer 92, a first barrier layer 94 covering the first metal layer 92, and an ILD (IMD) layer 96 covers the first barrier layer 94. The term "horizontal" is used for clarity and does not imply that the surface must be completely flat. The ILD (IMD) layer 66 has a first thickness layer 97 and a second thickness layer 68 covering the first thickness layer 97. The integrated circuit 90 includes a metal mosaic channel 102 formed through a selected area of the second thickness layer 98 of the ILD (IMD) layer 96, so that P: \ PTS \ LAL \ S4731SPOOa LAL -14- Paper size applies to Chinese National Standard (CNS) Α4 specification (210 × 297 g) (Please read the notes on the back before filling out this page) Clothing, 1T Printed by the Central Bureau of Standards of the Ministry of Economic Affairs Shellfish Consumer Cooperative Λ7 1 ^ —____ B V. Description of the Invention (1) The vertical sidewall surface 99 in the second thickness layer 98 of the ILD (IMD) layer 96 and the selected horizontal surface 100 on the first thickness layer 97 of the ILD (IMD) layer 96 are exposed. Come out. The present invention is in some cases, for example, when the first metal layer 92 is not copper, the first barrier layer 94 is not included. When the first metal layer 92 belongs to a metal that does not contaminate the substrate area of the surrounding garden, it is not necessary to add a barrier layer 94. When there is no first-barrier layer 94, the material constituting the first metal layer 92 may be selected from aluminum, aluminum-copper alloy, crane, and metal silicide. In FIG. 10, a metal inlay The interposer 104 passes through the first thickness layer 97 and the first barrier layer 94 of the ILd (IMD) layer 96 The selected area is formed, thereby exposing the vertical sidewall surface 106 in the first thickness layer 97 of the ILD (IMD) layer 96 and the selected horizontal area 108 on the first metal layer 92. Then, in FIG. 11, A second barrier layer 112 is formed, which is formed by depositing a barrier material on the vertical sidewall surfaces and 99 of the first thickness layer 97 and the second thickness layer 98 of the ILD (IMD) layer 96 and on the horizontal surface 108 and the horizontal surface. 100. The second barrier layer 112 is usually conductive. Subsequently, as shown in Figure 1.2, the copper seed layer 122 is 122. The second barrier is alternately formed by ionized metal plasma and chemical vapor deposition. Layer 112 is deposited isomorphically. The metal damascene interlayer 104 and channel 102 now have a copper seed layer 122 'The copper seed layer has strong texture and good step coverage, and has been Preparation of direct electrochemical deposition (ECD) copper on top. Finally, in FIG. 13, the copper conductor 130 is filled in the interlayer 104 and the channel 102. The filling can be performed by the ECD method and the first metal layer Selected areas on 92 are connected to 108. Thereafter, chemical mechanical polishing (CMp) can be used to level Surface of the channel 102 and remove all copper on the second thickness layer 98 P: \ PTSU-AL \ 54731SP.DOC \ LAL -15 · This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297) (Please read the precautions on the back before filling out this page) Clothing * * τ. Λ7 B7 V. Description of the invention ("and the barrier layer. The metal copper formed by filling into the interlayer 104 and the channel 102 has strong (111) -Texture and good step coverage. In the present invention, the first barrier layer 94 is non-conductive and the material of the second barrier layer 112 can be selected from conductive materials. The conductive barrier material can be selected from the group consisting of refractory materials and refractory metal compounds, including titanium (Ti), titanium nitride (TiN), titanium / titanium nitride (Ti / TiN), and tantalum (Ta). , Tantalum nitride (TaN), giant / tantalum nitride (Ta / TaN) and tungsten nitride (WN). The material of the first metal layer 92 may be selected from among inscriptions, inscription-copper alloys, copper, cranes, and metal silicides. The material of the ILD (IMD) layer 96 may be oxide, nitride, low-k materials, oxynitride, or any two or more of the above. Of combination. The technical content and technical features of the present invention have been disclosed as above. However, those skilled in the art can still make various substitutions and modifications without departing from the spirit of the present invention based on the disclosure and disclosure of the present invention; therefore, the scope of protection of the present invention should be It is not limited to those disclosed in the embodiments, but should include various substitutions and modifications without departing from the spirit of the present invention. -------- "Loading-(Please read the notes on the back before filling out this I), 11 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs P: \ PTS \ LAL \ 54731SP DOC \ LAL 16 _ This paper size applies to the Chinese National Standard (〇 奶) 6 4 specifications (210/297 cm)