JP2005501412A - 電解研磨法において金属の窪みを低減するダミー構造物 - Google Patents

電解研磨法において金属の窪みを低減するダミー構造物 Download PDF

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Publication number
JP2005501412A
JP2005501412A JP2003522995A JP2003522995A JP2005501412A JP 2005501412 A JP2005501412 A JP 2005501412A JP 2003522995 A JP2003522995 A JP 2003522995A JP 2003522995 A JP2003522995 A JP 2003522995A JP 2005501412 A JP2005501412 A JP 2005501412A
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JP
Japan
Prior art keywords
semiconductor structure
dummy structures
metal layer
dummy
structure according
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Pending
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JP2003522995A
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English (en)
Japanese (ja)
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JP2005501412A5 (https=
Inventor
ワン，フイ
イー，ペイハウアー
Original Assignee
エーシーエム リサーチ，インコーポレイティド
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Application filed by エーシーエム リサーチ，インコーポレイティド filed Critical エーシーエム リサーチ，インコーポレイティド
Publication of JP2005501412A publication Critical patent/JP2005501412A/ja
Publication of JP2005501412A5 publication Critical patent/JP2005501412A5/ja
Pending legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2003522995A 2001-08-23 2002-08-16 電解研磨法において金属の窪みを低減するダミー構造物 Pending JP2005501412A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31461701P 2001-08-23 2001-08-23
PCT/US2002/026309 WO2003019641A1 (en) 2001-08-23 2002-08-16 Dummy structures to reduce metal recess in electropolishing process

Publications (2)

Publication Number Publication Date
JP2005501412A true JP2005501412A (ja) 2005-01-13
JP2005501412A5 JP2005501412A5 (https=) 2006-01-05

Family

ID=23220680

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003522995A Pending JP2005501412A (ja) 2001-08-23 2002-08-16 電解研磨法において金属の窪みを低減するダミー構造物

Country Status (8)

Country Link
US (1) US20040253810A1 (https=)
EP (1) EP1419523A4 (https=)
JP (1) JP2005501412A (https=)
KR (1) KR101055564B1 (https=)
CN (1) CN100524644C (https=)
CA (1) CA2456301A1 (https=)
TW (1) TW573324B (https=)
WO (1) WO2003019641A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010219449A (ja) * 2009-03-18 2010-09-30 Nuflare Technology Inc 荷電粒子ビーム描画方法、荷電粒子ビーム描画装置及びプログラム
JP2023183338A (ja) * 2022-06-15 2023-12-27 日本メクトロン株式会社 導電パターン形成方法

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EP1505653A1 (en) * 2003-08-04 2005-02-09 STMicroelectronics S.r.l. Layout method for dummy structures and corresponding integrated circuit
US20050045993A1 (en) * 2003-08-28 2005-03-03 Sanyo Electric Co., Ltd. Semiconductor device with concave patterns in dielectric film and manufacturing method thereof
US7074710B2 (en) * 2004-11-03 2006-07-11 Lsi Logic Corporation Method of wafer patterning for reducing edge exclusion zone
KR101067207B1 (ko) 2009-04-16 2011-09-22 삼성전기주식회사 트렌치 기판 및 그 제조방법
US20130075268A1 (en) * 2011-09-28 2013-03-28 Micron Technology, Inc. Methods of Forming Through-Substrate Vias
CN103692293B (zh) * 2012-09-27 2018-01-16 盛美半导体设备（上海）有限公司 无应力抛光装置及抛光方法
US8627243B1 (en) * 2012-10-12 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for optimizing conductor patterns for ECP and CMP in semiconductor processing
WO2014082197A1 (en) * 2012-11-27 2014-06-05 Acm Research (Shanghai) Inc. Method for forming interconnection structures
WO2019066792A1 (en) * 2017-09-27 2019-04-04 Intel Corporation INTEGRATED CIRCUIT COMPONENTS WITH FACIAL STRUCTURES
US20230335534A1 (en) * 2022-04-13 2023-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated Circuit Packages and Methods of Forming the Same

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JPS59182541A (ja) * 1983-04-01 1984-10-17 Hitachi Ltd 半導体装置の製造方法
US5677244A (en) * 1996-05-20 1997-10-14 Motorola, Inc. Method of alloying an interconnect structure with copper
US5885856A (en) * 1996-08-21 1999-03-23 Motorola, Inc. Integrated circuit having a dummy structure and method of making
US6017437A (en) * 1997-08-22 2000-01-25 Cutek Research, Inc. Process chamber and method for depositing and/or removing material on a substrate
US6309956B1 (en) * 1997-09-30 2001-10-30 Intel Corporation Fabricating low K dielectric interconnect systems by using dummy structures to enhance process
US6052375A (en) * 1997-11-26 2000-04-18 International Business Machines Corporation High speed internetworking traffic scaler and shaper
TW396524B (en) * 1998-06-26 2000-07-01 United Microelectronics Corp A method for fabricating dual damascene
US6395152B1 (en) * 1998-07-09 2002-05-28 Acm Research, Inc. Methods and apparatus for electropolishing metal interconnections on semiconductor devices
US6232231B1 (en) 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6709565B2 (en) * 1998-10-26 2004-03-23 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
CN1264162A (zh) * 1999-02-13 2000-08-23 国际商业机器公司 用于铝化学抛光的虚拟图形
US6259115B1 (en) * 1999-03-04 2001-07-10 Advanced Micro Devices, Inc. Dummy patterning for semiconductor manufacturing processes
US6239023B1 (en) * 1999-05-27 2001-05-29 Taiwan Semiconductor Manufacturing Company Method to reduce the damages of copper lines
US6459156B1 (en) * 1999-12-22 2002-10-01 Motorola, Inc. Semiconductor device, a process for a semiconductor device, and a process for making a masking database
JP2002158278A (ja) * 2000-11-20 2002-05-31 Hitachi Ltd 半導体装置およびその製造方法ならびに設計方法
US6486066B2 (en) * 2001-02-02 2002-11-26 Matrix Semiconductor, Inc. Method of generating integrated circuit feature layout for improved chemical mechanical polishing
US6852630B2 (en) * 2001-04-23 2005-02-08 Asm Nutool, Inc. Electroetching process and system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010219449A (ja) * 2009-03-18 2010-09-30 Nuflare Technology Inc 荷電粒子ビーム描画方法、荷電粒子ビーム描画装置及びプログラム
JP2023183338A (ja) * 2022-06-15 2023-12-27 日本メクトロン株式会社 導電パターン形成方法

Also Published As

Publication number Publication date
KR101055564B1 (ko) 2011-08-08
CN1547763A (zh) 2004-11-17
EP1419523A4 (en) 2007-12-19
CA2456301A1 (en) 2003-03-06
KR20040027990A (ko) 2004-04-01
WO2003019641A1 (en) 2003-03-06
TW573324B (en) 2004-01-21
CN100524644C (zh) 2009-08-05
US20040253810A1 (en) 2004-12-16
EP1419523A1 (en) 2004-05-19

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