TW567589B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
TW567589B
TW567589B TW091132109A TW91132109A TW567589B TW 567589 B TW567589 B TW 567589B TW 091132109 A TW091132109 A TW 091132109A TW 91132109 A TW91132109 A TW 91132109A TW 567589 B TW567589 B TW 567589B
Authority
TW
Taiwan
Prior art keywords
film
gas
semiconductor device
insulating film
manufacturing
Prior art date
Application number
TW091132109A
Other languages
English (en)
Other versions
TW200301004A (en
Inventor
Yoshimi Shioya
Kazuo Maeda
Hiroshi Ikakura
Original Assignee
Canon Sales Co Inc
Semiconductor Process Lab Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Sales Co Inc, Semiconductor Process Lab Co filed Critical Canon Sales Co Inc
Publication of TW200301004A publication Critical patent/TW200301004A/zh
Application granted granted Critical
Publication of TW567589B publication Critical patent/TW567589B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695—Deposition of porous oxides or porous glassy oxides or oxide based porous glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Description

567589 五、發明說明（1) <發明所屬之技術領域〉 本發明是有關於半導體裝置之製造方法，特別是形成 一具有低介電常數的絕緣膜於一以銅膜為主的導線上之半 導體裝置製造方法，或形成一具有低介電常數的主要絕緣 膜於一阻障絕緣膜其上。 〈先前技術〉 —一近幾年，隨著半導體積體電路元件的高度整合，需求 著尚速資料傳輸。為此原因，使用具有低介電常數的絕緣 膜（於此之後，意指為低介電常數絕緣膜）以得到小的RC延 遲。 使用三甲基矽烷（1;1^11161：}171“13116，以{1((：113)3)與％〇 之習知電漿增效CVD方法（PE-CVD方法）以形成此低介電常 數絕緣膜。例如’其在Electr〇chem· S〇c· Faii研討會 摘要ρ· 344( 1 998 )所描述者或類似之M. j, L〇b〇da、 J.A.Seifferly、R.F.Schneider 與 C.M.Grove 所描述者。 更者，在SEMICON Korea Technical Symposium 20 00· ρ· 279 ( 2000 )或類似之 j.Shi·、MA pian〇、TM〇untsier 與 3.^8所描述之使用四甲基矽烷（以11((：：113)4)與％〇之電漿增 效CVD方法。 θ 換言之’以塗佈方法沉積S〇g膜為習知之例子。 附帶地’使用四甲基矽烷、或有機矽烷與甲烷之其它 型態的CVD方法所沉積之絕緣膜一般皆可得到約為2. 3〜2. 8 之相對介電常數。然而，於現今情況下，相較於較易平坦 化之S0G膜’以CVD方法所沉積之絕緣膜於實際使用上會有 第5頁 2060-5290-PF(Nl).ptd 567589
延遲。 在未來，期望以CVD方法沉積主要絕緣膜於阻障絕 膜之上，因為以CVD方法沉積可能製造出具有比sqg膜更佳 膜品質的絕緣膜。為此目的，有必要更進一 介電常數。 少降低其相對 〈發明内容〉 本發明之一目的為提供一種半導體裝置之制造方法 其中形成-主要絕緣膜（其相對介電常數明衣阻章 膜之上…障絕緣膜覆蓋於主要由銅膜所構成的^ 綠上。
在半導體裝置之製造方法中，膜的形成氣體轉換為 漿，以導致反應形成具有低介電常數的絕緣膜於基板^。 其膜的形成氣體特徵為其含有含矽絕緣膜的蝕刻氣體（如 ΜΙ、CL、CA，與CA之其中任一者），還加上若非矽氧 烷（“1犯31^)即是甲基矽烷（以士时1心13116)(^{1(^ : n = 0，l，2,3)，以及含氧氣體。 n 4n
在此實施例中，沉積與蝕刻同時發生在沉積含矽絕緣 膜時，因其膜的形成氣體含有可蝕刻含矽絕緣膜的氣體如 肝3。因此’所形成的含矽絕緣膜表面變得不平坦，並且 相較於只有膜的形成氣體的情況，本實施例之含矽絕緣膜 具有較多的空隙在其中。因此，以此種膜的形成氣體沉積 而成的含矽絕緣膜的介電常數將大大降低。 於具有非石夕氧烷即曱基矽烷（以4((：113) -η · n-0, 1，2, 3)、含氧氣體以及蝕刻氣體的混合氣體中進
567589 五、發明說明（3) 一步加入環己烷或甲基環己烷，更導致增加含矽絕緣膜的 多孔性且更降低含矽絕緣膜的相對介電常數。 〈實施方式〉 本發明實施例將參考圖示作以下說明。 第1圖顯示使用於本發明實施例半導體裝置製造方法 的平行板態（parallel plate type)電漿增效化學氣相沉 積裝置1 0 1結構側視圖。 如電漿增效CVD裝置101具有：沉積區域101A，其絕緣膜 藉由電漿氣體形成於欲沉積之基板2 1上（此後，簡稱為基 板），以及膜的形成氣體（film forming gas)供應區域 1 0 1 B ’具有複數個氣體供應源以組成膜的形成氣體。 沉積區域101A包括如第1圖所示之減壓室1，且減壓室 1經由排出管4與排出單元（exhaust uni t)6相連接。控制 ，壓室1與排出單元6之間相通與否的開/關閥5設置於排出 管4之中途。減壓室1設有壓力量測裝置（如真空儀（未圖 示））以監控減壓室1内的壓力。 提供一相對之上電極2與下電極3於減壓室1内。具有 13· 56MHz高頻電源之高頻電源供應器（RF電源）7連接於上 電極2，以及具有380kHz低頻電源之低頻電源供痒巧/ 於下電極3。這些電源7,8分別提供電力予上電：二 極3以轉換膜的形成氣體為電漿。這些上電極2、下電極^ 與電源7、8組成電漿產生裝置。 上電極2也作為膜的形成氣體之分散組件。複數個 孔形成於上電極2上。位於穿孔背面且吉垃品 Iπ牙〜月囬且罝接面向下電極3的 567589 五、發明說明（4) " 通道（opening)作為膜的形成氣體釋放的通道（導入的通 道）或其相似功能。釋放的通道藉由管路9&與膜的形成氣 體供應區域101B相連接。更者，有些情況下，上電極2具 有加熱器（未圖示）。這是因為在沉積過程中，藉由加熱上 電極2至約1 〇 0 C以避免由膜的形成氣體反應產物所組成的 微粒黏附到上電極2。 下電極3也作為基板2 1的基板支撐物，且它包括加熱 器1 2用以加熱位於基板支撐物上的基板2 1。 膜的形成氣體供應區域1 0 1 B，具有矽氧烷供應源；甲 基石夕烧供應源（SiHn(CH3)4_n:n = 0，l，2,3);含氧氣體供應 源；非環己烷（c^2)即曱基環己烷（CH3c6Hii)供應源；蝕刻 # 氣體供應源；稀釋氣體供應源；以及氮氣（乂）氣體供應源 其作為稀釋氣體或淨化氣體（purge gas)。 經由分支管路9b到9h以及與所有分支管路9b到9h皆相 連接的9a，適當地將氣體供應到沉積區域i〇iA的減壓室1 中。流速調整裝置11 a到11 g與控制分支管路9b到9h的開/ 關裝置10b到1 On, 1 Op設置於分支管路9b到9h中途。控制管 路9a的開/關裝置i〇a設置於管路9a中途。 更者，控制N2氣供應源與分支管路9h以及其他分支 管路9b到9f相通與否之開/關裝置l〇q到l〇u的設置，其藉 由流入&氣以清除在分支管路9b到9f中的殘留氣體。值得 注意的是乂除了清除分支管路9b到9f中的殘留氣體，也清 除管路9a與減壓室1中的殘留氣體。％也可作為稀釋氣 體。
567589
石夕氧烷供應 源’且更具有電 體為電漿。 膜可藉由之後將 如上所示，前述之沉積裝置1 Ο 1具有： 源；含氧氣體供應源；以及蝕刻氣體供應 製產生裝置2、3、7與8以轉換膜的形成氣 經由此裝置，具有低介電常數的絕緣 顯示的電漿增效CVD方法來加以形成。 於疋，如提供一藉由平行板型態之上、下電極2與3以 產生電漿的裝置作為電漿產生裝置。用以提供兩頻率（言 頻及低頻）電力之電源7、8分別連接於上、下電極2與3: 於是，兩頻率（高頻及低頻）之電力供給於各電極2 ，° 產生電漿。 、 下列為供應電力於上電極2與下電極3的結合。特別是 (i)具有大於或等於ΙΟΟΚΗζ以及小於1MHz頻率的低頻電力 供給於下電極3，（ii)具有大於或等於imHz頻率的高頻電 力供給於上電極2，或（iii)低頻電力供給於下電極3且高 頻電力供給於上電極2。 之後，依據使用於本發明的膜的形成氣體，可使用下 列氣體’如石夕氧烧、甲基石夕烧、含氧氣體、餘刻氣體與稀 釋氣體等典型例子。 (i )矽氧烷 六甲基二矽氧烷（HMDS0:(CH3)3Si-0-Si(CH3)3) 八甲基環四矽氧烷（0MCTS:((CH3)2)4Si4 04 )
2060-5290-PF(Nl).ptd 第9頁 567589 五、發明說明（6) ch3 ch3
I I CH3 — Si - O - Si - CH3
I I 0 o
1 I CH3 — Si - O — Si — CH3 3 H c 3 H c 四甲基環四矽氧烷（TMCTS : (CH3H)4Si4 04 ) Η Η
I I CH3 — Si — 0 — Si - CH3
I I 0 o
1 I CH3 — Si — O — Si — CH3
I I
Η H (ii)甲基矽烷（SiHn(CH3)4_n:n = 0, 1，2, 3) 單甲基矽烷（SiH3(CH3)) 雙曱基矽烷（SiH3(CH3)2) 三甲基矽烷（SiH3(CH3)3) 四曱基矽烷（SiH3(CH3)4) (i i i)蝕刻氣體 nf3 cf4 _議11画 2060-5290-PF(Nl).ptd 第10頁 567589 五、發明說明（7)
CsF8 (lv)含氧氣體 氧化氮（N2 0) 水蒸氣（h2o) 二氧化碳氣體（co2) (v)稀釋氣體 氦（He) 氬（Ar) 氮（N2) 接下來參考第2A到2D圖，將對本發明實施例之 :之製造方法作一描述。第2A圖至第2D 體 施例半導體裝置及其製造方法剖面圖。 本發明實 本發明應用於沉積一内導線層絕緣膜35的方法， 線層絕緣膜35夾層於一含有下導線34的絕緣層32與」= 斤上導線38的絕緣層36。使用HMDS + N20 + NF3 + He為膜的合 軋體，且使用電漿增效CVD方法為沉積方法。 、々成 如下將顯示沉積條件。值得注意的是從氣體被導入到 開始、’儿積（電聚被激發）需預留1分30秒的時間（穩定期間） 以替換使用於減壓室中的氣體。加熱上電極2至丨〇 〇。〇以避 免反應微粒黏附到上電極2。 沉積條件 膜的形成氣體 HMDSO 流速：50sccm
2060-5290-PF(Nl).ptd 第11頁 567589 五、發明說明（8) N2 0 流速：2 0 0 s c c m NF3 流速：200seem H e 流速：4 0 0 s c c m 氣體壓力：1. 5Torr 電漿激發條件 下電極 低頻電力（頻率：380KHz) :0瓦（W) 上電極
高頻電力（頻率：13.56 MHz) :250W 基板加熱條件：3 7 5 °C
首先，如第2A圖所示，以電漿增效CVD方法形成由膜 厚約lum的PE-CVD Si〇2膜所構成之含有下導線的絕緣層 32於基板31上。 接著，姓刻含有下導線的絕緣層32以形成一埋藏導線 的溝槽（wiring buried groove)33。之後，形成一用以抑 制銅擴散的TaN膜34a於埋藏導線的溝槽33之表面。 接者’以錢鑛方式形成銅種子層（copper seed la\er)(未顯示）於TaN膜34a之内表面。再來，由塗佈方式 ，藏銅膜於其上。之後，以CMp方法（化學機械研磨法）將"
從埋藏導線的溝槽33突出的銅膜34b與TaN膜34a研磨以得 到一平坦表面。因此，形成由銅膜與TaN膜所構成的 線3 4。 守 、接^，以電漿增效CVD方法形成由PE-CVD S%膜所構 成的阻障絕緣膜35a。之後，使用HMDS + NJ + NF^He之電漿
567589 五、發明說明（9) 增效CVD方法形成由PE-CVD Si02膜所構成的主要絕緣膜 35b。如上所述之膜35a、35b構成内導線層絕緣膜35。之 後’將作更詳細的描述。
特別地’為形成内導線層絕緣膜3 5，先將基板3丨置入 =積裝置1 0 1的減壓室i中，並由基板支撐物3支撐。接 ，^加熱基板31且其溫度維持在3 7 5 。HMDS〇、心〇與氦 氣分別以流速5〇sccm、20〇sccm與4 00sccn^^入如第1圖所 ^之電衆增效沉積裝置101的減壓室1中，且減壓室1中的 氣壓調整為1·5Τ〇ΓΓ。接著，具有38〇KHz頻率的低頻電力 ljOW(相當於〇. 18w/cm2)供給於下電極3。值得注意的是可 月匕有或可能沒有適當電力供給於上電極2。 膜的形成氣體因此轉換為電漿以導致反應。此狀態步 維持一預定時間以形成具有臈厚約1〇〇nm的以―CVD Si〇2 膜’其構成阻障絕緣膜35a °如上所示構成基板2 i。 其後，基板21的溫度維持在3 7 5艽，HMDS〇、、N ，、He ^別以流速50sccm、2〇〇sccm、㈣導 =減壓室1中，且氣壓調整為157町。之後，具有 雷；員率的高頻電力25〇W(相當於0· 3W/cm2)供給於上 電和。值得注意的是沒有電力供給於下電極3。
，以开、評3與Η6因此轉換為電聚。此狀態維持4丨 二，膜厚約500n_PE~cvD si〇2膜，其構成主要 例中，因膜形成氣體含有可姓刻含 :=氣；如牝’故沉積與勉刻同時發生。為“ 因，>儿積時，切料膜的表面變得不平坦。0此f
567589 五、發明說明（10) 於只有膜形成氣體所形成的絕緣膜實施例，本實施例之含 矽絕緣膜具有較多的空隙在其中。因此，含矽絕緣膜的介 電常數將大大降低。經由實驗，可得到在含矽絕緣膜中具 2 · 2到2. 3的相對介電常數。 如上所述，具有膜厚約600nm的内導線層絕緣膜35是 由阻障絕緣膜35a與主要絕緣膜35b所構成。 接著，使用與形成PE-CVD Si02膜32相同的方法，形 成由膜厚約lum的PE-CVD Si02膜所構成的含有上導線的絕 緣層3 6於内導線層絕緣膜3 5上。
接著’以習知的雙道金屬鑲嵌法（dua卜damascene)方 法，形成主要由銅膜所構成的連接導體37與上導線38。值 得注意的是圖不中的參考標號37a及38a代表TaN膜，參考 標號37b及38b代表銅膜。 接下來’在相同的條件下使用與形成阻障絕緣膜35& 相同的方法’形成阻障絕緣膜3 9於整個表面。因此，完成 半導體裝置。 依據本發明的實施例，採用含有用以 如上所述 含矽絕緣膜的NF3加上若非矽氧烷即是曱基矽烷 (SiHn(CH3)4_n.n-〇, 1，2,3)與含氧氣體之氣體為内導線層
緣膜3 5的主要絕緣膜3 5 a之贈沾r ^碰 π 八膜的形成氣體，該主要絕緣月 3 5 a具有低7丨電吊數。 用以蝕刻含矽絕緣膜& # _ . ^ ,道從八访绍緣时、的軋體’其^於膜的形成氣體 中，導致含矽絕緣膜的形忐1女 成具有較多的空隙在其中。因 此，含矽絕緣膜的介電常數將大大降低。
2060-5290-PF(Nl).ptd 第14頁 567589 五、發明說明（11) 如前述，雖然本發明依據實施例以描述詳細，但本發 明的範圍並不侷限於實施例中的例子。任何熟習此技藝 者’可輕易作些許之更動與潤飾，然必須了解到如此之些 許之更動與潤飾皆涵蓋於本發明之保護範圍内。 在實施例中，其他矽氧烷可用以取代HMDS〇。換言 之’甲基石夕烧（SiHn(CH3)4_n:n = 〇, 1，2, 3)可用以取代矽氧 燒。因甲基矽烷的種類已經描述過，故在此予以省略。 曰更者，膜的形成氣體可含有若非甲基環己烷（CH3C6Hu) 即疋環己烷（C6 Hu )，加上矽氧烷與甲基矽烷之任一者、含 氧氣體以及餘刻氣體。使用之，可使膜的多孔增加並更 進一步降低介電常數降低。 此外，含有非氬（Ar)即氮U2)的鈍氣用以取代氦（He) ，以加入膜的形成氣體。使用之，可避免所形成的膜有所 謂的白色混濁（white turbidity)。當情況需求，鈍氣也 可被膜的形成氣體排除在外。 如前述，依據本發明在半導體裝置之製造方法中，！ 的形成氣體轉換為電漿以形成具有相對低介電常數的含； 絕緣膜，使用氣體中含矽絕緣膜的蝕刻氣體加上若 ^ 烷即是曱基矽烷（SiHn(CHqL ·η-η 1 作為膜的形成氣體。3“ °，1’2,3)以及含氧氣體 因為沉積與蝕刻同時發 膜的形成氣體含有可姓刻含 絕緣膜表面變得不平坦，並 餘刻氣體之情況，本實施例
生在沉積含矽絕緣膜時（因其 矽絕緣膜的氣體如ΝΙ?3 )，含矽 且相較於膜形成氣體中不含有 之3矽絕緣膜具有較多的空隙
567589 五、發明說明（12) 在其中。 因此，以膜的形成氣體其具有可蝕刻含矽絕緣膜的氣 體加以沉積，該含矽絕緣膜的相對介電常數可大大降低。 inra 2060-5290-PF(Nl).ptd 第16頁 567589 圖式簡單說明 的雷mr惠使户用於本發明實施例半導體裝置製造方法 相沉積裝置結構側視圖。 、生古土立,丨而闰 圈颂不本發明實施例半導體裝置及其製 造方法剖面圖。 〈符號說明〉 上電極 排出管 排出單元 8低頻電源供應器 9b〜9h分支管路 1減壓室 3 下電極 6 5開關閥 7高頻電源供應器 9a管路 10a管路的開/關裝置 10b〜10n，l〇p分支管路的開/關裝置 3 2 含有下導線的絕緣層 34下導線 3 5 内導線層絕緣膜 3 5b 主要絕緣膜 1 0q 1 0u &氣供應源與分支管路的開/關裝置 11a〜llg流速調整裝置12加埶器 21，31 基板 33溝槽 3 4 a，3 7 a，3 8 a T a N 膜 3 5 a，3 9阻障絕緣膜 3 6含有上導線的絕緣層3 7連接導體 38上導線 37b，38b銅膜 1 01電漿增效化學氣相沉積裝置 101A沉積區域 101B氣體供應區域

Claims (1)

  1. 567589
    ι· 一種半導體裝置之製造方法，其中一膜形成氣體 換為電漿以導致反應形成具有低介電常數的絕緣膜於 積的基板上， 儿 其特徵在於： 該形成氣體含有一矽氧烧與甲基矽烧之其中任一者 一含氧氣體，以及一蝕刻氣體。 、 2·如申請專利範圍第1項所述之半導體裝置之製造方 法’其中該膜形成氣體含有環己烷與甲基環己烷之其&中任 一者，加上矽馬烷與甲基矽烷之其中任一者、含氧^體， 以及蝕刻氣體。 3·如申請專利範圍第1項所述之半導體裝置之製造方 法’其中在該膜形成氣體中的該矽氧烷為六甲基二矽氧烷 (HMDSO:(CH3)3Si - 0-Si(CH3)3)、八甲基環四矽氧烷 (OMCTS : ((CH3 )2 )4S i4 〇4 )，以及四甲基環四石夕氧院 (TMCTS:(CH3H)4Si4 04 )之其中任〆者0 4 ·如申請專利範圍第1項所述之半導體裝置之製造方 法，其中該含氧氣體為％〇、jj20，與C02之其中任一者。 5 ·如申請專利範圍第1項所述之半導體裝置之製造方 法，其中該蝕刻氣體為評3、CF4、C2F6，與C3F8之其中任一 者。 6 ·如申請專利範圍第1項所述之半導體裝置之製造方 法，該膜形成氣體含有氦（He)、氬（Ar)，以及氮（N2)之其 中任一者。 方 7 ·如申請專利範圍第1項戶斤述之半導體裝置之製造
    567589 六、申請專利範圍 法，其中該欲沉積的基板，其表面具有被阻障絕緣層所覆 蓋之主要為銅膜所構成的導線。 2060-5290-PF(Nl).ptd 第19頁
TW091132109A 2001-12-05 2002-10-29 Manufacturing method of semiconductor device TW567589B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001371625A JP3749162B2 (ja) 2001-12-05 2001-12-05 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW200301004A TW200301004A (en) 2003-06-16
TW567589B true TW567589B (en) 2003-12-21

Family

ID=19180643

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091132109A TW567589B (en) 2001-12-05 2002-10-29 Manufacturing method of semiconductor device

Country Status (5)

Country Link
US (1) US20030104689A1 (zh)
EP (1) EP1321975A3 (zh)
JP (1) JP3749162B2 (zh)
KR (1) KR20030046303A (zh)
TW (1) TW567589B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6541367B1 (en) 2000-01-18 2003-04-01 Applied Materials, Inc. Very low dielectric constant plasma-enhanced CVD films
US20030211244A1 (en) * 2002-04-11 2003-11-13 Applied Materials, Inc. Reacting an organosilicon compound with an oxidizing gas to form an ultra low k dielectric
US20030194495A1 (en) * 2002-04-11 2003-10-16 Applied Materials, Inc. Crosslink cyclo-siloxane compound with linear bridging group to form ultra low k dielectric
US6936551B2 (en) * 2002-05-08 2005-08-30 Applied Materials Inc. Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices
US7056560B2 (en) * 2002-05-08 2006-06-06 Applies Materials Inc. Ultra low dielectric materials based on hybrid system of linear silicon precursor and organic porogen by plasma-enhanced chemical vapor deposition (PECVD)
US7060330B2 (en) * 2002-05-08 2006-06-13 Applied Materials, Inc. Method for forming ultra low k films using electron beam
US6897163B2 (en) * 2003-01-31 2005-05-24 Applied Materials, Inc. Method for depositing a low dielectric constant film
US20040266184A1 (en) * 2003-06-30 2004-12-30 Ramachandrarao Vijayakumar S Post-deposition modification of interlayer dielectrics
US20050214457A1 (en) * 2004-03-29 2005-09-29 Applied Materials, Inc. Deposition of low dielectric constant films by N2O addition
US20070134435A1 (en) * 2005-12-13 2007-06-14 Ahn Sang H Method to improve the ashing/wet etch damage resistance and integration stability of low dielectric constant films
US7297376B1 (en) 2006-07-07 2007-11-20 Applied Materials, Inc. Method to reduce gas-phase reactions in a PECVD process with silicon and organic precursors to deposit defect-free initial layers

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5040046A (en) * 1990-10-09 1991-08-13 Micron Technology, Inc. Process for forming highly conformal dielectric coatings in the manufacture of integrated circuits and product produced thereby
EP0519079B1 (en) * 1991-01-08 1999-03-03 Fujitsu Limited Process for forming silicon oxide film
DE69224640T2 (de) * 1991-05-17 1998-10-01 Lam Res Corp VERFAHREN ZUR BESCHICHTUNG EINES SIOx FILMES MIT REDUZIERTER INTRINSISCHER SPANNUNG UND/ODER REDUZIERTEM WASSERSTOFFGEHALT
JP2684942B2 (ja) * 1992-11-30 1997-12-03 日本電気株式会社 化学気相成長法と化学気相成長装置および多層配線の製造方法
JPH07254592A (ja) * 1994-03-16 1995-10-03 Fujitsu Ltd 半導体装置の製造方法
JP3355949B2 (ja) * 1996-08-16 2002-12-09 日本電気株式会社 プラズマｃｖｄ絶縁膜の形成方法
KR100205318B1 (ko) * 1996-10-11 1999-07-01 구본준 자유전율의 절연막 제조방법
US6211096B1 (en) * 1997-03-21 2001-04-03 Lsi Logic Corporation Tunable dielectric constant oxide and method of manufacture
US5989929A (en) * 1997-07-22 1999-11-23 Matsushita Electronics Corporation Apparatus and method for manufacturing semiconductor device
JP3141827B2 (ja) * 1997-11-20 2001-03-07 日本電気株式会社 半導体装置の製造方法
US6287990B1 (en) * 1998-02-11 2001-09-11 Applied Materials, Inc. CVD plasma assisted low dielectric constant films
JP2000332010A (ja) * 1999-03-17 2000-11-30 Canon Sales Co Inc 層間絶縁膜の形成方法及び半導体装置
US6440876B1 (en) * 2000-10-10 2002-08-27 The Boc Group, Inc. Low-K dielectric constant CVD precursors formed of cyclic siloxanes having in-ring SI—O—C, and uses thereof
US6716770B2 (en) * 2001-05-23 2004-04-06 Air Products And Chemicals, Inc. Low dielectric constant material and method of processing by CVD

Also Published As

Publication number Publication date
JP3749162B2 (ja) 2006-02-22
US20030104689A1 (en) 2003-06-05
EP1321975A2 (en) 2003-06-25
EP1321975A3 (en) 2004-11-24
TW200301004A (en) 2003-06-16
KR20030046303A (ko) 2003-06-12
JP2003174029A (ja) 2003-06-20

Similar Documents

Publication Publication Date Title
JP4090740B2 (ja) 集積回路の作製方法および集積回路
JP3712356B2 (ja) 成膜方法および半導体装置の製造方法
KR100407012B1 (ko) 반도체 장치 및 그 제조 방법
TW493244B (en) Semiconductor device and method of manufacturing the same
JP5567588B2 (ja) 酸素含有前駆体を用いる誘電体バリアの堆積
TWI638425B (zh) 高深寬比結構中具有改良階梯覆蓋之密閉性ｃｖｄ蓋
JP3745257B2 (ja) 半導体装置及びその製造方法
JP3545364B2 (ja) 半導体装置及びその製造方法
CN103430291A (zh) 用于恢复及封孔受损的低介电常数薄膜的紫外线辅助硅烷化
JP2008530821A5 (zh)
JP2009170872A (ja) 優勢エッチング抵抗性を具備する低ｋ誘電バリアを得る方法
TW567589B (en) Manufacturing method of semiconductor device
JPWO2008010591A1 (ja) 多孔質絶縁膜の形成方法
CN102770580A (zh) 藉由等离子体增强化学气相沉积使用含有具有机官能基的硅的杂化前驱物所形成的超低介电材料
JPH098032A (ja) 絶縁膜形成方法
JPH10335322A (ja) 絶縁膜の形成方法
JP2005294333A (ja) 成膜方法及び半導体装置
JP4032044B2 (ja) 成膜方法、半導体装置の製造方法及び半導体装置
TW531835B (en) Film forming method, semiconductor device and manufacturing method of the same
JP2011151057A (ja) 半導体装置の製造方法
WO2004038782A1 (ja) 半導体装置及びその製造方法
JPH10209148A (ja) 低誘電率絶縁体膜の形成方法およびこれを用いた半導体装置
CN113802108A (zh) 沉积的方法
JPH07288251A (ja) 半導体装置の製造方法
KR101008490B1 (ko) 저온 화학기상증착에 의한 산화막 증착 방법

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees