TW561598B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW561598B
TW561598B TW91123266A TW91123266A TW561598B TW 561598 B TW561598 B TW 561598B TW 91123266 A TW91123266 A TW 91123266A TW 91123266 A TW91123266 A TW 91123266A TW 561598 B TW561598 B TW 561598B
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TW
Taiwan
Prior art keywords
aforementioned
conductive pattern
conductive
semiconductor device
terminals
Prior art date
Application number
TW91123266A
Other languages
English (en)
Inventor
Tetsuro Asano
Mikito Sakakibara
Hideyuki Inotsume
Haruhiko Sakai
Shigeo Kimura
Original Assignee
Sanyo Electric Co
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Filing date
Publication date
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Publication of TW561598B publication Critical patent/TW561598B/zh

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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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Description

【發明所屬之技術領域】 本發明係有關一種半導體裝置， 圖案、’以解決使用者設定不方便的問 【先别技術】 導電 561598 尤指一種著力於 題之半導體裝置 行動電話等移動體用通信機器中 微波情形居多，而且，大多使用可：二 關元件來作為天線之切換電路或收4破之開 , 为电吩a叹努仏號之切換電路篝 (例如曰本特開平9 — 1 8 1 6 42號）。由於 用#用石由几力―Λ 、 1更Ν頻 &大多採 一 鎵（GaAs)之場效電晶體（以下稱為FET)作為其 : 因此，將前述開關電路本身加以積體化後之單晶微 波積體電路（MM 1C)之開發亦隨之有所進展。 而且’為實現習知半導體裝置之小型化、低成本化， k出 種日日片尺寸型封裳（Chip Scale Package ， CSP)。 關於其半導體裝置，以化合物半導體之GaAs的雙聯開關電 路裝置為例說明如下（例如參考非專利文獻1 )。 第9圖係表示習知化合物半導體開關電路裝置之電路 圖。遠電路係由：在通道（channel )層表面設有源極、閘 極及汲極之作為第1、第2FET之FETal、FETa2，以及作為 第3、第4FET之FETb卜FETb2;分別與第卜第2FET之源極 (或汲極）相連接的作為第卜第2輸入端子之I N a卜I N a 2， 以及分別與第3、第4FET之源極（或汲極）相連接的作為第 3、第4輸入端子之iNb卜INb2 ;與第卜第2FET之汲極（或 源極）相連接之第1共通輸出端子之OUTa，以及與第3、第 4F ET之汲極（或源極）相連接之第2共通輸出端子之0UTb ;
314083.ptd 第7頁 561598 五、發明說明（2) 、 將作為第1、第3FET之FETal、FETbl之閘極分別與作為第 控制端子之C11 - 1相連接之電阻Ra 1、Rb 1 ;以及將作為第 2、第4FET之FETa2、FETb2之閘極分別與作為第2控制端子 之Ct 1-2相連接之電阻Ra2、Rb2所構成。 配置電阻Ral、Ra 2及R b 1、R b 2之目的係在於防止高井員 信號相對於形成交流接地之控制端子Ct 1 - 1、ct 1 -2之直、流 電位而經由閘極洩漏。 作為第1、第2FET之FETal、FETa2，以及作為第3、第 4FET之 FETM、FETb2係利用 GaAs MESFET(耗盡 (depletion)型FET)所構成，並積體化於GaAs基板上。 第9圖所示之電路係由使用GaAs MESFET之所謂單極雙 投（SPDT’ Single Pole Double Throw)之化合物半導體開 關電路裝置之原理的2組電路所構成，其特徵在於使各自 之控制端子共通化，利用合計8 p i η (插腳）達成雙聯開關 化。 其次，參照第9圖，針對本發明之化合物半導體開關 電路裝置的動作加以說明。 施加於第1及第2控制端子c 11 - 1、C11 - 2之控制信號為 互補信號，施加有高位準信號側之F E T會導通（〇 N )，而施 加於輸入端子INal或INa2中任一方之輸入信號及施加於輸 入端子INbl或INb2中任一方之輸入信號會分別傳送至共通 輸出端子OUTa及OUTb。 例如當施加高位準信號於控制端子C11 _ 1時，則作為 開關元件之FETal、FETbl會導通，輸入端子INa2的信號及
561598 五、發明說明（3) 輸入端子INb2的信號會分別傳送至輸出端子〇uTa及輸出端 子 OUTb。
因此存在有2種信號，而欲選擇其中之一時，例如當 存在有行動電話等移動體通訊機器中所使用的CDMA方式之 信號及GPS方式之信號，而欲選擇其中之一時，若將CDMA 方式的平衡信號（或GPS方式的平衡信號）與輸入端子 INal、INbl相連接，將GPS方式的平衡信號（或CDMA方式的 平衡信號）與輸入端子I Na2、I Nb2相連接的話，則依據從 輸出端子OUTa、OUTb的兩端施加於控制端子c11 - 1、C11 -2 之控制信號的位準，可取出CDMA方式的信號或GPS方式的 信號。亦即，作為雙聯開關元件而動作。 第1 0圖表示將習知化合物半導體開關電路裝置加以積 體化之化合物半導體晶片11 9之一例。 於GaAs基板中央部的左右配置進行切換之2組成對的 FETa卜 FETa2及 FETbl、FETb2，將電阻 Ra卜 Ra2、RM、
R b 2連接於各F E T之閘極。而端子有輸入端子i n a 1、I N a 2、 INb卜INb2，共通輸出端子〇UTa、OUTb，以及控制端子 C11 - ：l、C11 - 2等8個（參照第1 3圖），將對應於各端子之電 極焊塾 Ial、Ia2、Ibl、Ib2、Oa、Ob、Cl、C2設置在基板 周邊。而且，以虛線表示之第2層配線係在各FET的閘極形 成時同時形成之閘極金屬層（Ti (鈦）/ Pt (鉑）/ A u (金））7 7 ’以貫線表示之第3層配線則係進行連接各元件 及形成焊塾之焊墊金屬層（Ti (鈦）/ Pt (鉑）〆Au(金））78。 在第1層基板作歐姆（Ohmic )接觸之歐姆金屬層（AuGe (金錯
314083.ptd 第9頁 561598
合金）/ Ni (鎳）/ Au (金 電阻兩端之取出電極者 第1 〇圖中並未圖示。 ))係 ，由 形成各F E T之源極 於與焊墊金屬層相 :及極及各 重疊，故在 裝 第11圖係表示將化合物半導 而形成之化合物半導體開關電路 圖’ （B)為剖視圖。
化合物半導體晶片i i 9之各電極以第i 〇圖 t配置，化合物半導體晶片119之各電極分別藉m 機構137、導電圖案部135、通孔133,而與各電極之位置 所對應的位置上之外部電極丨3 4作電性連接。 亦即，8個外部電極1 3 4係以相對於絕緣基板i 2 2的中 心線形成左右對稱的方式各配置4個，而且沿著絕 122的一邊，第卜第2、第3、第4輸入端子以135心土 135b、135c、135d的順序配置，同時，沿著絕緣基板122 一邊之對邊，第1控制端子ctu、第1共通輸出端子 OUTa、第2共通輸出端子〇UTb、第2控制端子ctl-2則係以 1 3 5 h、1 3 5 g、1 3 5 f、1 3 5 e的順序配置。 封裝體（package )的周圍四個側面係以樹脂層1 3 8及絕 緣基板1 2 2的剖面所形成，封裝體的上面係以經平坦化之
樹脂層1 3 8的表面所形成，封裝體的下面係以絕緣基板1 2 2 的背面側所形成。 該化合物半導體開關電路裝置係在絕緣基板1 2 2的上 面覆蓋約0 · 3 m m的樹脂層1 3 8，以密封化合物半導體晶片 1 1 9。化合物半導體晶片1 1 9具有約1 3 0// m之厚度。島部
314083.ptd 第10頁 561598 五、發明說明（5) 12 5 與導電圖案部 135a、135b、135c、135 d 及 135e、 135f、135g、135 h會從封裝體的端面後退，而只有導電圖 案之連接部的切斷部分露出於封裝體側面。 又，封裝體表面側整面係以樹脂層i 3 8所形成，而背 面側的絕緣基板122之外部電極i34a、134b、134c、134d 及1 3 4 e、1 3 4 f、1 3 4 g、1 3 4 h係以左右（上下）對稱之圖案配 置’因而難以判斷電極之極性，因此最好係於樹脂層1 3 8 的表面側形成凹部或加以印刷等，以刻印表示極性的記 號。 第12(A)圖係表示形成於絕緣基板122表面之導電圖寶 的俯視圖，第12(B)圖係表示形成於絕緣基板122背面側$ 導電圖案的俯視圖。 以虛線圍繞的封裝區域i20呈矩形形狀，而且互相隔 著約100" „!之間隔縱橫配置。該間隔會在之後的製程 成切割（d i c i n g)線1 2 4。導雷si崇Λ夂私壯 > 案 封裝區域120内形3 島4 125及V電圖案部126，而該等圖案在各 内均為相同之形狀。其中，島香丨25# 哀&或1 20 曰《 1 1 _邱# s ^ 馬。1丄係格載化合物半導體 日日片119的。Μ立，導電圖案部126則係連 片119之電極焊墊及連接機構的部位。“物丰導體曰Ε 從島片部125係以2條第i連結部12 該等線寬係以較島部丨25A + t^ 、戈之圖案延伸。 連钍邙127将赭、丹Λ 寬例如〇· 5mm延伸。第1 遝〜W 1 2 7係越過切割線i 24，一直延 域120的島部125相連結為止。而繁彳、查处”相邠之封裝11 裝區域1 2 0周圍之並、畜口、奎\士立 、、、口部1 2 7又與圍繞制 衣l a u u周固之共通連結部} 3 2相連結。
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從導電圖案部1 26則係朝各個第2連結部i 盘μ 部127垂直之方向延伸，並越過切割線124，—吉、弟1連結 相鄰之封裝區域120的導電圖案部126相連結 、伸至與 鄰接的第2連結部1 28分別利用第3連結部1 29在切$ ^互相 内相連結。 隹切割線124 從位於封裝區域120内的一邊之兩端的導電圖 起’各第4連結部1 3 〇係朝與第1連結部1 2 7平行、與第°、 結部1 28垂直的方向延伸，且越過切割線丨24，延彳/申至2連 鄰之封裝區域1 20的導電圖案部1 26相連結為止，第與社相 4 1 3 0與圍繞封裝區域1 2 〇周圍之共通連結部1 3 2相連、社° 而且’第4連結部130藉由第5連結部131，而在切判、、、^ 内與第1連結部127相連結。 ° Ί 如上所述，利用第；1、第2、第3、第4、第5連結部 1 2 7、1 2 8、1 2 9、1 3 0、1 3 1延伸的方式，將各封裝區域丄2 〇 的島部1 2 5與導電圖案部1 2 6予以電性共同連接。 — 參閱第1 1 (B )圖，在絕緣基板1 2 2上每一封裝區域1 2 〇 各配置有通孔（through hole)133。通孔133之内部埋設有 鹤等導電材料。而在背面側對應各通孔1 3 3形成有外部電 極 134a、134b、134c、134d 及 134e、134f、134g、134h。 該等外部電極 134a、134b、134c、134 d 及 134e、134f、 13 4g、l34h係以從封裝區域120的端部後退約〇. 05至0· 1mm 之圖案所形成。透過各通孔1 3 3與共通連結部1 3 2作電性連 接’並且以由樹脂層1 3 8所形成之封裝體將外型覆蓋。 【非專利文獻1】
314083.ptd 第12頁 561598 五、發明說明（7) 特願2 0 0 1 - 1 2 1 2 9 3號說明書 【發明所欲解決之問題】 路方ΐ ΐ所示之雙聯開關電路襄置中，如第13圖所示之電 =^ ^圖，必須在使用者側之基板上使RF信號路 ==體15〇外，裝設RF信號路徑交又 型化之晶片3作為CSP(Chip Scale packa“，P晶片 尺寸5L封裝件），仍會產生在使 ， , ,Θ θ 7生王你忧用者側基板所佔面積較 5疋於没计基板時有所限制等問題。 、
用可：Ϊ矽半導體晶片之性能顯著提升，i於高頻帶之利 用可此性亦不斷提高。例如_ ^ 25GHz以上之石夕半導體的^雪士曰稭/使用fT(截止頻率）為
Si::::夫以：可： = «電 昂貴的化合物半導體以利用於高頻，，故使用
接古日目d m 1 Λ 日日片，不過，若矽半導體晶片的性能 同且具利用可能性，目丨丨S 狀於曰主从Α人1 則日日圓本身當然會在價格競爭方面 勝於叩貝的化合物半導辦曰 即使朝小型化及低曰；。而且，化合物半導體晶片 拄作士认ΐ 進展，只要基板佔有面積-直維
揮，在謀求晶片小型化^二優勢將無法完全發 ^ ^ ^ ni ^ r , 化^封哀體小型化之同時，使用者側 =女裝時之小型化亦是眾望所歸的。 ’發明内容】 缘性ί =鑑Π述問題點所開發者，係'-種具備有絕 土低％衣面具有稷數個電極焊墊之半導體晶 片、設於基板且分別與複數個電極焊墊相對應ίϊΐ圖
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案、連接複數個電極焊墊及導電圖 別與導電圖案相對應之外茶之連接機構、以及分 徵為：利用絕緣性樹脂將^ ^極之半導體裝置，其特 圖案上，該至少一個導電片固定於至少一個導電 端，通過前述晶片下方而從曰、η部連接電極部分作為起 端，而將連接機構固定於露^曰部。、端部露出並延伸至尾 猎此，可以提供一種於csp之 號路徑實質交又之電路，且於 1體内，，現將 小型化之半導體裝置。 W女衷時，得以謀求 【實施方式】
參閱第1圖至第5圖 詳細說明本發明之第 1貫施形 絕緣基板1、導電圖案2、 5以及外部連接電極6'所構 半 本發明之半導體裝置係由 導體晶片3、連接機構4、通孔 成。 第圖係固定有_晶片之 由設置於絕緣基板1上之8支導電圖案2所开固成導電圖案2係 於半導體晶片上之電極焊墊相於且與配置 固定區域U中並沒有相當於習知的 ^導體晶片的 片係利用絕緣性樹脂而固定於電7 ’ +導體晶 導電圖案2係利用鍍金方式=伸案，上。 例如導電圖t 2c係將與外部連接電極相、 ^電圖案 為起端，通過以虛線所示之半導體晶片固定區Ϊ \部5作 而從晶片的端部露出並延伸至尾端。導電圖案ti1之下方 路出之位
第14頁 561598 五、發明說明（9) 置並不侷限於弟1(A)圖所示之位置，不過，當固定半導體 晶片時，從起端延伸至晶片下方之部分以外，必須設置從 晶片端部露出至少1處導電圖案2 c的部分。而且，由於在 該露出部固定連接機構，因此於搭接時當然必須露出所需 面積。再者，在本發明之實施形態（容後詳述）中，為了達 到變換晶片上的電極焊墊之排列順序以及與電極焊墊相對 應的輸入端子之排列順序之目的，導電圖案2 c係以繞過導 電圖案2 b的方式延伸，並且從晶片端部露出。 例如在晶片下方彎折導電圖案2c，並於搭接時從晶片 端部露出所需面積時，其尾端可以位於半導體晶片之下 方，也可以具有複數個露出部。 如第1(B)圖所示，該等導電圖案2在每一封裝區域1〇 内均為相同之形狀，且利用連結部丨2連續設置。各封裝區 域1 0具有例如長邊*短邊為1.9mm*1.6m m之矩形形狀，而固 定區域1 1為例如0· 62mm*0. 31mm，然而該固定區域丨1會因 半導體晶片大小而異。而且，各封裝區域1 〇之導電圖案2 係互相隔著約1 0 0// m之間隔縱橫配置。前述間隔會在組裝 步驟中形成切割線。在此，各圖案2係利用鍍金方式設 置，不過亦可利用無電解電鍍方式，此時由於並不需要連 結，因此各導電圖案係個別設置。 如第2圖所示，複數個（例如1 〇 〇個）對應於1個半導體 晶片之封裝區域1 0係縱橫配置於基板1上。基板1係由陶究 或玻璃環氧樹脂等所構成之大張的絕緣基板，將1張或數 張該基板互相重疊，當板厚合計為1 8 0至2 5 0 // m時，則該
314083.ptd 第 15 頁 561598
板厚可保持製程中之機械強度。 第3圖係表示半導體晶片3。該晶片3與第1 0圖相同。 亦即’於GaAs基板之中央部的左右，配置進行切換之2組 成對的 FETa 卜 FETa2 及 FETbl、FETb2，電阻 Ra 卜 Ra2、 R b 1、R b 2係連接於各F E T之閘極。而端子有輸入端子 INal、INa2、INb卜 INb2，共通輸出端子 〇UTa、OUTb，以 及控制端子C11 - 1、c 11 - 2等8個（參照第4 ( B )圖），將對應 於各端子之電極焊墊Ial、Ia2、Ibl、Ib2、Oa、Ob、Cl、 C 2設置在基板周邊。而且，以虛線表示之第2層配線係在 各FET的閘極形成時同時形成之閘極金屬層（τ i (鈦）/ P t (鉑）/ A u (金））7 7，以實線表示之第3層之配線則係進行 連接各元件及形成焊墊之焊墊金屬層（Ti (鈦）/ pt (鉑 A u (金））7 8。在第1層基板作歐姆（〇 h m i c )接觸之歐姆金屬 層（A u G e (金鍺合金）/ N i (鎳）/ A u (金））係形成各f1 £ τ之源 極、汲極及各電阻兩端之取出電極者，由於與焊墊金屬芦 相重疊，故在第3圖中並未圖示。 此外，該開關電路裝置之電路圖與第9圖所示者相 同，而且動作原理亦如前述，故在此省略其說明。 利用第4圖說明將半導體晶片3固定於絕緣基板1之 例。第4(A)圖係俯視圖，第4(B)圖係電路方塊圖。而&， 按照第3圖所示之方向固定第4圖之晶片3。 形成於基板之導電圖案2中的導電圖案2c係以通孔部, 為起端，通過晶片3之下方，而從晶片3端部露出並延伸3 ^ 尾端。
314083.ptd 561598
五、發明說明（π) 化合物半導體晶片3之各電極焊墊，係利用分別對廉 且接近各電極焊墊之導電圖案2及連接機構4進行連接，"並 分別藉由連接機構4、導電圖案2、通孔5與各電極焊墊相/ 對應之外部連接電極6作電性連接。 連接機構4連接有半導體晶片3之各電極焊墊及各導電 圖案2。藉由利用熱壓接方式之球形接合或利用超音波方“ 式之楔形接合，一次進行引線接合，將輸入端子用電極 墊I a 1、I a 2、I b 1、I b 2，控制端子用電極焊墊c J，輪沪 子用電極焊塾〇a、0b，以及控制端子用電極焊墊。分 2 導電圖案2a、導電圖案2c、導電圖案2b、導電圖案^ 電圖案2h、導電圖案2g、導電圖案2f、導電圖案2\相 接。 >、連 如圖所示，導電圖案2c係以通孔部5為起端，以銬 導電圖案2b的方式在晶片3下方延伸，並從晶片3露出"^直至 尾端。輸入端子用電極焊墊I a2與其導電圖案&尾端側 露出部相連接，而且，輸入端子用電極焊墊丨b丨與2 附近之導電圖案2b相連接。 ’、 在此，於各導電圖案2標示所對應之端子之符號。 圖可知，藉由進行該連接，雖然使用與習知相同之曰 不過輸入端子INa2及輸入端子INbli排列順序與習:’ 置方式相反，能夠以將分別與該輸入端子連接之電極塾 (I a2、I b 1 )之排列順序予以變換之方式配置。藉此， 實現一種於封裝體内將RF信號路徑實質交又之^路。"以 第4(B)圖係表示利用本發明之封裝體内部及端子之電
314083.ptd 第17頁 561598 五、發明說明（12) 路Γί Ϊ發Γ:使導電圖案2c繞路的方式，將晶片3的輪 Tn ? 焊墊1a2、Ibl及分別與其連接之輸入端子 :a、=的排列順序加以變換，而可以從圖的上 舰、N卜INa2、麵之川員序酉己置。亦即，如第 ^，右晶片上之電極焊塾的排列順序（U2 一 ibi)以及盘复斤 =焊墊相對應之端子的排序順序（INa2_lNbi)相同之情
2 i時’則在ϊ4圖中端子的排列順序會變成相反的排 :)順序：而可：貫現一種於封裝體内部將rf信號路徑二 ^ ^ =電路。藉此，由於係藉由CSP内部的導電圖案2使RF 規格信號：；號路】；：：要在使用者側使Α規格信號及Β 在此，由於料電圖案2使用用以形成電鍵圖案之 膜印刷，故可以將圖案（導電圖案）之間的最小 子
二:。*於大幅縮小導電圖案之間的距離，故藉此成广 吊有助於封裝體之小型化。 F 第5圖係表示將化合物半導體晶片3組裝於 成之化合物半導體開關電路裝置之剖視圖。 斤形 化合物半導體晶片3係利用絕緣性黏著劑固定於 ，案基板上’晶片3之各電極焊墊分別藉由連接機構電 、導電圖案2mm電極焊塾之位置所對應 位置上之外部連接電極6作電性連接。 a、 在基板1上配置有對應各導電圖幸？ 穿基板i，且其内部埋設有鶴等導4:之通而孔且5。貫 具有與各通孔5相對應且作為各端子之外部連接電極^ $ 561598
五、發明說明（13) 圖（A))。 亦即，形成8個端子之外部遠4 其柅m由、μ , L 1 l… 1連接電極6係以相對於絕緣 基板1的中心線形成左右對稱的 絕緣基板丨的一邊，以第mA^方子式^配置4個，而且沿著 INb卜第2輪入端子⑺以、第Nal、第3輸入端子 同時，沿著絕緣基W-邊之f邊入端子1剛順序配置， cti-卜第i共通輸出端子0UTa、第=第1控制端子 第2控制端子CU-2的順序配置（第5 R、通輸出端子〇U'、 實祐形妒 ， I第5 (B)圖）。如此’根據本 的排列順將庠由力封、裝傲體導出之第2及第3輸入端子INa2、INbl 路徑交又。口以艾換’因而並不需要在使用者側將RF信號 封製體的周圍四個側面係 剖面所渺忐^ ^ 1 U向係以树脂層1 5及絕緣基板1的 所形成，封获辦^ 係千坦化之樹脂層1 5的表面 成。的下面則^邑緣基才反㈤背面側所形 的η 〇化β物半導體開關電路裴置係在紹給A 1卜舜笔 、、勺〇· 3mm的樹脂層i 5，以 ，、在、、色緣基板1上復盍 半導體晶片3具有 、s物半導體晶片3。化合物 各導電圖案/，、m、、、 / m之厚度。由於靠近晶片3配置有 離半導體^ K卩知以可以將引線接合的支柱（post )放置在 長度即可曰。曰 父近之處，因此連接機構4係以最低限度之 又，到'裝^ | 的絕緣基板丨a 1面側全面係以樹脂層1 5形成，而背面側 1之外部連接電極6係以左右（上下）對稱之圖案
561598 五、發明說明（14) 配置，因而難以判斷電極之極性，因此最好於樹脂層1 5的 表面側形成凹部或加以印刷等，以刻印表示極性的記號。 在此，參照第6圖及第7圖說明本發明之第2實施形 ，。第6圖為剖視圖，由於俯視圖與第1圖及第4圖所示之 f 1貫施形態相同，故在此省略其說明。其係將第1實施形 =之CSP加以多晶片模組化者，其構造為將導電圖案埋入 ^為支持基板之絕緣性樹脂。 為支持基板之絕緣性樹脂2 1將半導體晶片2 3及複數 圖案（導電圖案）22完全覆蓋，於導電圖案2 2之間的 3 1中填充絕緣性樹脂2 1，而與導電圖案2 2側面的彎 (省略圖示，實際上導電圖案側面係呈彎曲狀）相嵌 固地結合。接著，利用絕緣性樹脂2 1支撐導電圖案 定於導電圖案22上之半導體晶片23亦一同被覆蓋而 型。以樹脂材料來說，環氧（epoxy)樹脂等熱硬化 I使用轉移模塑法達成，聚醯亞胺（po 1 y i m i de )樹 笨硫喊（polyphenylene sulfide)等熱塑性樹脂可 入模塑法達成。 作
個導電 隔離溝 曲構造 合而牢 22。固 共同成 性樹脂 月旨、聚 使用注
24的^緣f樹脂21的厚度係以從半導體晶片23之連接機構 度而將，部起覆蓋約5 0// m的方式加以調整。可以考慮強 處理可^厚度變厚或變薄。而且’利用退火（annealing) 在形成冬絕緣性樹脂21的表面予以平坦化。再者，特別是 的材料面積寬廣之絕緣性樹脂2 1時，由於作為導電圖案2 2 脹係數、^電消3 〇及形成絕緣性樹脂2 1之模塑樹脂之熱膨 、或進行迴焊（ref low)後溫度降低時之成型收縮率
561598 五、發明說明（15) yr pi 士口J ’而會導致導電箔3 〇發生翹曲。亦即， 树^ 2 1表面發生翹曲的情形，而藉由退火處 化。 連接機構2 4連接有半導體晶片2 3之各電 電圖案2 2。藉由利用熱壓方式之球形接合或 式之楔形接合，一次進行引線接合，將輸入 塾Ial ' la2、Ibl、Ib2，並將控制端子用電 出端子用電極焊墊〇 a、〇 b，以及控制端子用 別與所對應的導電圖案2 2相連接。 導電圖案2 2係埋入於絕緣性樹脂2 1，且 體晶片2 3外周之電極焊墊相對應設置。於固 沒有相當於習知的島部之部分，半導體晶片 性黏著劑5 0而固定於1支導電圖案2 ( 2 c )上。 如第7 ( B )圖所示，導電圖案2 2為導電辖 述）。設有隔離溝3 1之導電箔3 〇係藉由研磨 刻、雷射蒸發金屬等方式，以化學性及/或 背面，而分離成導電圖案2 2。藉此，於絕緣 成露出導電圖案2 2之背面的構造。填充於隔 性樹脂2 1的表面及導電圖案2 2的表面實質上 構造。 半導體晶片2 3由於與第1實施形態相同 述，不過，在此為化合物半導體開關電路装 半絕緣性的GaAs基板。由於係雙聯開關電略 制端子C11 - 1、輸出端子〇 υ τ a、〇 u T b、控制i 為抑制絕緣性 理予以平坦 極焊墊及各導 利用超音波方 端子用電極焊 極焊墊C1，輸 電極焊墊C2分 與配置於半導 疋區域中，並 2 3係利用絕緣 3 0 (容後詳 、研削、蝕 物理性地去除 性樹脂2 1中形 離溝3 1之絕緣 會形成相同的 ’故不再贅 置’背面形成 裝置，將與控 哉子ctl-2、輸
314083.ptd 第21頁 561598
^端子INa卜INb卜INa2、INb2相連接之8個電極焊墊 =:曰片外周的方式配置於晶片*面。利用絕緣性 晶片固定於導電圖案22c上，且利用連接機構24將各電^ ，焊塾及導電圖案22予以連接。又，導電圖案22、半 曰同曰=23的固定區域以及連接機構24的固定位置與第镧相
外部連接電極2 6係利用光 各導電圖案2 2，將所希望之位 配置。藉此’於黏結時，由於 有可以按照原狀地水平移動且 之特徵。 阻劑2 7覆蓋作為導電圖案之 置予以開口，且供應焊錫而 焊錫等之表面張力，因而具 自動對位（self-alignment) 第7圖係表示形成導電圖案之導電箔3 〇。導電箱3 〇的 厚度若考慮之後的蚀刻作業’則以約1 〇 # m至3 0 〇 # m為 宜，而在此係採用70/z m( 2盎司）的銅箔。不過，無論是 3 〇 0// m以上或1 m以下，只要可以形成較導電箔3 〇的厚 度為淺之隔離溝3 1即可。藉此，在長方狀導電箔3 〇形成多 數固定區域之複數個（在此為4至5個）方塊（block) 3 2會隔 開排列（第7(A)圖）。 9
第7(B)圖係表示具體的導電圖案22。本圖係第7(A)圖 中所示之1個方塊3 2的放大圖。以虛線表示之部分係i個封 裝區域1 0，在1個方塊3 2中以矩陣狀排列多數個導電圖案 22。導電圖案22係至少將形成導電圖案22以外的區域之導 電箔3 0予以蝕刻，並形成隔離溝3 1而設置。考慮焊材的黏 著性、搭接性、電鍍性而選擇該導電箔3 0的材料，以材料
314083.ptd 第22頁 561598 五、發明說明（17) ^ " ----- _ =，，採二以Cu(銅）為主材料之導電猪，以A1(銘）為 二之V電泊或由Fe-Ni (鐵-鎳）等合金而構成之導電箔 二而=，由於可以利用蝕刻方式形成導電圖案^，故 。巾田名小圖案間之距離，1非常有助於封裝體之小型 來 材 等 以 化 y ΐ 2實施形態之特徵係在覆蓋絕緣性樹脂以之 形成導電圖案22之導雷笔& 4· 以 板之導雷松& 3 0作為支持基板，而作為支拄| 板之導電泊3 〇係作為電極材料兩 又待基 節省構成材料以進行作業而、才料。因此，具有可 此外，由於隔離溝31形2道且可降低成本。 度，導電箱30不會個別分離電Μ 30之厚度淺之深 為片狀的導電箔30以整體處理：：：：案22。0此，會视 塑時’搬送至模具或安裝至：：有將絕緣性樹脂21模 徵。 槟具的作業變得非常容易之特 又’於本實施形態中就導 過，當基板係由矽晶圓、陶：：30的情形加以說明，不 亦同。 ΡΊ是基板、銅框等材料所構成時 路梦：且甘可以女裝之元件並不限於化合物半導體„ 晶片電容器、“電阻、以戍半導體晶片， 货會受厂子，不過CSP(晶片尺寸封裝，Chip sJe雜然厚 ackage)、BGA(球柵陣列型封裝， 朝下的半導體元件等表面安^ Γ1 Array)等面 再者參照第8圖說明本發明之第3實施形態
561598 五、發明說明（18) 本實施形態表示藉由切換與導電圖案2卜2 $接=構4的固定位置（連接處），以切換與電極接之 接之輸入端子之構造。本實施形態之導目連 示，亦即，將i支導電圖案Μ晶片3下方以=门斤 2b的方式延伸，且於導電圖案“的兩端露出。*同之 :導ίΐ: mi子用電極焊墊Ia2之連接機構與：近 與Λ?案2c的起始點側相連接。藉：= f Η電t 一曰一片所對應之端子用電極焊墊之排列順序 目3將::：：i 5 7種排列順序為正的開關電路裝置、。 方延用的導電圖案在晶片下 導電圖荦，雖A iH η 而，精由切換連接機構所連接之 導ΐ圖案#為相同之晶片圖案 部連接電極6可以成為正反 J Π之V電圖案，但外 地切換晶片上之電極焊塾 、。亦即，可以簡單 之端子的排列順序相同之=列順序以及對應於電極焊塾 案。因此，具有只利用+ f，以及已切換排列順序之圖 可簡單地| m 換連接機構之連接處的方法，即
J間早地在封裝體内切換R 對應使用者之需求之優點。Μ°旒路徑，且可迅速且彈性地 【發明之功效】 本發明之特徵在於，將 方以繞過其他導電圖案之方 ^電圖案在半導體晶片下 進行引線接合。 ’延伸且露出’並在該露出部 , 可以會王目户从 、 在使用者側安裝時之所佔面積 藉此，第， 314083.ptd 第24頁 561598 五、發明說明（19) 之小型化。由於以往必須在使用者側將RF信號路徑交叉設 定’故導致在使用者側基板的佔有面積較大，或是於設計 基板時有所限制等問題。不過，根據本發明之構造，由於 可以在進行C S P技術之封裝體内實質上將配線交叉，使用 者側可以按照原狀安裴，故具有對於安裝時之小型化大 貢獻之優點。 片及 擇需 極焊 的晶 機構 關電 於只 號路 故具 點0 第二 導電 要切 墊之 片圖 之連 路裝 要利 徑實 有可 ’利用引線接合之固定 圖案，可以簡單地達成 換之導電圖案之任一方 輸入端子的排列順序。 案）以及相同導電圖案 接處，即可實現一種可 置。具體而言，在進行 用變更搭接位置之方法 質交叉之圖案及未交叉 迅速、低成本、且彈性 輸入端』 "、 π用 ，可以正反切換對應灰 雖為相同晶片圖案（― 但是只要利用切換連 切換RF信號路徑 1工 < 雙靡 CSP技術之封裝體内 ，即可以實現—_ d，
種將R 之圖案的開關電路i 地對應使用者夕+ ~ 3 可之需求白^
561598 圖式簡單說明 【圖式簡單說明】 第1 (A)、（B)圖係說明本發明之俯視圖。 第2圖係說明本發明之斜視圖。 第3圖係說明本發明之俯視圖。 第4圖係說明本發明之（A)俯視圖及（B )方塊圖。 第5圖係說明本發明之（A)剖視圖及（B)俯視圖。 第6 ( A)、（ B)圖係說明本發明之剖視圖。 第7(A)、（B)圖係說明本發明之俯視圖。 第8圖係說明本發明之俯視圖。 第9圖係說明習知技術之電路圖。 第1 0圖係說明習知技術之俯視圖。 第1 1圖係說明習知技術之（A )俯視圖及（B )剖視圖。 第1 2 ( A )、（ B )圖係說明習知技術之俯視圖。 第1 3圖係說明習知技術之方塊圖。 1、 1 2 2絕緣基板 2、 22、 2a至2h、 22c導電圖案
3、 2 3、 1 1 9半導體晶片 4、 2 4、1 3 7連接機構 5 ^ 133 通孔 6、 26、134、134a 至 134h 外部連接電極 10 封裝區域 11 半導體晶片固定區域 12 連結部 15 、1 3 8樹脂層 21 絕緣性樹脂 27 光阻劑 30 導電箔 31 隔離溝 314083.ptd 第26頁 561598 圖式簡單說明 3 2 方塊 77 閘極金屬層 1 2 0封裝區域 1 2 5島部 1 2 8第2連結部 1 3 0第4連結部 1 3 2共通連結部 1 5 0封裝體 50 絕緣性黏著劑 7 8 焊墊金屬層 1 2 4切割線 1 2 7第1連結部 1 2 9第3連結部 1 3 1第5連結部 135、 135a至135h導電圖案部
314083.ptd 第27頁

Claims (1)

  1. 561598 六 申請專利範圍 ____ ——種半導體裝置，其係具備有：絕緣 於表面具有複數個電極焊墊之半曰二， 設於前述基板且分別與前述複 :=二 應之導電圖案； 1U電極焊墊相對 連接前述複數個電極焊墊及前述道予 機構；以及 別述導電圖案之連接 ^ ^別與前述導電圖案相對應之外、查姐 特徵為： p哗連接電極；其 利用絕緣性樹脂將前述半導體曰 ，前述導電圖案上，前述至少—個=固定於至少一 =接電極•分作為起端，通過前=圖，將前述外 日日片的端部露出並伸 述日日片下方而從該 定於該露出部。 翊，而將前述連接機構固 如申請專利範圍 體晶片#由北第1項之+導體裝置，苴中兑 月係由背面為半絕緣性之化人鉍/、中，刖述半導 ^ ° ^ 化σ物半導體基板所構 4 列順序以：：相連接，而將至少2個前前述電極 排别，及與該電極焊墊對痛夕二 迷電極焊塾之排 =序形成正反配Ϊ墊對應之-述外部連接電極之 少1個^專番利範圍第1項之半導體裝置， 電圖案延伸且其中，將前述i 配置於其兩側，乂二過相鄰接的其他導電圖“ 稭由切換與該至少2個4:;:連： 314083.ptd 第28頁 ^61598 六、申請專利範圍 之連接機構的位置，可 ^、、 置成正反之排列順序。：⑺述至少2個外部連接電極配 5·如申請專利範圍第丨項之 體晶片係將2個開關電路‘體裝置，其中，前述半導 開關電路裝置。 、置設置於1個晶片上之雙聯 6· 一種半導體裝置，其係 於表面具有與2個輪出有/絕/緣基板； 入端子相對應之複數個子、2個控制端子、4個輸 片； 革極焊墊之化合物半導體晶 之導ίίΐ前述基板上且分別與前述電極焊塾相對應 以及連接前述電極焊塾及前述導電圖案之連接機構； 分別與前述導電圖案相對應，且 之外部連接電極；其特徵為： 】达各^子 利用絕緣性樹脂將前述化合物半導 一個前述導電圖案上，前述一個導電圖案二於 部連接電極部分作為起端，通過前述晶片=則述外 晶片的端部露出並延伸至尾端’而將前 ：邊 定於該露出部。 4連接機構固 7 ·如申請專利範圍第6項之半導體裝置，其中，且 設置與前述導電圖案相對應且貫穿前述絕緣基%備有·· 孔’且與該通孔相對應而設置於前述絕緣=反之通 的外部連接電極。 土板之背面
    314083.ptd 561598
    種半導體裝置，其係具備有：絕緣樹脂； 埋入於該絕緣樹脂，且於表面具有與 2個控制端子、4個輸入端子相對應之 斗塾之化合物半導體晶片；
    &八於前述 對應之導電圖案； 2個輸出端 複數個電極 且为別與别述電極焊塾相 機構 連接前 ;以及 述複數個 電極焊墊及前述導電圖案之連接 之外部 利 一個前 接電極 的端部 該露出 I·如申請 利用前 述電極 列順序 序形成 0 ·如申請 ϊ i ϊ ϊ導ϋ案相對應’且作為前述各端子 要冤極，其特徵為： Ξίϊ Ξ ί脂將前述化合物半導體晶片固定於 部分作：起i ’前述一個導電圖案係將外部連 露出並延過前述晶片了彳而從該晶片 部。 至尾端，而將前述連接機構固定於 項或第8項之半導體裝置，其中， 焊塾之一冓將前述導電圖案之前述露出部與前 以及與該^相連接，而將2個前述電極焊墊之排 正反^ °置。。極焊塾相對應之前述端子之排列順 專利範圍第q 端子。 項之半導體裝置，其中，前述端子 專利範圍第斗、# 1個導電圖安或第8項之半導體裝置’其中’ β -、延伸且配置於相鄰接之其他導電圖 為輪入 1 ·如申請 將前述
    561598 六、申請專利範圍 案之兩側，藉由切換與該2個導電圖案相連接之連接機 構的位置，可將前述端子中之2個端子配置成正反之排 列順序。 1 2 .如申請專利範圍第1 1項之半導體裝置，其中，前述2個 導電圖案與輸入端子相對應。 1 3 .如申請專利範圍第6項或第8項之半導體裝置，其中， 前述化合物半導體晶片之背面為半絕緣性基板。 1 4.如申請專利範圍第6項或第8項之半導體裝置，其中， 前述化合物半導體晶片係將2個開關電路裝置設置於1 個晶片上之雙聯開關電路裝置。
    314083.ptd 第31頁
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