TW516160B - Planar and densely patterned silicon-on-insulator structure and process of fabricating - Google Patents
Planar and densely patterned silicon-on-insulator structure and process of fabricating Download PDFInfo
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- TW516160B TW516160B TW089100846A TW89100846A TW516160B TW 516160 B TW516160 B TW 516160B TW 089100846 A TW089100846 A TW 089100846A TW 89100846 A TW89100846 A TW 89100846A TW 516160 B TW516160 B TW 516160B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76278—Vertical isolation by selective deposition of single crystal silicon, i.e. SEG techniques
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Description
516160 A7 B7 五、發明說明( 發明領域: 本發明係有關於一種絕緣層上含矽(silicon_on_ inW; S〇I)之結構,特別是一種平坦且緻密之圖案化 SOI結構及其製造方法。 發明背景 : 圖案化SOI(S1hc〇n-〇n-insulat〇r)結構包含s〇I區域以 及非SOI(或是塊狀)區域。圖案化s〇I結構係用於同時需 要傳統元件與SOI元件之電路,這些電路包含(例如)合併 式邏輯動態隨機存取記憶體(Merged Logic Dynamic Random Access Memory ; ML-DRAM)電路。 一種製造圖案化S0I晶圓的製程牽涉到將系晶碎選 擇性地沉積(選擇性羞晶碎製程)於已形成之溝渠中。於石夕 基板中蝕刻狹窄溝渠之能力的進步增加了選擇性蟲晶石夕 製程的重要性。如果能成功地以石夕材質填滿這些溝渠,則 有可能形成由絕緣層(例如氧化物)所緊密隔離之矽島。 形成由絕緣層(例如氧化物)所緊密隔離之矽島的第一 步驟係形成溝渠。在此步驟中,選擇性地將s〇i基板向下 触刻至基底層的表面以形成溝渠,該基底層的表面係欲為 非S〇I基板處。接著,選擇性地以蟲晶碎填滿這些溝渠。 該方法係選擇性地使磊晶矽成長於曝露之矽層上,並 且該曝路(碎層王要是位於該蝕刻所形成之溝渠底部曝 路的矽日日圓上。當具有南表面遷移率之矽原子移動至有助 於成核之單一矽結晶處時,選擇性的磊晶矽沉積才可以形 第2頁 本纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----丨丨丨一卜丨丨臻 (請先閱讀背面之注意事項再填寫本頁)
訂---------線J 經濟部智慧財產局員工消費合作社印製 516160 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明() 成。由於此種選擇性羞晶矽製程,該溝渠會被矽填滿。所 得結構至少包含一 S ΟI區域以及一具有填矽溝渠之非s〇J 區域。 不幸地’在形成選擇性磊晶矽製程時會遭遇數種問 題。其中之一是受損之矽晶層的形成,並且此問題是由兩 個或多個生成源(source of growth)所導致的。當溝渠中之 蟲晶碎生成時,以單一生成源來長矽是非常合宜的。磊晶 石夕製程的目的之一是有效地以與底層矽晶圓晶格結構相 同之碎層將溝渠填滿,以便使填入溝渠之矽層可為矽晶圓 之延伸。當兩個或多個生成源同時存在時,因為矽層傾向 於以不同速率及方向成長,所以所得之磊晶矽會受損。如 此一來,便無法得到所要的均勻矽晶結構。 第二個問題是凸塊(bump)的形成。當磊晶矽生成於溝 渠側壁之矽層部份時,會有凸塊形成於s〇I區域與非s〇I 區域 < 間,而此凸塊會造成數種缺點。最嚴重的後果是形 成小而緻密之圖案化so;[及非s〇I區域的能力會降低,並 且,這些凸塊會妨礙後績的平坦化步驟,迫使成本及時間 耗費於額外的製程步驟上。 由以選擇性磊晶矽填滿溝渠的缺點可看出仍需將溝 渠側壁之矽層部份的磊晶矽清除。為克服選擇性磊晶矽的 缺點,本發明提供一種新的製程,其目的之一是提供一種 以選擇性羞晶妙填滿溝渠之製程,該製程可形成與底部碎 層相同足想要的均句結晶結構,並且不會產生凸塊於s〇i 區域與非SOI區域之間。 第'3頁 本紙張尺度適用中國國家標準(CNS)A4規格(21Q x 297公g------- (請先閱讀背面之注意事項再填寫本頁) 訂: •線- 516160 經濟部智慧財產局員工消費合作社印制衣 A7 ------— ___B7____ 五、發明說明() 形成一溝渠底部氧化層以及一溝渠側壁氧化層; (c) 形成保護性側壁於該溝渠側壁上,該保護性側 壁延伸於溝渠側壁氧化層之上,並且該保護性側壁位 於邵份該溝渠底部氧化層上; (d) 移除所有不位於該保護性側壁底部之溝渠底 部氧化層;且 (e) 以一半導體層填入該溝渠至至少該上表面。 可以認知的是前述一般性的說明以及接下來的詳細 說明僅係範例,而非用以限定本發明。 圖式簡單說明: 閱讀詳細說明時伴隨下列圖示可對本發明有最佳的 了解’必須強調的是,圖示中的特徵並非按照實際比例, 相反地’為清楚說明,不同特徵的尺寸已被任意地擴張或 是減少。此圖示包含下列數圖: 第1圖係一 SOI結構之示意圖,該S0I結構具有矽晶圓、 氧化層、矽層、保護性氧化層以及氮化層。 第2圖係s ΟI結構之示意圖,其中該氮化層、該保護性氧 化層、該碎層該以及氧化層已被移除以形成一溝 渠。 第3圖係第2圖之S ΟI結構的示意圖,其中一氧化層已形 成於該溝渠底部以及側壁矽部之上而形成一溝渠 底部氧化層以及一溝渠側壁氧化層。 第4圖係第3圖之SOI結構的示意圖,其中一保護性側壁 第5頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) « n n ϋ n n n n n n n n n · n u II ϋ n I n 一<6, · n n n ϋ n [i n I n If n n D n n n I I n n n n I n I 1 n n I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 516160 A7 B7 五、發明說明() 已形成於該溝渠側壁上。 第5圖係第4圖之SOI結構的示意圖,其中不位於保護性 側壁下方之部份該溝渠底部氧化層已被移除。 第6圖係第5圖之S 01結構的示意圖,其中該溝渠已被一 半導體層填滿。 第7圖係第6圖之SOI結構的示意圖,其中該氮化層、該 保護氧化層、部份該保護性側壁以及部份該半導體 層已被移除。 第8圖係第7圖之S 01結構的示意圖,其中該溝渠底部氧 化層、該溝渠側壁氧化層以及該保護性側壁已被移 除而形成一填滿氧化物之溝渠。 圖號對照說明: 1 基板 10 矽 晶 圓 12 氧 化 層 14 矽 層 16 保 護 氧 化 層 18 氮 化 層 20 曝 露 表 面 22 溝 渠 24 溝 渠 側 壁 25 側壁 矽 部 26 溝 渠 底 部 28 溝 渠 底 部 氧化層 30 溝 渠 側 壁 氧化層 32 保 護 性 側 壁 34 半 導 體 層 36 氧 化 物 區 域 38 非 SOI 區 域 40 主 動 SOI 區域 發日 月詳 細 說 明 第6頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) n In HI ⧧ I iai 1 I I n i an n n n_· I n j -V-口 矣 ^ (請先閱讀背面之注意事項再填寫本頁) 516160 A7 五、發明說明() 本發明將參考上述圖示說明之, ” τ布目问〈圖號 係指這些圖示中相同的元件。這些圖示旨在以範例= (並非限足),並且使本發明之設備易於解釋 請參閱第1圖,實施本發明之第一步驟係取得—基板 1,該基板1包含一矽晶圓10、一形成於矽晶圓1〇之上的 氧化層12、一矽層14以及一氮化層18。該基板1(特別是 指基板1上 < 氮化層18)具有一曝露表面2〇。氮化層18 係自習知技術所常見的氮化層中所選出,例如氮化矽或是 氮氧化物。在一較佳實施例中,係以氮化矽形成該氮化層 18° 該基板1亦包含一保護氧化層1 6,其沈積於矽層i 4 之上。保護氧化層1 6可保護矽層1 4不因氮化層1 8的形 成而損傷。在一較佳實施例中,該氧化層1 2的厚度約為 220nm至400nm;該矽層14的厚度約為100nm至300nm ; 該保護氧化層1 6的厚度約為5 nm至1 5 nm ;該氮化層1 8 的厚度約為220nm至500nm。形成基板1所用之技藝係為 習知,並且並非本發明之關鍵。 本發明之下一步驟係於第1圖所示之結構的非SOI區 域中形成溝渠,其係藉由傳統技術,例如罩幕及蚀刻技 術。如第2圖所示’形成一溝渠22,該溝渠22自該基板 1的曝露表面2 0向矽晶圓1 〇延伸。 該溝渠22具有側壁24以及底部26,並且侧壁24以 大致垂直該曝露表面2 0的方式形成是較佳的。該溝渠側 壁24以乾蝕刻技術蝕刻是較佳的。適當的乾蝕刻技術包 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) --------丨!丨丨€.丨丨 (請先閱讀背面之注意事項再填寫本頁)
丨訂---------線J 經濟部智慧財產局員工消費合作社印製 516160 A7 _B7_ 五、發明說明() 護性側壁3 2移除以形成溝渠,之後該溝渠將被氧化物填 滿。 雖然以上之示範及說明係參考特定實施例,但是其並 非旨在將本發明限定於詳細說明中之細節。當然在與本發 明專利申請範圍等效之領域及範圍且不悖離本發明之精 神下仍然可進行不同改良。 (請先閱讀背面之注意事項再填寫本頁) —訂---------線! 經濟部智慧財產局員工消費合作社印製 第12頁 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 516160 A8 B8 C8 D8 六、申請專利範圍 少包含一氮化矽層。 5 .如申請專利範圍第1項所述之方法,其中上述形成溝渠 之步驟至少包含乾蝕刻上述基板。 6. 如申請專利範圍第1項所述之方法,其中上述形成保護 性側壁之步驟至少包含沉積一氮化層於上述溝渠側壁並 且餘刻該溝渠。 7. 如申請專利範圍第1項所述之方法,其中上述以一半導 體層填入該溝渠之步驟至少包含一選擇性磊晶製程。 8. 如申請專利範圍第7項所述之方法,其中上述半導體層 係一碎層。 9. 一種絕緣層上含硬(silicon-on-insulator; SOI)結構,該 絕緣層上含矽結構具有一表面,該結構至少包含: 一矽晶圓; 一氧化層,位於該矽晶圓上; 一矽層,位於該氧化層上; 一不含埋入式氧化物之區域,該區域係由一填入半 導體層之溝渠所定義,該溝渠由該表面延伸至該矽晶 圓,該溝渠具有一上方、一底部以及一具有側壁矽部之 側壁; 第14頁 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 516160 A8 B8 C8 D8 六、申請專利範圍 一溝渠側壁氧化層,位於該溝渠側壁之該側壁矽部 上;及 一保護性側壁,位於該溝渠側壁之上,該保護性側 壁自該溝渠上方延伸至該溝渠底部,並且該保護性側壁 位於該溝渠側壁氧化層之上。 10.如申請專利範圍第9項所述之SOI結構,其中上述半 導體層係一梦層。 1 1 .如申請專利範圍第9項所述之SOI結構,其中上述保 護性側壁係一氮化矽層。 12.如申請專利範圍第1 1項所述之SOI結構,其中上述基 板更包含一形成上述咬層上之氮化碎層。 1 3 .如申請專利範圍第1 2項所述之SOI結構,其中上述基 板於上述氮化矽層與上述矽層之間更包含一保護氧化 層。 14.一種絕緣層上含硬(silicon-on-insulator; SOI)結構,該 絕緣層上含矽結構具有一表面,該結構至少包含: 一碎晶圓; 一氧化層,位於該碎晶圓上; 一矽層,位於該氧化層上; 第15頁 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) • -- 、言· 經濟部智慧財產局員工消費合作社印製
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US09/250,895 US6180486B1 (en) | 1999-02-16 | 1999-02-16 | Process of fabricating planar and densely patterned silicon-on-insulator structure |
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US (2) | US6180486B1 (zh) |
JP (1) | JP3630401B2 (zh) |
KR (1) | KR100358630B1 (zh) |
CN (1) | CN1155073C (zh) |
DE (1) | DE10003014B4 (zh) |
TW (1) | TW516160B (zh) |
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US6180486B1 (en) * | 1999-02-16 | 2001-01-30 | International Business Machines Corporation | Process of fabricating planar and densely patterned silicon-on-insulator structure |
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US6501973B1 (en) | 2000-06-30 | 2002-12-31 | Motorola, Inc. | Apparatus and method for measuring selected physical condition of an animate subject |
US6427066B1 (en) | 2000-06-30 | 2002-07-30 | Motorola, Inc. | Apparatus and method for effecting communications among a plurality of remote stations |
US6410941B1 (en) | 2000-06-30 | 2002-06-25 | Motorola, Inc. | Reconfigurable systems using hybrid integrated circuits with optical ports |
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1999
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- 1999-12-24 CN CNB991265696A patent/CN1155073C/zh not_active Expired - Fee Related
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2000
- 2000-01-19 TW TW089100846A patent/TW516160B/zh not_active IP Right Cessation
- 2000-01-24 KR KR1020000003197A patent/KR100358630B1/ko not_active IP Right Cessation
- 2000-01-25 DE DE10003014A patent/DE10003014B4/de not_active Expired - Lifetime
- 2000-02-14 JP JP2000035433A patent/JP3630401B2/ja not_active Expired - Fee Related
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US6404014B1 (en) | 2002-06-11 |
US6180486B1 (en) | 2001-01-30 |
CN1264157A (zh) | 2000-08-23 |
JP3630401B2 (ja) | 2005-03-16 |
JP2000243944A (ja) | 2000-09-08 |
CN1155073C (zh) | 2004-06-23 |
KR20000057797A (ko) | 2000-09-25 |
DE10003014B4 (de) | 2005-06-23 |
DE10003014A1 (de) | 2000-08-24 |
KR100358630B1 (ko) | 2002-10-25 |
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