TW513791B - Modularized 3D stacked IC package - Google Patents
Modularized 3D stacked IC package Download PDFInfo
- Publication number
- TW513791B TW513791B TW90123853A TW90123853A TW513791B TW 513791 B TW513791 B TW 513791B TW 90123853 A TW90123853 A TW 90123853A TW 90123853 A TW90123853 A TW 90123853A TW 513791 B TW513791 B TW 513791B
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- carrier board
- wafer
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- board
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/01—Chemical elements
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- H—ELECTRICITY
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Description
於## Μ明係應用於新世代之半導體構裝技術,特別適合 梦任二日日片上之無線通訊與攜帶型產品。且本發明之封 'J可沿用現有之晶片設備,並依實際需要來創造 免性的層疊構裝方式。 常見的半導體構裝型態中,為增加固定區域中的集積 度’除了重新設計該晶片的規格,.提高丨/〇腳數之外,最 常採取的手段莫過於將兩顆晶片層疊於一載板上,其架構 如第一圖,主要係先將一底部設有錫球4,之載板3,( InterPoser)上以金屬線1’接合方式將已用晶片接合膠13, 貼合之第一晶片Γ作電氣接合,再用晶片接合膠23,在第翁 一晶片1’上貼一第二晶片2’ ,再由第二晶片2,之腳墊21, 上以金屬線22與載板3’作電氣接合者;另一習見的晶片 層疊封裝結構如第二圖所示,其主要係先將一底部設有凸, 塊4’之載板3’上以覆晶接合方式將第一晶片丨,之金屬凸塊 14,作電氣接合,再用晶片接合膠2 3,在第一晶片Γ上貼一 第二晶片2 ,再由第二晶片2’之腳墊21,上以金屬線22,與 載板3’作電氣接合者。 上述之白見結構技術雖可將密度提高,惟受限於結構 設計的缺失,無法多層一直往上疊,若執意層疊,則其封鲁 裝面積勢必擴大,其實際上並不可行。 本發明之首要目的係提供一種可以在不増加封裝面積 的狀態之下,不斷地多層疊高,一直增加其封裝密度,且 保有高度之可靠性。 茲配合圖式將本發明較佳實施例詳細說明如下。
513791 五、發明說明(2) 參閱第三圖(A )之本發明第一種型態之模組式三次元 晶片層疊構裝,其中包括·· 第一載板1,在其第一載板1底面設有錫球15,而在其 第一載板1正面設置第一晶片11,並使第一晶片11與該載 板作覆晶接合之電氣連接;另設一第二載板2,在其載板 底面設置第二晶片2 1 ’並使第二晶片2 1與該載板作覆晶接 合電氣連接,再以一第一可撓式電路板5於第一載板1與第 二載斤2之内侧以異方向性導電薄獏/膠1 4,24 ( A C F, Anisotropic Conductive Film/ACP,Anisotropic
Conductive Paste)工法接通為一立體構裝之基本結構丨 者0 續請參照第三圖(B) 一第三晶片31成為第一延伸結構厂其一中 = 充當一載板’並在其上設置-第三晶片 4 1 〃之作覆晶接合之電氣連接者。 構參另照Λ第〜圖(C)所示’前述第三圖⑻之第一延伸结 霉了再另§又一第三載板4〇,並在 甲、口 片41與之連接,之後以一 载板底侧設一第四晶 ;第三載板4。之内侧以異方:性板6於第二載板2 通,^,一第二延伸結構4者。 4骐/膠工法34, 44接 構的ίί : ίΪί第二延伸結構4並不限定為二層基本社 合;备:至可以在空間條件的充許下,杯立Wr 構上:^上述之第1伸結構3除了可以二"Λ 之外亦可實施在第二延伸結構4之Γ構在基本結 513791 五、發明說明(3) 又如第四圖(A)所示出之本發明的另一實施例7,其係 為I發a月第二型態的模組式三次元晶片層疊構裝,其中包 括: 第—載板71 ’在其第一載板71底面設有錫球716,而 在其第一載板7 1正面設置第一晶片7 j 1,並使第一晶片7 i i 與δ亥載板作打線接合之電氣連接;另設一第二載板72,在 其載板底面設置第二晶片721,並使第二晶片721與該載板 作打線接合電氣連接,再以一第一可撓式電路板75於第一 載板71與第二載板?2之内側以異方向性導電薄膜/膠了丨5, 725工法接通為一立體構裝之基本結構者。 ’續請參照第四圖(Β)所示,上述之基本結構可在第二 載板頂面再新增一第三晶片731成為第一延伸結構73,· 其中藉第二載板72頂面充當一載板,並在其上設置一第三 晶片73 1與之作打線接合之電.氣連接者。 睛參照第四圖(C )所示,前述第四圖(β )之第一延伸結 構73可再另設一第三載板74〇,並在該載板底侧設一第四 晶片741與之連接,之後以一第二可撓式電路板”於第二 載板72與第三載板740之内侧以異方向性導電薄膜/ 735,745接通,組成一第二延伸結構74者。 < 另外,上述之第二延伸結構74並不限定為二層基本結 構的組合,甚至可以在空間條件的充許下,任意多層來组 合;當然,上=之第-延伸結構73除了可以架構在基本結 構上之外亦可實施在第二延伸結構74之上。 綜上所述,當知本案所發明之半導體封裝製程及其封
513791 五、發明說明(4) 裝件已具有產業利用性、新穎性與進步性,符合發明專利 要件。惟以上所述者,僅為本發明之較佳實施例而邑,並 非用來限定本發明實施之範圍。即凡依本發明申請專利範 圍所做的均等變化與修飾,皆為本發明專利範圍所涵蓋。
513791 圖式簡單說明 第一圖係習知二次元晶片堆疊構裝示意圖。 第二圖係另一習知二次元晶片堆疊構裝示意圖。 第三圖A係本發明之覆晶式晶片接合型態基本結構示意 圖。 第三圖B係本發明之覆晶式晶片接合型態第一延伸結構示 意圖。 第三圖C係本發明之覆晶式晶片接合型態第二延伸結構示 意圖。 第四圖A係本發明之打線式晶片接合型態基本結構示意 圖。 第四圖B係本發明之打線式晶片接合型態第一延伸結構示 意圖。 ^ 第四圖C係本發明之打線式晶片接合型態第二延伸結構示 意圖。 習用圖式標號 1 ’ ·第一晶片 1 1 ’ ·腳墊1 2 ’ .金屬線 13’ .晶片接合膠14’ .金屬凸塊 2 •第二晶片 21’·腳墊22’.金屬線 23’ .晶片接合膠 3’ ·載板 4 ’ .錫球
513791 圖式簡單說明 5’ .晶片封裝膠 本發明圖式標號 1. 第一載板 11.第一晶片 1 3.填膠 1 5.锡球 2. 第二載板 21· 第二晶片 2 3.填膠 3. 第一延伸結構 31.第三晶片32.金屬凸塊 3 3.填膠 4. 第二延伸結構 40·。第三載板 * 4 1.第四晶片 4 3.填膠 5. 第一可撓式電路板 6. 第二可撓式電路板 7. 另一實施例 71.第一載板 7 11 ·第一晶片 1 2.金屬凸塊 14.異方向性導電薄膜/膠 2 2 .金屬凸塊 < 24.異方向性導電薄膜/膠 34.異方向性導電薄膜/膠 4 2..金屬凸塊 44.異方向性導電薄膜/膠 71 2.腳墊 713.金屬線 71 4.封裝膠 715.異方向性導電薄膜/膠71 6.錫球
513791 圖式簡單說明 72 2.腳墊 72 4.封裝膠 72. 第二載板 721.第二晶片 723.金屬線 725.異方向性導電薄膜/膠 73 2.腳墊 734.封裝膠 73. 第一延伸結構 7 3 1.第二晶片 7 3 3.金屬線 735.異方向性導電薄膜/膠 74. 第二延伸結構 740. 第三載板 74 2.腳墊 744.封裝膠 741. 第四晶片 7 4 3.金屬線 745.異方向性導電薄膜/膠 75. 第一可撓式電路板 76. 第二可撓式電路板
第10頁
Claims (1)
- 513791 ___案號 90123853__9·月10 S-^-- 六、申請專利範圍 1 . 一種模組式三次元晶片層疊構裝,其中包括: 第一載板,在其載板上可設置第一晶片,並使第一晶片 與該載板作電氣連接,另設一第二載板,在其載板底面 設置第二晶片,並使第二晶片與該載板作電氣連接,續 以一可撓式電路板於第一載板與第二載板之内側以異方 向性導電薄膜/膠接通為一基本結構者。 2 ·如申請專利範圍第1項所述之模組式三次元晶片層疊構 裝,其中在第一載板底面設有錫球者。 3 ·如申請專利範圍第2項所述之模組式三次元晶片層疊構 裝,其中藉第二載板頂面充當一載板,並在其上設置一 晶片與之連接者。 4·如申請專利範圍第2項所述之模組式三次元晶片層疊構 裝’其中藉第二載板頂面充當一載板,並在其上設置一 晶片與之連接,另於其載板頂面設一第三載板,並在該 載板上亦設置一第三晶片與之連接,再以一可撓式電路 板於第二載板與第三載板之内侧以異方向性導電薄膜/膠 接通為一層疊式延伸結構者。 5 ·如申請專利範圍第1項所述之模組式三次元晶片層疊構 裝’其中之晶片與載板間之接合係以覆晶接合型態者。 6·如申請專利範圍第1項所述之模組式三次元晶片層疊構 裝’其中之晶片與載板間之接合係採用打線接合型態者。
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TW90123853A TW513791B (en) | 2001-09-26 | 2001-09-26 | Modularized 3D stacked IC package |
US10/156,120 US20030059721A1 (en) | 2001-09-26 | 2002-05-29 | Fabrication method of semiconductor |
US10/161,744 US20030057540A1 (en) | 2001-09-26 | 2002-06-05 | Combination-type 3D stacked IC package |
JP2002172815A JP2003110092A (ja) | 2001-09-26 | 2002-06-13 | モジュールタイプの三次元チップの積み重ね構造 |
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TW90123853A TW513791B (en) | 2001-09-26 | 2001-09-26 | Modularized 3D stacked IC package |
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WO2017024674A1 (zh) * | 2015-08-10 | 2017-02-16 | 成都锐华光电技术有限责任公司 | 基于柔性基板的三维芯片堆叠封装结构及封装方法 |
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US6906416B2 (en) * | 2002-10-08 | 2005-06-14 | Chippac, Inc. | Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package |
US20040264148A1 (en) * | 2003-06-27 | 2004-12-30 | Burdick William Edward | Method and system for fan fold packaging |
KR100564585B1 (ko) * | 2003-11-13 | 2006-03-28 | 삼성전자주식회사 | 이중 스택된 bga 패키지 및 다중 스택된 bga 패키지 |
US20070158811A1 (en) * | 2006-01-11 | 2007-07-12 | James Douglas Wehrly | Low profile managed memory component |
US7508058B2 (en) * | 2006-01-11 | 2009-03-24 | Entorian Technologies, Lp | Stacked integrated circuit module |
FR2905520A1 (fr) * | 2006-09-04 | 2008-03-07 | St Microelectronics Sa | Boitier semi-conducteur a composants inverses et procede de fabrication d'un tel boitier |
KR20090032845A (ko) * | 2007-09-28 | 2009-04-01 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조방법 |
JP2010080943A (ja) | 2008-08-27 | 2010-04-08 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
US9269646B2 (en) | 2011-11-14 | 2016-02-23 | Micron Technology, Inc. | Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same |
CN104821306A (zh) * | 2015-04-28 | 2015-08-05 | 上海凯虹科技电子有限公司 | 超小型封装方法及封装体 |
CN108109949B (zh) * | 2017-12-22 | 2019-07-05 | 华中科技大学 | 一种芯片的封装方法及封装结构 |
CN111093316B (zh) * | 2018-10-24 | 2021-08-24 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制作方法 |
CN110459492B (zh) * | 2019-08-15 | 2024-06-14 | 许昌市森洋电子材料有限公司 | 一种半导体致冷件封边装置 |
US12040282B2 (en) | 2021-10-01 | 2024-07-16 | Microchip Technology Incorporated | Electronic device including interposers bonded to each other |
WO2023055430A1 (en) * | 2021-10-01 | 2023-04-06 | Microchip Technology Incorporated | Electronic device including interposers bonded to each other |
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US5944222A (en) * | 1994-04-08 | 1999-08-31 | Ing. Erich Pfeiffer Gmbh | Tamper evident discharge apparatus for flowable media |
US5994222A (en) * | 1996-06-24 | 1999-11-30 | Tessera, Inc | Method of making chip mountings and assemblies |
US6479887B1 (en) * | 1998-08-31 | 2002-11-12 | Amkor Technology, Inc. | Circuit pattern tape for wafer-scale production of chip size semiconductor packages |
KR20010009350A (ko) * | 1999-07-09 | 2001-02-05 | 윤종용 | 기판이 없는 칩 스케일 패키지 및 그 제조방법 |
KR100391094B1 (ko) * | 2001-02-22 | 2003-07-12 | 삼성전자주식회사 | 듀얼 다이 패키지와 그 제조 방법 |
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WO2017024674A1 (zh) * | 2015-08-10 | 2017-02-16 | 成都锐华光电技术有限责任公司 | 基于柔性基板的三维芯片堆叠封装结构及封装方法 |
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US20030057540A1 (en) | 2003-03-27 |
US20030059721A1 (en) | 2003-03-27 |
JP2003110092A (ja) | 2003-04-11 |
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