TW510001B - Semiconductor device having dummy bonding wire - Google Patents

Semiconductor device having dummy bonding wire Download PDF

Info

Publication number
TW510001B
TW510001B TW088108085A TW88108085A TW510001B TW 510001 B TW510001 B TW 510001B TW 088108085 A TW088108085 A TW 088108085A TW 88108085 A TW88108085 A TW 88108085A TW 510001 B TW510001 B TW 510001B
Authority
TW
Taiwan
Prior art keywords
wiring
support plate
semiconductor wafer
virtual wiring
virtual
Prior art date
Application number
TW088108085A
Other languages
English (en)
Inventor
Satoshi Kikuchi
Koya Sakumoto
Junichi Goto
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW510001B publication Critical patent/TW510001B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06179—Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

510001 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（1 ) 發明背景 1、 發明領域 本發明係關於一種具有微間距圖樣之半導體元件。 2、 相關技術說明 最近，資訊裝備有漸趨於微縮而半導體亦要求具有小 的封裝體。小封裝體必須要求半導體晶片體積之微縮化。 當半導體晶片之體積變小時，晶片上的電路必須安排成微 間距，因此在支撐板上所提供用以安裝半導體晶片的電路 亦必安排在微間距。其結果，需要有用於接線的微連接技 術措以彼此連接半導體晶片與支樓板。在這一方面，支撐 板包括玻璃/環氧樹脂支撐板、陶瓷支撐板、引線框、TAB 膠帶或其他等等。 例如，有多種BGA型半導體封裝體已被採用，係因 為其並不昂貴且具有高品質。該等半導體封裝體係為了樹 脂屏蔽目的而經由轉移模塑獲得。轉移模塑期間會發生接 線流動（掃掠），因此由於射入樹脂的流動接線遭受移動， 結果可能造成電氣方面的斷路或短路。 在先前技術，為了防止電氣的斷路或短路之發生，接 線之長度係限制於不比預定值更長。具體言之，係設計一 種依據體積及/或圖樣可以與個別的半導體晶片相容的特 定的支撐板，因此在支撐板上的圖樣係彼此平行，藉以縮 短接線的長度，並藉以限制接線之彎曲。 然而，由於支撐板之微縮化並不若半導體晶片之微縮 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） • ϋ I I a— a^i\^ϋ I ·ϋ I n ϋ 1 ϋ I n ϋ l I I ϋ aM— I . (請先閱讀背面之注意事項再填寫本頁) 4 川υ〇ι 五、 發明說明（ 2 化那麼進步，於是有即使半導體晶片之體積雖小但支撐板 的體積卻不能微縮化的問題，因此接線的長度並不能予以 縮短。另外，其中在為了獲得微圖樣的目的而半導體晶片 的電極墊係安排成兩排的狀況下，雖然欲接至第一排電極 墊的接線變得較短，但是欲接至第二排電極墊的接線卻變 知較長。於是有了若干的問題，就是用以發展新型支撐板 所需的人力工時造成成本的增加，否則欲安置在既有支樓 板上的半導體晶片的數目會受到限制。 訂 製造一種可以安裝於BGA型半導體封裝體的而其已 漸趨於微縮化的半導體晶片是一種市場需求。為滿足此一 需求’必消除其限制半導體晶片體積的接線長度之限制， 藉此半導體晶片可以不受任何限制的安裝於支撐板上。 發明概述 本發明之目的係提供一種半導體元件，其中半導體晶 片得以不受限制的安裝於支撐板，例如在接線的長度限制 方面。 根據本發明的一方面，一半導體元件包含一支撐板、 一半導體晶片安裝於該支撐板並以接線連接半導體晶片至 支撐板、一模塑樹脂覆蓋半導體晶片、一裝設於支撐板内 而並未作為電氣作業使用的虛擬接線區、以及至少一虛擬 接線具有至少一端連接至虛擬接線區。 根據本發明的另一方面，一半導體元件包含一支撐 板、一半導體晶片安裝於該支撐板、接線連接半導體晶片 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^^υυ〇ι 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 至支撐板、一模塑樹脂覆蓋半導體晶片、一裝於半導體内 而並未作為電氣作業使用的虛擬接線墊、以及至少一虛擬 接線具有至少一端連接至虛擬接線墊。 根據本發明的另外一方面，一半導體元件包含一支撑 板、一半導體晶片安裝於該支撐板、接線連接半導體晶片 至支撐板、一模塑樹脂覆蓋半導體晶、、一虛擬接線區裝 於支撐板而並未作為電氣作業使用、一虛擬接線墊裝於半 導體晶片而並未作為電氣作業使用、以及至少一虛擬接線 具有一端連接至虛擬接線區而另一端則連接至虛擬接線 墊。 根據本發明’以這種方式該支撐*板具有一虛擬接線區 其並未使用作為電氣作業，及/或半導體晶片具有一接線 墊其並未作為電氣作業使用，其中至少一虛擬接線係連接 至虛擬接線區及/或連接至虛擬接線墊。該至少一虛擬接 線的功能至某種程度可發揮在防止電氣作業所需接線，在 進行作為樹脂屏蔽的轉移模塑期間由於熔化的樹脂之流動 而被移動至某種程度，因此避免發生電氣斷路或短路現 象。於是有可能在不必特別的縮短接線長度的情況下於支 撐板上安裝半導體晶片，並藉以獲得一種半導體元件，其 中可以沒有任何限制的承載半導體晶片。 較佳者，該支撐板係封裝體基板、引線框和支撐膠帶 中的一種。 該支撐板具有球體藉以與其他元件做電氣和機械方式 本紙張尺度過用T國國豕標準（CNS)A4規格（210 X 297公釐） ------裝·Ί'ί (請先閱讀背面之注意事項再填寫本I.') 訂----,-----n^r· 五、 發明說明（ Α7 Β7 經濟部智慧財產局員工消費合作社印製 的連接。 另外’由於通常半導體晶片係呈矩形，而至少一虛擬 接線係定位於半導體晶片的角隅或位於角隅的外側。 至少一虛擬接線包含複數的虛擬接線元體安排呈彼此 交叉。 另外’至少一虛擬接線具有直徑大於該用於適當電氣 作業所需的接線之直徑。 圖式之簡單說明 從下列較佳具體例參考所附圖式而作的說明，對本發 明將更為彰顯，附圖中： 第1圖係說明根據本發明之半導體元件在進行樹脂屏 蔽以前之正視圖； 第2圖係第1圖所示根據本發明之半導體元件在進行 樹脂屏蔽以後之部份分解透視圖； 第3圖係第1圖所示半導體元件之剖視圖； 第4A至4C圖係接線具有各種不同的迴路配置之剖 視圖； 第5圖係描述在模塑期間之樹脂流動和接線變形之剖 視圖； 第6圖係描述支撐板之剖視圖，其中具有成形的虛擬 接線區； 第7圖係半導體晶片之剖視圖，其中具有成形的虛擬 接線墊； (請先閱讀背面之注意事項再填寫本頁) 裝 -n ϋ n - 7 510001 A7 B7 五、發明說明（ 第8圖係描述一種舉例之剖視圖，其中虛擬接線單純 係由在支樓板的虛擬接線區支樓； 第9圖係描述不同的虛擬接線之剖視圖；以及 第10圖係描述另外一種不同的虛擬接線之剖視圖。 經濟部智慧財產局員工消費合作社印製 較佳具體例之詳細說明 第1圖係根據本發明的半導體元件10在進行樹脂屏 蔽前之正視圖，第2圖係該半導體元件在進行樹脂屏蔽以 後的部份分解透視圖，而第3圖則係第丨圖所示半導體元 件10之剖視圖。 參考第1至3圖，半導體元件1〇包含一支撐板12、 一女裝於支撐板12的半導體晶片14、連接半導體晶片14 至支撐板12的接線16、以及一覆蓋半導體晶片14的模 塑樹脂18。支撐板12係第2圖内半導體封裝體之基板。 支撐板可以是一種引線框或一種支撐膠帶（TAB膠帶）。 半導體晶片14具有積體電路（圖中未顯示）和連接至 .積體電路的接線墊20。支撐板12具有成形的接線區22 例如作為印刷電路圖樣之一部份。另外，支撐板12具有 連接至印刷電路圖樣之焊錫球體24。 ’ 接線16之一端係連接至接線墊20，而接線16之另 一端係連接至接線區22。因此，在半導體晶片14的積體 電路通常係經由接線16以電氣方式連接至在支撐板12的 印刷電路圖樣。在支撐板12的印刷電路圖樣係經由球體 % ^ Il〇 χ 297 ) ijr (請先閱讀背面之注意·
-Wi SH S^J -裝--- 填寫本頁) 訂·· 510001 A7 B7 五、發明說明（ 6 經濟部智慧財產局員工消費合作社印製 24以電氣方式連接至其他的元件。 根據本發明，支撐板12具有虛擬接線區22a ,其在 矩形狀的半導體晶片14的相應角隅的外側，並未作 為電氣作業使用。另外，半導體晶片14在此角隅具有虛 擬接線墊20a，其並未作為電氣作業使用。還有，虛擬接 線16a的一端係連接至虛擬接線區22a，而其另一端則係 連接至虛擬接線塾2〇a。 虛擬接線16a成列成排，作為電氣作業使用之接線16 係位於該排末端，而在排的末端並具有與接線16 一樣的 配置。在此一具體例中，兩虛擬接線l6a係安裝於半導體 晶片14的各個角隅。由於半導體晶片14的角隅通常並未 被任何元件所佔據，因此可能在角隅安裝虛擬接線16a , 而不必實質的改變半導體晶片14以及支撐板12的電路設 計。 接線16與虛擬接線16a可以由習常的接線機一起成 形。另外，接線16與虛擬接線16a赤可以用不同的配置 成形。例如，第4A圖描述接線16(以及虛擬接線16a)係 以半圓形狀成形。第4B圖描述接線16(以及虛擬接線16a) 係以矩形狀成形。第4C圖描述接線16(以及虡擬接線16a) 係以分欄狀成形。 在接線16和虛擬接線16a的接線步驟以後，則進行 轉移模塑藉以形成模塑樹脂18覆蓋半導體晶片14，隨之 以印刷結構特徵、附加焊錫球體24、以及切割或其他步 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 面 之 注 意 事
再 f k 本 頁 I 訂 A7 ^ ----------- B7 ______ 五、發明說明（7 ) 騍’藉以完成一種BGA型的半導體元件10。 --- ΙΛ» -----IAW--· L I (請先閱讀背面之注意事項再填寫本頁) 第5圖顯示在轉移模塑期間樹脂之流動。在轉移模塑 時，樹脂喷射埠係設置在支撐板12的一個位置，如圖中 箭號A和B所示，經由此，熔融的樹脂在半導體晶片u 周圍流動。如箭號β所示，在半導體晶片14角隅附近， 由於接線間的間隔較寬而樹腊之流速較快。 因此，虛擬接線16a移動至更大程度，其造成虛擬接 線16a緊密的靠近鄰近的接線16。然而，由於虛擬接線16& 並未以電氣方式連接至半導體晶片14和支撐板12之電 路，故即使虛擬接線16a與鄰近的接線16接觸將不致發 生斷路或短路現象。若虛擬接線不存在，則設置於鄰 近虛擬接線16a的接線16將以類以方式發生變形，其促 使此一接線16朝安排於其鄰近的另一接線丨6移動，而造 成接觸。 ^ 經濟部智慧財產局員工消費合作社印製 在BGA半導體元件，具有352插腳以及使用28微 米厚度和3·5毫米長度的金質接線，在轉移模塑以後，線 流動的值加以比較。當虛擬接線16a存在時，線流動的平 均值係1.27%。另一方面，在沒有虛擬接線16a時，線流 動的平均值係4.74%，其意味著根據本發明可使線流動的 平均值降低至約1/4。其中還加上最長的線長可以增加至 5毫米，而在先前技術則係限制於3 · 〇亳米。 第ό圖顯示支撐板12具有在其上面形成的虛擬接線 區22a。第7圖顯示半導體晶片14具有在其上面形成的 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 10 發明說明（8 ) 虛擬接線塾20a。在前文參考第1至5圖所說明的具體例 中’虛擬接線16a係在虛擬接線區22a與虛擬接線墊2〇a 間形成。然而，由於虛擬接線l6a並不作為電氣作業使用， 虛擬接線16a並不需要在虛擬接線區22a與虛擬接線塾20a 間形成。 例如’一方面將虛擬接線丨6a的一端連接至虛擬接線 區22a ’而虛擬接線的另一端則可以連接至一適當的位 置。另外，一方面將虛擬接線16a的一端連接至虛擬接線 墊20a，而虛擬接線i6a的另一端則可以連接至一適當的 位置。亦即，只要是在任何欲妨礙樹脂流的效應，則可以 僅只加上虛擬接線區22a或僅只加上虛擬接線墊2〇a以避 免接線流動。 第8圖說明一種案例，其中省略了在半導體晶片I# 的虛擬接線墊20a，而虛擬接線16a係僅由虛擬接線區22a 形成在支撐板12。另外，在此一案例中係以妨礙樹脂流 藉以避免接線的流動。所列入考慮的事實是，該樹脂射出 埠係裝設於支撐板12的角隅，而如第5圖箭號A和B所 示之樹脂流，若該接線區22a係裝設於支撐板12各侧的 相反端時，可以獲致最佳的效果。在此一考量下，除了前 述位置以外的任何一個位置，可以依不同的模具結構，例 如相應側的中間部份而可能會有效果。 第9圖顯示虛擬接線16a的變化。該虛擬接線16&包 含複數的接線元體16b和16c其彼此交又且係黏結至單一 510001 A7 B7 五、發明說明（9
V 虛擬墊20a以及單一虛擬接線區22a。如此造成增加接線 區作為栅壩效應的用途藉以降低接線的流動。 第10圖顯示虛擬接線16a的另一變化。該虛擬接線 16a具有較大的直徑，如此造成增加接線區作為攔壤效應 的用途藉以降低接線的流動。 如前文所述，根據本發明可以獲致一種半導體元件， 其中半導體晶片係安裝於支撐板而無需受任何限制，例如 接線長度之最小化。尤其是由提供虛擬接線，其可能藉以 降低接線之流動，因此半導體晶片可能不管晶片大小如何 皆可被安裝於半導體封裝體，如BGA型内，其結果降低 用以發展支撐板所需的人力工時藉以降低封裝體的成本。 元件標號對照 --U----------, Γ%先閱讀背面<意事項再填寫本頁) 訂- 經濟邨智慧財產局員工消費合作社印製 10 半導體元件 14 半導體晶片 16 a 虛擬接線 16c 虛擬接線 20 接線墊 22 接線區 24 焊錫球體 12 支撐板 16 接線 16b 虛擬接線 18 模塑樹脂 20a 虛擬接線墊 22a 虛擬接線區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 12

Claims (1)

  1. 經濟部智慧財產局員工消費合作社印製 申Μ專利範圍 h 一種半導體元件，包+: 一支撐板； 一半導體晶片，其係安裝於該支撐板； 接線，其係連接半導體晶片至支撐板； 一模塑樹脂，其係覆蓋半導體晶片； 一虛擬接線區，其係安裝於支撐板而並未作為電 氣作業使用；以及 至>一虛擬接線，其係具有至少一端連接至虛擬 接線區。 2. 如申請專利範圍第、丨項之半導體元件，其特徵在於支 撐板係封裝體基板、引線框、和支撐膠帶中之一種。 3. 如申請專利範圍第丨項之半導體元件，其特徵在於支 撐板具有球體用以與其他元件做電氣和機械方式的連 接。 4. 如申請專利範圍第i項之半導體元件，其特徵在於半 導體晶片通常係矩形，而該至少一虛擬接線係定位於 半導體晶片之角隅或在角隅外側位置。 5·如申請專利範圍第丨項之半導體元件，其特徵在於該 至V 虛擬接線包含複數的虛擬接線元體安排呈彼此 交又。 6·如申請專利範圍第1項之半導體元件，其特徵在於該 至少一虛擬接線具有直徑大於作為電氣作業所需接線 之直徑。 (CNS)A4 規格（210 X 297公釐） ---·--^-------mp-裝-----.---訂·-------- (請先閱讀背面之注意事項再填寫本頁) 13 丄丄 丄丄 經濟部智慧財產局員工消費合作社印製 、申請專利範圍 7. 一種半導體元件，包含-支撐板、—半導體晶片安裝 於該支撐板、接線連接半導體晶片至支撐板、—模塑 樹月曰覆蓋半導體晶片、一虛擬接線墊安裝於半導體晶 片而並未作為電氣作業使用、以及至少一虛擬接線具 有至少一端連接至虛擬接線墊。 8·如申請專利範圍第7項之半導體元件，其特徵在於支 撐板係封裝體基板、引線框、和支撐膠帶中的一種。 9·如夺請專利範圍第7項之半導體元件，其特徵在於支 撐板具有球體用於以電氣和機械方式連接至其他元 件。 ίο.如申請專利範圍第7項之半導體元件，其特徵在於半 導體晶片通常係矩形，而該至少一虛擬接線係定位於 半導體晶片之角隅或位於角隅之外側。 U.如申請專利範圍第7項之半導體元件，其特徵在於該 至少一虛擬接線包含複數的虛擬接線元體安排呈彼此 交又。 12.如申請專利範圍第7項之半導體元件，其特徵在於該 至少一虛擬接線具有直徑大於必須作為電氣作業之接 線的直徑。 13·—種半導體元件，包含一支撐板，一半導體晶片安裝 於支樓板，一模塑樹脂覆蓋半導體晶片，一虛擬接見 區女裝於支撐板而並未作為電氣作業使用，一虛擬接 線塾女裝於半導體晶片而並未作為電氣作業使用，以 ^紙張尺度適用中國國家標準㈣油規格⑵心撕
    . = ^--------t·-------- (請先閱讀背面之注意事項再填寫本頁) 着 14 丄 A8 B8 C8
    申凊專利範圍 及至少一虛擬接線具有一端連接至虛擬接線區而另一 端則連接至虛擬接線墊。 14·如申請專利範圍第13項之半導體元件，其特徵在於支 撐板係封裝體基板、引線框、和支撐膠帶中之一種。 15.如申請專利範圍第13項之半導體元件，其特徵在於支
    撐板具有球體作為至其他元件之電氣和機械方式之連 接。 16·如申請專利範圍第13項之半導體元件，其特徵在於半 導體晶片通常係矩形，而該至少一虛擬接線係定位於 半導體晶片之角隅或位於角隅之外侧。 訂 17·如申請專利範圍第13項之半導體元件，其特徵在於該 至；一虛擬接線包含複數的虛擬接線元體安排呈彼此 交又。 a如申請專利第13項之半導體元件，其特徵在於該 至少一虛擬接線具有直徑大於作為電氣作業的必要接 線之直徑。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） 15
TW088108085A 1998-05-19 1999-05-18 Semiconductor device having dummy bonding wire TW510001B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10136575A JPH11330128A (ja) 1998-05-19 1998-05-19 半導体装置

Publications (1)

Publication Number Publication Date
TW510001B true TW510001B (en) 2002-11-11

Family

ID=15178486

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088108085A TW510001B (en) 1998-05-19 1999-05-18 Semiconductor device having dummy bonding wire

Country Status (3)

Country Link
JP (1) JPH11330128A (zh)
KR (1) KR19990088347A (zh)
TW (1) TW510001B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100857494B1 (ko) * 2002-04-30 2008-09-08 삼성전자주식회사 구동 집적 회로 패키지 및 이를 이용한 칩 온 글래스액정표시장치
JP5641788B2 (ja) * 2010-05-31 2014-12-17 キヤノン株式会社 液体吐出ヘッドおよび液体吐出ヘッドの製造方法
WO2014119477A1 (ja) * 2013-01-29 2014-08-07 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及び半導体装置の製造方法
JP2017092212A (ja) * 2015-11-09 2017-05-25 株式会社東芝 半導体装置およびその製造方法

Also Published As

Publication number Publication date
KR19990088347A (ko) 1999-12-27
JPH11330128A (ja) 1999-11-30

Similar Documents

Publication Publication Date Title
US7547963B2 (en) Semiconductor device and its wiring method
JP3779789B2 (ja) 半導体装置およびその製造方法
JP3291368B2 (ja) ボールグリッドアレイ型半導体パッケージの構造
US6593169B2 (en) Method of making hybrid integrated circuit device
JP3516608B2 (ja) 半導体装置
US20080105962A1 (en) Chip package
US6483184B2 (en) Semiconductor apparatus substrate, semiconductor apparatus, and method of manufacturing thereof and electronic apparatus
EP0445726A1 (en) Lead frame having at least two islands and resin molded semiconductor device using it
EP0623954B1 (en) Molded plastic packaging of electronic devices
TW510001B (en) Semiconductor device having dummy bonding wire
JP2596615B2 (ja) 樹脂封止用回路基板
KR950012925B1 (ko) 반도체 리이드 프레임
KR100829613B1 (ko) 반도체 칩 패키지 및 그 제조 방법
TW507502B (en) Semiconductor module
TWI677956B (zh) 用於半導體封裝結構的萬用轉接電路層
US20060043612A1 (en) Wire sweep resistant semiconductor package and manufacturing method thereof
TW296473B (zh)
TW200301960A (en) Reverse wire bonding techniques
US20070164395A1 (en) Chip package with built-in capacitor structure
JP2786047B2 (ja) 樹脂封止型半導体装置
KR100216061B1 (ko) 반도체 패키지
KR20080084075A (ko) 적층 반도체 패키지
JPH0671059B2 (ja) メモリモジュール
KR100645191B1 (ko) 반도체 패키지
KR950006434B1 (ko) 리이드 프레임