TW507380B - Method for making field effect devices and capacitors with thin film dielectrics and resulting devices - Google Patents

Method for making field effect devices and capacitors with thin film dielectrics and resulting devices Download PDF

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TW507380B
TW507380B TW089123228A TW89123228A TW507380B TW 507380 B TW507380 B TW 507380B TW 089123228 A TW089123228 A TW 089123228A TW 89123228 A TW89123228 A TW 89123228A TW 507380 B TW507380 B TW 507380B
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electrode
dielectric layer
dielectric
plasma
layer
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Glenn B Alers
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Lucent Technologies Inc
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Description

507380 五、發明說明（1) 相關申請案 本申請案為收錄於1998年四月15曰之美國專利申請案序 號〇9/〇6〇，42〇之部份接續（(：〇]：1^丨1111^1〇1^-丨1：1-031"1；)，含括 於此以供參考並主張其歸檔日期之利益。 發明領域 本發明係關於一種具有薄膜電介質及其產生裝置之製造 方法。 發明背景
場效應裝置，如場效電晶體，在近代電子中乃基本元 件。金屬氧化半導體場效電晶體（M0SFET)在製造超大規模 積體電路時乃一主要且重要的元件，且已知具有多種型式 的MOSFETs °M0SFET技術基本上其分類包含nm〇s、PM0S及 CMOS技術。NM〇S表示η通道M0S元件、PM0S表示p通道M0S元 件、而CMOS則表示η通道與ρ通道區域集積在相同晶片上之 元件。用於識別MOSFETs之其它同義字包含dm〇s (其中” d，1 表示π擴散π或’’雙擴散11 )、IGBT (絕緣閘極雙載子電晶 體）'BiCMOS (具有雙載子元件之CMOS)以及DGDM0S (雙閘 極DM0S)。 M0SFET元件一般包含一條置於源極與汲極之間的可控制 導電路徑、稱作通道。一閘極乃製於一薄介電膜上並覆蓋 該條通道。你j如，源極與汲極可為η型矽區域而通道可‘ 與其連接之ρ型區域。閘極電極可為一製於一矽氧化介電 薄層上並覆蓋通道之導電掺雜多晶矽層。 · 若沒有電壓加諸閘極，電流無法由源極流向通道或由通 507380 五、發明說明（2) -- 道流向汲極。然而，若有一足夠的正電壓加諸閘極，則有 電子導入通道區域，因而在源極與汲極之間產生一連續路 徑0 、、 電容亦為積體電路之重要元件。一般的電容器包含由一 薄介電層所隔離之第一和第二導電層。
一電容器可製於一M0S元件上以產生一記憶元件。例 如，常見於一動態隨機存取記憶體（DRAM)單元之設計包含 二轉移閘（如M0SFET)以及一具有一電容器之儲存節點=1 常見於DRAM單元之設計乃示於圖i。該單元包含一基底 12，一般由矽所構成，包含M〇SFET之源極13與 沪 區。問極架構16a、16b乃製於基底±。基底10之== 具有一場效氧化圖樣（或F〇X) 18。電容器部份4〇乃置於閘 極上’包含由介電材料薄膜層22所隔離之底部電極2〇與上 部電極21。底部電極2〇和上部電極21與交置之薄介電膜22 共同形成一電容器。一絕緣層2 4可使電容器隔離於閘極架 構 1 6 a、1 6 b 〇
積體電路之可靠運作乃依電路元件内遞增之薄介電層之 仏賴度而疋 卩現著電晶體愈變愈小且集積度愈來愈大，電 介質亦愈變愈薄。電容器與閘極電介質之厚度通常小於8〇 埃且接近5 0埃或更小。為了使積體電路工作，數千個不同 的電晶體中每一個的薄層必須提供足夠的電容值以驅動、元 件’使通道免於雜質漫移，並在其表面產生電荷陷阱。這 些尚度要求很快地超出傳統石夕氧化層之能力。小於2奈米 之矽氧化層會產生過大的漏電流。
第6頁 507380 五、發明說明（3) 於閘極電介質取代矽氧化物之努力到目前仍難令人滿 意。因為電容值不足以驅動元件，矽氧化物之相對較低的 介電常數仁3. 9使得電晶體的尺寸無法變得更小。目前正 在發展具有較高介電常數之材質。例如，氧化钽已試用於 DRAM單元之電容器部份之介電層（如圖1之層22)。然而， 在這種情況下，在較低的金屬電極（例如圖1之2 0 )與氧化 膜22之間會產生反應並使電極20產生部份氧化。此部份氧 化會在金屬電極與電介質之介面產生次氧化物。由此形成 之部份氧化層具有一高電子陷阱密度，會降低該架構之電 容值並增加漏電流。因此，需要一種改良方法，用來產生 具有高介電常數薄層之元件，特別是用於電子元件，如 DRAM單元，之電容器部份之介電常數之層。 發明概述 總言之，本發明包含一種用於製造一具有電容器部份之 電子元件之製程。一金屬膜乃沉積於一表面上，如覆蓋在 一基底上之絕緣或介電層之表面。該金屬膜可使用如光阻 或金屬餘刻之方法製作圖樣。一金屬氧化層乃沉積於該金 屬膜上並形成上部電極。該架構在沉積金屬層之後及形成 上部電極之前乃暴露於一極少（remote)的氮氣電漿中。該 電漿經由介面之氮氣合併（incorporation)大幅減少金屬 電極/電介質介面之電荷陷阱密度。 圖示簡述 本發明之優點、性質及：許多.的其它特點可經由底下詳 述之說明性具體實施例得以通盤瞭解。附圖中：
第7頁 507380 五、發明說明（4) 圖1為一 DRAM單元之圖示描述； 圖2為一流程圖，表示用來製造一具有改良式電容器架 構之電子元件之方法之步驟； 圖3為一剖面圖，描述一場效元件及一具有一改良式介 電層之電容器； 圖4為一圖示，乃四種不同元件以電壓為函數之電容 值；以及 圖5為一圖示，表示曝露於氮氣電漿之後，矽上之一介 電膜之組成深度輪靡（composition-depth profile)。 須知這些圖示的目的在描述本發明之概念且除了這些圖 表（g r a p h )之外，並未依比例描繪。 詳細發明說明 參考圖示，圖2描繪製作一具有一改良式薄膜電介質之 電子元件之步驟。如圖2之方塊A所示，第一步為提供一有 電容器架構形成其上之表面。該表面可包含一沉積於一 M0S元件上之絕緣層，例如，自一DRAM單元之電容器架構 隔離M0S元件，如圖1之一絕緣層24。 下一步驟乃示於方塊B，將一金屬層沉積在絕緣層上（例 如圖1之金屬層20)。該金屬層可包含一嫣金屬膜、一氮化 鎢膜或一矽化鎢膜。亦可使用一氮化鈦或氮化钽多晶矽 膜。該金屬層可包含一基本或二元金屬或一選自鐫、欽、 组及銦之材質組合物。該金屬層可藉由包含化學氣相沉積 法與反應性濺鍍之已知方法予以沉積。可於絕緣層2 4上製 作一所需之幾何圖樣以定義一較低之電極，應用本領域内
第8頁 507380 五、發明說明（5) 圖樣步驟 已知之圖樣技術（例如，使用光阻和金屬蝕刻 乃示於圖2之方塊c。 一較低電極之表面鈍化步驟乃揭露於美國專利 5，780，115，發佈於其它文件（park)。在文件中/純^ 驟乃施行於沉積電介質之前於矽移除固有的氧化物。化缺步 而，文件製程並不應用於金屬電極，其中氧化物之蒋然、 不重要。該製程依靠面際鈍化區域之遞增厚度，除並 成形於電漿處理期間以增加電容值，因而產生較;品域乃 件。例如，該製程達到一最小之相等之二氧化^:^元 為3奈米。 /与度，僅 再來，第四步驟（方塊D)包含沉積一具有高介 質之薄層u列如圖！之層22)。較佳地，該層 ：：材 τ#，另一高介電常數材質。該電介質可藉如 相 >儿積法（CVD)或低壓CVD (LpcvD)在金子孔 如已知於本領域之方法。沉積必須在450 t以下予二積進 行以避免較低金屬電極之氧化。 又進 一種可包含一使用氧氣或其它氧 膜處理乃揭露於美國專利安编二^广;:之電聚處理之石夕 六ua寻扪荼編唬5,486 488 曰^布於卡米樣(K一），含括於此以供參二6 = =使用f如卡米樣中之氧化氣體是有弊的，0為氧氣在 派^七1 〇n)期間會氧化較低的電極/電介質介、 5,[ έτ ^ ί- #4 φ 4 / 未衩衣程只壓縮Ta2〇5膜且未考慮 到派縮衣私對電極/電介質介面所造成的衝擊。 該介面於一第五步驟（方塊E)予以穩定，包含隨後對氮
第9頁 507380 五、發明說明（6) 氣電漿之曝露。示於方塊E之步驟包含氮化該電介質介 面，亦即一氮氣電聚乃加諸電介質之上部表面。本曝露可 針對極少的微波下流電漿，例如，一加諸2陶爾且基底溫 度為1 0 0 - 5 0 0 °C( 3 0 0 °C較佳）的氮氣電漿，經由氮^的加1入 以穩定下部閘極/電介質介面。氮氣電漿；可在氧氣電#灵之 後亦於2陶爾且基底溫度為1 0 0 -5 0 0 °C ( 30 0 X：較佳）的g況 下用於壓縮介電層並減少漏電流。介電膜對一含氮氣的電 漿之曝露只會將氮氣增加至氧化物/電介質介面/圖6為二 曝露於氣氣電聚之後’石夕上之一介電膜之組成深度°輪^ # 於電介質/矽介面偵測氮離子，表示氮氣已於電漿製程 間透入該介電層並且束縳於下面的矽層以鈍化白τ '』 1 u曰田句7盘奇 氣的束縳力。鈍化與氮氣而非氧氣之這些束縳力對減緩^ 化物之成生、減少介面漏電以及增加元件之電容值、 氣 有高度的優點。此鈍化作用因而使得避免直接鈍化3 °具 極變得可能。 权低電 第六步驟（方塊F )乃沉積上部電極（例如圖i之層2工。 步驟一般包含沉積一金屬之上部電極如TiN、丁。、此 WN。沉積可用CVD或PVD達成，低於8〇〇。〇之溫产或 好是低於6 0 0 t。 X Λ好’最 上述製程可用於一DRAM單元之製造，如圖1所述， 沉積於一MOS電晶體之閘極電極上之電容器架構。妙具号 亦考量其它包含一製造電容器架構之應用'圖3為f2: 例電子兀件之剖面圖，描述一具.有改良式介電層曰只知 件1〇及電容器π，具有用於表示如圖丨之相似特0 γ文元 <^相似
第10頁 507380 五、發明說明（7) 特色。雖然不需用於本發明，在此特殊例子中，場 及電容器兩者皆製於一共用基底1 2之上，例如一 /曰 、、、Ό 日日命日日 圓。 場效元件1 0 (此處為一電晶體）本質上包含一源極丨3、 一汲極14及一通道15，其中每一個皆可包含一供自美底12 之矽摻雜區域。一閘極電極16覆蓋於通道15之上並^由一 薄介電膜17與通道互相隔離。如所繪，介電膜具有一對鄰 接閘極電極1 6 (閘極/電介質介面）與通道1 5 (電介質/ s | 介面）之主介面。該介電膜一般具有一小於約2〇〇埃的厚 度。該閘極電極1 6 —般摻雜有一薄層多晶矽以顯現導電 性。電容器11包含一對由一薄介電膜22所隔離的導電層 及21。導電層20與介電膜22之電容器架構可用上述製程製 這。該介電膜22可為一氧化鈕膜，如上所提，具有包含一 或多個Π N、TaN、W或WN之上部與下部電極。 •圖4為一圖示，表示電介質沉積於一具有一ΤίΝ/τ^%/ TiN木構之電容器上之後的電漿處理效應。曲線1表示在— ^處理膜之不同電壓下之電容值。注意該電容值乃限制在 f F/ # m2。曲線2表示一電漿處理效應，包含3〇 〇。[時 刀鐘〇2/^之應用。曲線3和4表示根據本發明當一唯〜電、 ^處理施用於第一電極時所獲得之遞增結果。曲線3表示 使用〇2電漿之後進行唯I電漿處理時電容值。曲線4表、 使用任何氧氣前施用唯化電漿處理時之電容值。可以看 i政使用一純氮氣電漿可獲得改良結果，無論是在一氡《 7 則或之後’且其結果乃動態改良（例如曲線4 )，去
507380 五、發明說明（8) 純氮氣在之前予以施加時。此處所用之字眼”純氮氣π意指 不具氧氣的氮氣，並且，當然，此領域人士瞭解一如氬氣 或氦氣之惰性氣體亦可用於此。 另外，須知上述的製程條件為示範性。氮氣回火氣體可 在0. 1至1 0陶爾的壓力下從一產生氮氣根之極小電漿源導 入（亦即方塊Ε之第五步驟）一回火室。該極小的電漿室可 在一大約2. 5 GHz的頻率下使用一微波源產生電漿。另 外，可隨著一大約1 3 MHz頻率下所施加的RF偏壓以及一包 含氮氣與氬氣或氦氣之類的惰性氣體兩者的氣體產生該電 須知上述的具體實施例乃描述性質，僅為可呈現本發明 應用之許多具體實施例中之少數。本行人士已可在不偏離 本發明之範疇與精神的條件下想出許多且多變的其它設 計0
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Claims (1)

  1. 507380 案號 89123228 Ϋ/年6月乂曰 修 ^ -¾ >. V ·，ι一 補充 六、申請專利範圍 1. 一種用於製造具有一電容器架構之電子元件^方法 包含： 於一介電材料膜上沉積一用於定義一第一電極之金屬 層；於該第一電極上沉積一第二介電層；將該介電材料膜 曝露於一純氮氣電漿中以減少位於電介質/電極介面之電 荷陷阱密度；以及於該第二介電層上沉積一第二金屬層以 定義該電容器架構之上部電極。 2. —種用於製造一具有薄介電材料膜之電子元件之電容 器架構之方法，該方法包含： (a) 提供一基底； (b) 於該基底上沉積一第一介電材料膜以定義一第一介 電層； (c) 於該第一介電層沉積一第一金屬材料層； (d) 製作該第一金屬材料層的圖樣以定義一第一電極； (e) 於該第一電極上沉積一介電材料層以定義一第二介 電層； t (f )將該第二介電層曝露於一純氮氣電漿中以減少位於 該第一電極和該第二介電層之間介面的電荷陷阱密度；以 及 (g)形成一第二電極並覆置於該第二介電層上以完成該 電容器架構。 3. 如申請專利範圍第2項之方法，其中將該第二介電層 曝露於電漿中之該步驟包含在基底溫度落於100-500 °C的 範圍時對不具氧氣之氮氣電漿之第一曝露步驟。
    O:\67\67406-910627.ptc 第14頁 507380 案號 89123228 f /年/月曰 修正 六、申請專利範圍 4. 如申請專利範圍第2項之方法，其中該第二介電層乃 一具有一介電常數大於5之金屬氧化物。 5. 如申請專利範圍第4項之方法，其中該第二介電層包 含氧化组。 6. 如申請專利範圍第5項之方法，其中將第二介電層曝 露於電漿中之該步驟包含在基底溫度落於100-500 °C的範 圍時對不具氧氣之氮氣電漿之第一曝露步驟並接著將該第 -二介電層曝露於一氧氣電漿中。 7. 如申請專利範圍第2項之方法，其中將該第二介電層 曝露於電漿中之該步驟包含對一氧氣電漿之第一曝露步驟 並接著在基底溫度落於100-500 °C的範圍時對一純氮氣電φ 漿之曝露步驟。 8. 如申請專利範圍第2項之方法，其中於該第一電極上 沉積一介電材質之該步驟包含沉積一厚度介於2-10奈米之 介電材料膜。 9. 如申請專利範圍第2項之方法，其中該第一和第二電 極乃由選自TiN、W、TaN及WN之金屬所製成。 10. 如申請專利範圍第2項之方法，其中該第二介電層包 含丁a205 。 11. 一種電子元件，具有一電容器，其包含有： 一第一電極； || 一介電層，包含有氧化鈕置於該電極上；以及 胃> 一第二電極置於該介電層上，其中： 該介電層與該第一電極間之介面包含有一過量氮離
    O:\67\67406-910627.ptc 第15頁 507380 修正 案號 89123228 六、申請專利範圍 子，以減少位於該介面之電荷陷阱密度。 12. —種場效電晶體，具有一電容器，其包含有： 一第一電極； 一介電層，包含有氧化鈕置於該電極上；以及 一第二電極置於該介電層上，其中： 該介電層與該第一電極間之介面包含有一過量氮離 子，以減少位於該介面之電荷陷阱密度。 13. —種内含電容器架構之一具有一薄介電材料膜之電 子元件中的製造方法，該方法包含： (a) 提供一包含一具有至少一閘極電極之M0S元件之基 底， (b) 將一第一介電材料膜沉積於該M0S元件上，覆蓋該閘 極電極以定義一第一介電層； (c) 將一第一金屬材料層沉積於該第一介電層上； (d) 製作該第一金屬材料層之圖樣以定義一第一電極； (e) 將一氧化钽層沉積於該第一電極以定義一第二介電 層； (f) 將該第二介電層曝露於一包含純氮氣之第一電漿及 一包含氧氣之第二電漿，其中該第一及第二電漿皆施用於 一溫度範圍落於100-500 °C之基底以減少位於該第一電極 及該第二介電層之介面之電荷陷阱密度；以及 (g) 形成一覆蓋該第二介電層之第二電極以完成該電容 器架構。 14.如申請專利範圍第13項之方法，其中該第一及第二電
    O:\67\67406-910627.ptc 第16頁 507380 修正 案號 89123228 六、申請專利範圍 漿乃依序施用，該第一電漿乃施用於該第二電漿之前。 15.如申請專利範圍第13項之方法，其中該第一及第二 電漿乃依序施用，該第二電漿乃施用於該第一電漿之前。
    O:\67\67406-910627.ptc 第17頁
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KR20010051362A (ko) 2001-06-25
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JP2001196368A (ja) 2001-07-19
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