TW507354B - Electrostatic discharge protection for salicided devices and method of making same - Google Patents

Electrostatic discharge protection for salicided devices and method of making same Download PDF

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TW507354B
TW507354B TW088102425A TW88102425A TW507354B TW 507354 B TW507354 B TW 507354B TW 088102425 A TW088102425 A TW 088102425A TW 88102425 A TW88102425 A TW 88102425A TW 507354 B TW507354 B TW 507354B
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Sheng Teng Hsu
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Sharp Kk
Sharp Microelect Tech Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Description

507354 _案號 88102425_年月日__ 五、發明說明（1) 發明所屬領域 本發明係關於積體電路，特別是關於一個結構與方法， 用來對内含自對準矽化物組件之積體電路提供靜電放電保 護。 發明背景 矽之積體電路易受到靜電放電（ESD )之損害，特別是在 該情形中：含有積體電路之裝置的使用者，在他們的身上 產生靜電，而接著與含有該積體電路之裝置相接觸；在人 體中誘發之靜電電荷，可以產生5 0 0 0伏特之數量級的電 壓；因為大部份積體電路在不高於5伏特操作，所以來自 人體之靜電放電可以使積體電路嚴重受創；在積體電路中 附上ESD保護之一種方式，係將積體電路建立在一個較不 受ESD損害影響之基板上；該積體電路可以製作在塊狀 (bulk)矽基板、矽在絕緣體上（SOI)基板、或者氧佈植隔 離（SIM0X)基板上。 靜電放電（ESD)保護通常藉由在製造過程中，加上一遮 罩步驟來提供，以避免鄰近閘極電極之汲極區的矽化；可 是，此技術不能提供完全之ESD保護，而且在製程中需要 額外之步驟、時間與花費。 發明概述 形成靜電放電保護之自對準矽化物裝置的方法，其包 括，在單晶基板上，形成一源極區、一閘極通道與一汲極 區，其中該源極區與該汲極區，係使用低摻雜密度製程以 第一種離子作佈植而形成；在閘極通道上沈積一層閘極氧 化物；遮罩至少一部份之汲極區與至少一部份閘極通道與
O:\57\57214.ptc 第 5 頁 507354 _案號 88102425_年月日__ 五、發明說明（2) 閘極氧化物層；佈植第二種離子，而在該源極區與閘極通 道之間，以及該汲極區與閘極通道之間形成一個區域，因 此而將汲極區與閘極通道隔開；以及，在該汲極區與源極 區上形成自對準矽化物層，其中該自對準矽化物層係與該 閘極通道相隔開。 本發明之一個目的，係提供一個附有堅強之ESD保護的 C Μ 0 S結構，而不需使用額外之遮罩。 本發明之另一個目的，係提供一種方法，其使用最少之 步驟製作堅強E S D保護之裝置。 附圖簡述 圖1係在一個Μ 0 S電晶體中，寄生雙載子電晶體之部分截 面圖。 圖2a與2b係附有先前技術ESD保護之雙載子電晶體的部 份截面圖，以及其等效電路。 圖3 a與3 b係根據本發明之L D D結構的部份截面圖，以及 其等效電路。 圖4描述根據本發明，建構ESD保護之裝置的一個中間步 驟。 圖5描述根據本發明，建構ESD保護之裝置的另一個步 驟。 圖6係根據本發明建構之一對CMOS電晶體的截面圖。 圖7描述根據本發明，在建構p / η接面裝置中的一個步 驟。 . 圖8描述根據本發明，在建構S C R裝置中的一個步驟。 較佳實施例詳述
O:\57\57214.ptc 第6頁 507354 _案號 88102425_年月日__ 五、發明說明（3) Μ〇S電晶體之靜電放電（E S D )電流的確透過寄生之雙載子 電晶體傳導；以η Μ 0 S電晶體（η Μ 0 S1)為例，在E S D事件開始 時，大電壓加在該η Μ 0 S Τ之没極；此導致在該没極接面發 生雪朋（a ν a 1 a n c h e )朋潰，電子流向〉及極電極而電洞流至 基板；該電洞電流流動造成電位降，其結果產生源極接面 之正向偏壓；此偏壓啟動了該η ρ η寄生雙載子電晶體。 參照圖1 ，一 Μ 0 S電晶體之部分截面一般示於1 0 ，而示意 電路附於1 2 ;電晶體1 0包括基板1 4、η+源極區1 6、η+汲極 區1 8以及閘極區2 0 ;此外，氧化物隔絕區2 2、2 4沿著該結 構周圍延伸；自對準矽化物區2 6、2 8分別覆蓋源極與汲極 區，而淡摻雜區3 0、3 2則位於閘極區2 0的兩側；氧化物蓋 3 4位在閘極區2 0上方，並以多晶矽閘極電極3 6填滿；該寄 生雙載子電晶體，係以源極1 6作為射極，基板（井）1 4作為 基極，而汲極區1 8作為集極來形成。 自對準矽化物層2 6、2 8係高度可傳導的；該寄生雙載子 電晶體之集極電流，係集中在鄰近閘極通道20之η_汲極接 面的很邊緣處；在汲極接面之電流密度分佈晝於圖1之插 圖3 8中；插圖3 8描繪出j對X ，並示出該電流分佈j ，隨 X (遠離該閘極通道區之距離）的增加而迅速減少。 此問題之一個已知的解決方法，係增加一道遮罩以避免 鄰近閘極電極之汲極接面石夕化；如此建構之先前技術的 Μ 0 S電晶體，一般地描繪於圖2 a中之4 0 ;等效電路繪於圖 2 b、以及圖2 a示意插圖中的4 2 ，其中R 1 > R 2 > R 3 ;該電流分 佈變得較為均勻，如插圖4 4中所示；此結構與圖1中所示 相似，可是，自對準矽化物區2 8 a並未完全延伸跨過汲極
O:\57\57214.ptc 第7頁 507354
507354 _案號 88102425_圭_月 日_修正 五、發明說明（5) ' 作之例；裝置60包括一nMOS電晶體62與一pM〇s電晶體64 ; 裝置6 0係形成於單晶矽6 6之基板上；在該基板上形成兩個 裝置區域：一p_井68與一 ΓΤ井7〇 ;形成n-井、p-井後，即接 著現今技術製程；該裝置區域係以s τ Ϊ或L 〇 c 〇 S絶緣技術隔 絕。 . 典型之STI (窄溝隔絕）製程，一開始先在基板66上沈積 一薄層二氧化矽，在10 nm至50㈣之範圍中，之後^尤貝積 一層厚度在50 nm至2 0 0 nm之間的氮化矽；在建構主動0裝貝 置之主動區域部份上被覆一光阻圖樣；將在光阻未覆蓋區 域中之氮化物與氧化物層姓離，之後，將下方之石夕姓3至 一 4 0 0 nm至7 0 0 nm之深度；將光阻除去並清潔該晶圓；接着 著’在姓刻過之矽表面上成長一薄層二氧化矽，以及在整 個基板上沈積一層二氧化矽；此氧化物層之厚度至少相等 於先前形成之石夕溝的深度；然後對該晶圓進行CMp製程， 以磨去多餘之二氧化石夕，該C Μ P停在氮化矽層；以熱磷酸 HJO3餘刻該氮化石夕，並以BHF溶液移去主動區域上的氧化 物，如此便完成S Τ I結構之形成。 LOCOS係一局部氧化製程’用於隔絕一裝置區域；如同 STI衣私’ 一厚度10 nm至40 nm之薄氧化物襯墊，沈積於 基板66之上；接著，沈積一厚度介於1〇〇 nms2〇〇㈣之氮‘ 化矽層，主動區域以光阻覆盍，而以熱磷酸蝕刻製程移去馨 在其他區域之氮化物，移去該光阻並對該晶圓進行高溫氧 化製程；通常該氧化溫度在9 5 0 °c至丨丨〇 〇之間；此製程 在暴露之矽表面區域、也就是氮化矽未覆蓋 域生長 二氧化石夕；在氮化石夕層下方不會有氧化物生d =
507354 案號 88102425 年月曰_ 五、發明說明（6) 化物層之後，移去該氮化物與襯墊氧化物；主動區域被一 厚層氧化物隔開；起始電壓以離丰佈植調整。 在完成閘極氧化物之成長後，便沈積多晶矽並將其選擇 性地姓刻’以形成閘極電極9 4、9 6 ;形成η Μ 0 S電晶體6 2之 源極區7 2、閘極通道7 4以及汲極區7 6 ;源極區7 2與汲極區 76 以nLDD，藉由佈植雜質數5. 〇*i 〇i2cm-2 至！ · 〇*} 〇14cm-2、能 量20kev至50kev之砷離子來形成；氧化絕緣區78、8〇與82 係STI區。 再I成pMOS笔sa體7 0之 >及極區8 4、問極通道8 6與源極 區8 8 ;在此例中，源極區8 8與汲極區8 4係以p L D D，藉由佈 植雜夤數5· 0*1012cm 2 至 1. 〇*i〇14cm_2、能量20kev 至 50kev 之 B F 2離子來形成，閘極電極側牆則是由c V D之二氧化石夕與電 漿反向蝕刻製程，形成在閘極電極9 4、9 6周邊之氧化物蓋 9 0、9 2來形成。 為了 γτ之離子佈植，結構6 〇以光阻覆蓋，如圖4中之 9 8、1 0 0 ;此遮罩覆蓋了整個p Μ 0 S區域以及部份η Μ 0 S沒極 區與鄰近閘極通道區域。 佈植雜質數 1.0*1015cnr2 至 5.0*1015cnr2、能量 20kev 至 50kev之砷離子來形成n+源極區104與n+汲極區106 ;去掉光 阻，得到如圖5所繪之結構。 仍然參照圖5，鋪上用於p_離子佈植，如圖所示之光阻 1 08、1 09 ;此遮罩覆蓋了整個nMOS區域以及部份PM0S汲極 區與鄰近閘極區域；P+離子佈植包含雜質數1 . 〇 * 1 〇i5cm-2至 5.0*1015cnr2、能量20kev至50kev之BF2離子；結果形成p+汲 極區110與P+源極區112(圖6);再一次地去掉光阻。
111
II 11»! 1 O:\57\57214.ptc 第10頁 507354 _ 案號88102425_ 年月曰_ 修正 五、發明說明（7) ---- 自對準矽化物層114、116、118、120、122與124係以 化製程形成，其中，清潔該晶圓，-並將在源極、汲極與間 極上表面之上的氧化物，以BHF蝕刻製程移去；在石夕晶圓尹 上沈積一層Ti或Co，或其他適合之耐高溫金屬，厚度為5 ηπι至20 nm ;然後將該晶圓在氮氣之大氣環境中加執^〇”'至 3。〇秒，加熱溫度Ti是6 0 0 °C至6 5 0 t ，C〇則是5 0 0它至6〇〇 C ’以在碎與而于南溫金屬接觸之區域上，形成富含金屬之 自對準矽化物；以選擇性化學溶劑，如（PiranhH^^i HC 1/Η2Ο?混合物，移去未反應之金屬，附加之熱處理，在 氮氣大氣環境中，以7 0 0 °C至9 0 0 °C加熱20秒至^分鐘，將 ό玄s含金屬之自對準石夕化物轉化成為低電阻之二自石 化物。 一 、π / 以C V D之氧化物層1 2 6覆蓋邊結構，並钱刻之以便金屬化 (metallization);金屬化形成源極電極Kg，其為yss端 點’閘極電極130、共汲極電極132、閘極電極13'4與源極 電極1 3 6 ’其為V d d端點，如圖6中所示，該自.對準石夕化物 層係橫向地與閘極通道區分開，因而提供了堅強的E s D保 護，更詳細地說，分別覆蓋；:及極區7 6、8 4之自對準石夕化物 層118、120，與閘極通道74、86分開20 11111至150 nm，而 分別覆蓋源極區7 2、8 8之自對準矽化物層丨丨4、丨2 4，與閘 極通道74、86分開20 nm至150 nm。 圖7繪出具備ESD保護之p/n接面140之佈局；接面14〇包 括p井結構1 4 1與η井結構1 4 2 ;電路示意圖附加於該截面 上；該結構係在基板6 6上形成；ρ-井6 8與η-井7 〇形成至基 板6 6中’氧化絶緣區域1 4 3、1 4 4、1 4 6、1 4 8與1 5 0係根據
O:\57\57214.ptc 第11頁 507354 案號 88102425 年 月 曰 修正 五、發明說明（8) 本發明，在建構ρ / η接面之前形成；p層1 5 2與n 1 5 4係與源 極/及極離子佈植同時形成；微摻雜之η層1 5 6與ρ層1 6 6係 在L D D離子佈植時同時形成。 η+層1 62、ρ+層1 64以及微摻雜之Ρ—層1 66則形成於11-井結 構1 4 2之上；自對準矽化物層1 5 8、1 6 0、1 6 8與1 7 0則如前 所述地形成。 圖8繪出具有ESD保護之SCR 180之佈局，及附加之電路 示意圖；ρ_井68與rr井70形成於基板66之上；STI區域 186、188、190、192與194如前所述地形成；Ρ-層196、 2 0 8與rr層1 98、2 0 6與ρ-及it源極/汲極離子佈植同步形 成；rr層2 0 0與p_層210貝q個另在nM〇S與pMOS之LDD離子佈植 期間形成；自對準矽化物層2 0 2、2 0 4、2 1 2與2 1 4在Μ 0 S電 晶體自對準矽化物製程期間形成。η-井結構丨8 4、η-層 2 0 6、ρ_層2 0 8與ρ_層210被形成。自對準矽化物層2 0 2、 2 0 4、2 1 2與2 1 4在C Μ 0 S自對準石夕化物製程期間同步形成。 因此，E S D保護之自對準矽化物裝置其製造之方法已 闡述之；雖然敘述了本發明之最佳實施例與其數個變化， 但是熟知此類技術者應能瞭解，可作更多變化與修正，而 未偏離如所附之申請專利範圍所界定的，本發明的範圍。
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Claims (1)

  1. 507354 案號 88102425 Λ_Ά 修正 六、申請專利範圍 1 . 一種形成靜電放電保護之自對準矽化物裝置的方法， 其包含： 閘極通道與一汲極 在一單晶基板上，形成一源極區 區，其中該源極區與該汲極區係以使用低摻雜濃度製程之 第一種離子佈植來形成； 在該 遮罩 化物層 佈植 >及極區 與閘極 在汲 對準矽 2.如 度製程 中之離 3 ·如 度製程 間、而 4 ·如 度製程 間、而 5 .如 化物層 閘極通道上沈積一閘極氧化物層； 至少一部份（及極區與至少一部份閘極通道與閘極氧 第二種離子，以便在源極區與閘極通道之間，以及 與閘極通道之間形成一個區域，因而分隔了汲極區 通道；以及 極區與源極區之上形成自對準石夕化物層，其中該自 化物層係與該閘極通道分開。 申請專利範圍第1項之方法，其中該使用低摻雜濃 之形成，包含一般以1 · 0*1 018cnr3至5. 0*1 019cnr3範圍 子作佈植。 申請專利範圍第2項之方法，其中該使用低摻雜濃 包含佈植雜質數在大約5· 0*1 012cnr2至1 . 0*1 014cnr2之 能量在20kev至50kev之As離子。 申請專利範圍第2項之方法，其中該使用低摻雜濃 包含佈植雜質數在大約5. 0*1 012cnr2至1 . 0*1 014cnr2之 能量在20kev至50kev之BF2離子。 申請專利範圍第1項之方法，.其中該形成自對準矽 包含，將覆蓋在汲極區上之該自對準矽化物層與該
    O:\57\57214.ptc 第14頁 507354 案號88102425 年月日 修正 六、申請專利範圍 閘極通道，橫向地分開至少2 0 n m的距離。 6 .如申請專利範圍第1項之方法_，其中該形成自對準矽 化物層包含，將覆蓋在源極區上之該自對準矽化物層與該 閘極通道，橫向地分開至少2 0 n m的距離。 7. —種ESD保護之自對準矽化物裝置，其包含： 在^一早晶基板上之主動區域， 在該主動區域上形成之閘極通道； I 在該閘極通道兩側形成之一 L D D源極區與一 L D D汲極區； 至少部份地覆蓋該源極區與該汲極區之自對準矽化物 層，其中該自對準矽化物層係與該閘極通道分開； 一覆蓋在該結構所餘之處的氧化物層； 連接至該源極區、該閘極通道與該汲極區之電極。 8. 如申請專利範圍第7項之ESD保護的裝置，其中該覆蓋 在該汲極區之自對準矽化物層與該閘極通道，至少相隔2 0 置道 裝通 的極 護閘 保該 SD與 E層 之7/ 項4 7化 第矽 圍準 範對 利自 專之 請區 極 如源 Ο · 9言 m 在 η ^ ，其中該覆蓋 ，至少相隔2 0 n m ° 1 0 .如申請專利範圍第7項之ESD保護的裝置，其中該源 極區與該汲極區，係雜質數在大約5.0*1012cnr2至1.0*1014 cm-2之間、而能量在20kev至50kev之As離子形成的nLDD。 1 1 .如申請專利範圍第7項之ESD保護的裝置，其中該源 極區與該汲極區，係雜質數在大約5.0*1012cm_2至1.0*1014 cm-2之間、而能量在20kev至50kev之BF2離子形成的pLDD。
    O:\57\57214.ptc 第15頁
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