US20010012666A1 - Electrostatic discharge protection for salicided devices - Google Patents
Electrostatic discharge protection for salicided devices Download PDFInfo
- Publication number
- US20010012666A1 US20010012666A1 US09/772,463 US77246301A US2001012666A1 US 20010012666 A1 US20010012666 A1 US 20010012666A1 US 77246301 A US77246301 A US 77246301A US 2001012666 A1 US2001012666 A1 US 2001012666A1
- Authority
- US
- United States
- Prior art keywords
- gate channel
- drain region
- source region
- gate
- kev
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 230000000873 masking effect Effects 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000013078 crystal Substances 0.000 claims abstract description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- -1 BF2 ions Chemical class 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000010276 construction Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 241000252506 Characiformes Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000000472 traumatic effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Definitions
- This invention relates to integrated circuits, and specifically to a structure and method for providing electrostatic discharge protection for integrated circuits containing a salicide component.
- Silicon based integrated circuits are susceptible to electrostatic discharge (ESD) damage, particularly in the situation where a user of a device containing an integrated circuit develops a static charge on their body and subsequently comes in contact with the device containing the integrated circuit.
- ESD electrostatic discharge
- the electrostatic charge induced in a human body may produce a voltage on the order of 5,000 volts.
- an electrostatic discharge from a human body can be a traumatic experience for the integrated circuit.
- One way to provide an integrated circuit with ESD protection is to build an integrated circuit on a substrate that is less susceptible to damage from ESD.
- the integrated circuit may be fabricated on bulk silicon substrates, silicon on insulator (SOI) substrates, or separation by implantation of oxygen (SIMOX) substrates.
- Electrostatic Discharge (ESD) Protection is generally provided by the addition of a masking step during manufacture of an integrated circuit device to prevent silicidation of a drain region adjacent to the gate electrode. This technique, however, does not provide complete ESD protection, and requires additional steps, time, and expense in the manufacturing process.
- a method of forming an electrostatic discharge protected salicided device includes forming, on a single crystal substrate, a source region, a gate channel and a drain region, wherein the source region and drain region are formed by implanting ions of a first type using a low doping density process; depositing a gate oxide layer over the gate channel; masking at least a portion of the drain region and at least a portion of the gate channel and gate oxide layer; implanting ions of a second type to form an area between the source region and gate channel and between the drain region and gate channel thereby to separate the drain region from the gate channel; and forming salicide layers over the drain region and source region, wherein the salicide layers are separated from the gate channel.
- Another object of the invention is to provide a method of making a robust ESD protected device using a minimal number of steps.
- FIG. 1 is a cross-section of a portion of a parasitic bipolar transistor in a MOS transistor.
- FIG. 2 is a cross-section of a portion of a bipolar transistor with prior art ESD protection.
- FIG. 3 is a cross-section of a portion of a LDD structure according to the invention.
- FIG. 4 depicts an intermediate step in the construction of an ESD protected device according to the invention.
- FIG. 5 depicts a further step in the construction of an ESD protected device according to the invention.
- FIG. 6 is a cross section of a CMOS transistor pair constructed according to the invention.
- FIG. 7 depicts a step in the construction of a p/n junction device according to the invention.
- FIG. 8 depicts a step in the construction of a SCR device according to the invention.
- ESD electrostatic discharge
- nMOST nMOS transistor
- a large voltage is applied to the drain of the nMOST. This causes an avalanche breakdown to occur at the drain junction. Electrons flow to the drain electrode while holes flow to the substrate. The hole current flow causes a voltage drop, which results in a forward bias of the source junction. This bias voltage turns on the npn parasitic bipolar transistor.
- Transistor 10 includes a substrate 14 , a n + source region 16 , a n + drain region 18 and a gate region 20 . Additionally, oxide isolation regions 22 , 24 extend about the periphery of the structure. Silicide regions 26 , 28 overlay the source and drain regions, respectively, while lightly doped regions 30 , 32 are located on either side of gate region 20 . An oxide cup 34 is located above gate region 20 , and is filled by a polysilicon gate electrode 36 .
- the parasitic bipolar transistor is formed by source 16 as an emitter, substrate (well) 14 as a base, and drain region 18 as collector.
- Silicide layers 26 , 28 are very highly conductive.
- the collector current of the parasitic bipolar transistor is concentrated at the very edge of the n + drain junction adjacent gate channel 20 .
- the current density distribution at the drain junction is sketched in a graph inset, 38 , of FIG. 1.
- Inset 38 depicts j vs. x, and shows that the current density distribution, j, decreases rapidly as x, the distance away from the gate channel region, increases.
- a known solution to this problem is to add a mask to prevent silicidation of the drain junction adjacent to the gate electrode.
- a prior art MOS transistor so constructed is depicted generally at 40 in FIG. 2 a.
- the equivalent circuit is shown at 42 in FIG. 2 b, and in the schematic inset of FIG. 2 a, where R 1 >R 2 >R 3 .
- the current distribution becomes more uniform, as is shown in the graph inset at 44 .
- This structure is similar to that shown in FIG. 1, however, a silicide region 28 a does not extend fully across drain region 18 .
- the process to form such a device requires one additional masking step during device construction, which increases production cost and complicates the construction process.
- the present invention makes use of the fact that a silicide-to-silicon contact is ohmic only if the silicon is heavily doped.
- the contact resistance is strongly dependent on the doping density when the silicon doping density is relatively low.
- the contact resistance is large.
- a lower doping density results in a larger contact resistance.
- This characteristic is used in the present invention to fabricate devices having selected levels of contact resistance to create a robust ESD device.
- a process step described as implanting ions using a low doping density process means implanting ions to a concentration generally in the range of 1.0 ⁇ 10 18 cm ⁇ 3 to 5.0 ⁇ 10 19 cm ⁇ 3 .
- Layers 30 , 32 are lightly doped regions. Layer 32 serves to space drain region 18 from gate channel 20 . A silicide layer 28 b extends over drain region 18 and layer 32 .
- source region 16 and drain region 18 are formed by a LDD process, by implanting arsenic ions at a dose of 5.0 ⁇ 10 12 cm ⁇ 2 to 5.0 ⁇ 10 14 cm ⁇ 2 at an energy of 20 kev to 50 kev.
- R 1 is the sum of LDD resistance and the LDD to silicide contact resistance.
- R 3 is equal to the n + layer resistance and R 2 is in between. Therefore, R 1 >R 2 >R 3 .
- R 1 >R 2 >R 3 the current distribution in the drain n+junction is more uniform, similar to that of the prior art process.
- the same technique can be applied to the formation for SCR ESD protection, as shown in FIG. 8.
- CMOS transistor pair is provided as an example of device fabrication, generally at 60 .
- Device 60 will include a nMOS transistor 62 and a pMOS transistor 64 .
- Device 60 is formed on a substrate of single crystal silicon 66 .
- Two device areas are formed on the substrate: a p ⁇ well 68 and a n ⁇ well 70 .
- State of the art processes are followed to form n ⁇ well, p ⁇ well.
- the device areas are isolated by STI or LOCOS isolation techniques.
- a typical STI (Shallow Trench Isolation) process begins with the deposition of a thin layer of silicon oxide, in the range of 10 nm to 50 nm, onto substrate 66 , after which, a layer of silicon nitride is deposited to a thickness of between 50 nm to 200 nm.
- a pattern of photoresist is applied over the portion of the active area where the active devices are to be constructed.
- the nitride and the oxide layers are etched in the areas not covered by photoresist, after which, the underlying silicon is etched to a depth of 400 nm to 700 nm.
- the photoresist is stripped away and the wafer is cleaned.
- a thin layer of silicon oxide is grown onto the surface of the etched silicon, and a layer of silicon oxide is deposited over the entire substrate.
- the thickness of this oxide layer is at least equal to the depth of the previously formed silicon trenches.
- the wafer is then subjected to a CMP process to polish the excessive silicon oxide away.
- the silicon nitride is etched with hot phosphorus acid H 2 PO 3 , and the oxide pads over the active areas are removed by BHF solution. This completes the formation of the STI structure.
- LOCOS is a local oxidation process used to isolate a device area.
- a thin oxide pad having a thickness of 10 nm to 40 nm, is deposited on substrate 66 .
- a silicon nitride layer is deposited to a thickness of between 100 nm to 200 nm.
- the active areas is masked with photoresist and the nitride in the field areas is removed by a hot phosphorus acid etching process.
- the photoresist is stripped and the wafer is subjected to a high temperature oxidation process.
- the oxidation temperature is typically between 950° C. to 1100° C.
- This process grows silicon dioxide on the exposed silicon surface area, i.e., those areas not covered with silicon nitride. No oxide will grow under the silicon nitride layers. After the growth of the oxide layer, the nitride and the pad oxide are removed. The active device areas are separated by a thick layer of oxide. The threshold voltage is adjusted by ion implantation.
- gate oxide is deposited, and is selectively etched to form gate electrodes 94 , 96 .
- a source region 72 , gate channel 74 and drain region 76 are formed for nMOS transistor 62 .
- Source region 72 and drain region 76 are formed by nLDD, by implanting arsenic ions at a dose of 5.0 ⁇ 10 12 cm ⁇ 2 to 1.0 ⁇ 10 14 cm ⁇ 2 at an energy of 20 kev to 50 kev.
- Oxide isolation regions 78 , 80 and 82 are STI regions.
- a drain region 84 , gate channel 86 and source region 88 are formed for pMOS transistor 70 .
- Source region 88 and drain region 84 are, in this instance, formed by pLDD, by implanting BF 2 ions at a dose of 5.0 ⁇ 10 12 cm ⁇ 2 to 1.0 ⁇ 10 14 cm ⁇ 2 at an energy of 20 kev to 50 kev.
- Gate electrode side wall oxide is formed by CVD of silicon oxide and a plasma etch-back process to form oxide cups 90 , 92 , about gate electrodes 94 , 96 .
- Structure 60 is covered with photoresist, as shown in FIG. 4 at 98 , 100 , for n + ion implantation. This mask covers all of the pMOS areas and portion of nMOS drain region and adjacent gate channel area.
- an n + source region 104 and an n + drain region 106 are formed by implanting arsenic ions at a dose of 1.0 ⁇ 10 15 to 5.0 ⁇ 10 15 cm ⁇ 2 at an energy of 20 kev to 50 kev.
- the photoresist is stripped, resulting in the structure depicted in FIG. 5.
- photoresist, 108 , 109 is applied as shown for p + ion implantation.
- This mask covers all nMOS areas and portion of pMOS drain area and adjacent gate area.
- P + ion implantation includes BF 2 ions at a dose of 1.0 ⁇ 10 15 cm ⁇ 2 to 5.0 ⁇ 10 15 cm ⁇ 2 at an energy of 20 kev to 50 kev. This results in the formation of a p + drain region 110 and a p + source region 112 (FIG. 6). Again, the photoresist is stripped.
- Silicide layers 114 , 116 , 118 , 120 , 122 , and 124 are formed by a salicide process, wherein the wafer is cleaned, and the oxide on the source, drain and gate top surfaces is removed by a BHF etching process.
- a layer of Ti or Co, or other suitable refractory metal is deposited onto the silicon wafer to a thickness of 5 nm to 20 nm.
- the wafer is then heated in a nitrogen ambient atmosphere, at 600° C. to 650° C. for Ti, and 500° C. to 600° C. for Co, for 10 to 30 seconds to form metal rich silicide onto the areas where silicon contacts the refractory metal.
- the un-reacted metal is removed by selective chemical dissolution, such as Piranha, or in HCI/H 2 O 2 mixture. Additional heat treatment, at 700° C. to 900° C. in a nitrogen ambient atmosphere for 20 seconds to 1 minute converts the metal-rich silicide to low-resistance disilicide.
- the structure is covered with an oxide layer 126 by CVD, and etched for metallization.
- Metallization forms source electrode 128 , which is a Vss terminal, gate electrode 130 , a common drain electrode 132 , a gate electrode 134 and a source electrode 136 , which is a Vdd terminal.
- the silicide layers are laterally separated from the gate channel regions, thereby providing robust ESD protection.
- silicide layers 118 , 120 overlying drain regions 76 , 84 , respectively, are separated from gate channel 74 , 86 , by 20 nm to 150 nm, while silicide layers 114 , 124 overlying source regions 72 , 88 , respectively, are laterally separated from the gate channels by 20 nm to 150 nm.
- FIG. 7 depicts the layout of p/n junction 140 having ESD protection.
- Junction 140 includes p-well structure 141 and n-well structure 142 .
- a circuit schematic is overlaid on the cross section.
- the structures are formed on a substrate 66 .
- P ⁇ well 68 and n ⁇ well 70 are formed to the substrate 66 .
- Oxide isolation regions 143 , 144 , 146 , 148 and 150 are formed before the construction of the pin junction according to the invention.
- a p + layer 152 and a n + layer 154 are formed simultaneously with the source/drain ion implantation.
- a lighted doped n ⁇ layer 156 and a p ⁇ layer 166 are formed at the same time of LDD ion implantation.
- N + layer 162 , p + layer 164 and lighted doped p ⁇ layer 166 are formed on n ⁇ well structure 142 .
- Silicide layers 158 , 160 , 168 and 170 are formed as previously described.
- FIG. 8 depicts the layout of a SCR 180 for ESD protection, with an overlaid circuit schematic.
- P ⁇ well 68 and n ⁇ well 70 are formed on substrate 66 .
- STI regions 186 , 188 , 190 , 192 and 194 are formed as previously described.
- P + layers 196 , 208 and n + layers 198 , 206 are formed simultaneously with the p + and n + source drain ion implantation.
- An n layer 200 and p ⁇ layer 210 are formed during the LDD ion implantation for nMOS and pMOS, respectively.
- Silicide layers 202 , 204 , 212 , and 214 are formed during the salicide process for the MOS transistors.
- n ⁇ well structure 184 , n + layer 206 , p + layer 208 and p ⁇ layer 210 are formed.
- Silicide layers 202 , 204 , 212 and 214 are formed simultaneously during the CMOS salicide process.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A method of forming an electrostatic discharge protected salicided device includes forming, on a single crystal substrate, a source region, a gate channel and a drain region, wherein the source region and drain region are formed by implanting ions of a first type using a low doping density process; depositing a gate oxide layer over the gate channel; masking at least a portion of the drain region and at least a portion of the gate channel and gate oxide layer; implanting ions of a second type to form an area between the source region and gate channel and between the drain region and gate channel thereby to separate the drain region from the gate channel; and forming salicide layers over the drain region and source region, wherein the salicide layers are separated from the gate channel.
Description
- This invention relates to integrated circuits, and specifically to a structure and method for providing electrostatic discharge protection for integrated circuits containing a salicide component.
- Silicon based integrated circuits are susceptible to electrostatic discharge (ESD) damage, particularly in the situation where a user of a device containing an integrated circuit develops a static charge on their body and subsequently comes in contact with the device containing the integrated circuit. The electrostatic charge induced in a human body may produce a voltage on the order of 5,000 volts. As most integrated circuits operate at no higher than five volts, an electrostatic discharge from a human body can be a traumatic experience for the integrated circuit. One way to provide an integrated circuit with ESD protection is to build an integrated circuit on a substrate that is less susceptible to damage from ESD. The integrated circuit may be fabricated on bulk silicon substrates, silicon on insulator (SOI) substrates, or separation by implantation of oxygen (SIMOX) substrates.
- Electrostatic Discharge (ESD) Protection is generally provided by the addition of a masking step during manufacture of an integrated circuit device to prevent silicidation of a drain region adjacent to the gate electrode. This technique, however, does not provide complete ESD protection, and requires additional steps, time, and expense in the manufacturing process.
- A method of forming an electrostatic discharge protected salicided device includes forming, on a single crystal substrate, a source region, a gate channel and a drain region, wherein the source region and drain region are formed by implanting ions of a first type using a low doping density process; depositing a gate oxide layer over the gate channel; masking at least a portion of the drain region and at least a portion of the gate channel and gate oxide layer; implanting ions of a second type to form an area between the source region and gate channel and between the drain region and gate channel thereby to separate the drain region from the gate channel; and forming salicide layers over the drain region and source region, wherein the salicide layers are separated from the gate channel..
- It is an object of the invention to provide a CMOS structure with robust ESD protection without using an additional mask.
- Another object of the invention is to provide a method of making a robust ESD protected device using a minimal number of steps.
- FIG. 1 is a cross-section of a portion of a parasitic bipolar transistor in a MOS transistor.
- FIG. 2 is a cross-section of a portion of a bipolar transistor with prior art ESD protection.
- FIG. 3 is a cross-section of a portion of a LDD structure according to the invention.
- FIG. 4 depicts an intermediate step in the construction of an ESD protected device according to the invention.
- FIG. 5 depicts a further step in the construction of an ESD protected device according to the invention.
- FIG. 6 is a cross section of a CMOS transistor pair constructed according to the invention.
- FIG. 7 depicts a step in the construction of a p/n junction device according to the invention.
- FIG. 8 depicts a step in the construction of a SCR device according to the invention.
- The electrostatic discharge (ESD) current of a MOS transistor is actually conducted through a parasitic bipolar transistor. Using an nMOS transistor (nMOST) as an example, at the beginning of an ESD event, a large voltage is applied to the drain of the nMOST. This causes an avalanche breakdown to occur at the drain junction. Electrons flow to the drain electrode while holes flow to the substrate. The hole current flow causes a voltage drop, which results in a forward bias of the source junction. This bias voltage turns on the npn parasitic bipolar transistor.
- Referring to FIG. 1, a cross section of portion of a MOS transistor is shown generally at10, and an overlay of the circuit schematic is shown at 12.
Transistor 10 includes asubstrate 14, a n+ source region 16, a n+drain region 18 and agate region 20. Additionally,oxide isolation regions regions gate region 20. Anoxide cup 34 is located abovegate region 20, and is filled by apolysilicon gate electrode 36. The parasitic bipolar transistor is formed by source 16 as an emitter, substrate (well) 14 as a base, and drainregion 18 as collector. - Silicide layers26, 28 are very highly conductive. The collector current of the parasitic bipolar transistor is concentrated at the very edge of the n+ drain junction
adjacent gate channel 20. The current density distribution at the drain junction is sketched in a graph inset, 38, of FIG. 1. Inset 38 depicts j vs. x, and shows that the current density distribution, j, decreases rapidly as x, the distance away from the gate channel region, increases. - A known solution to this problem is to add a mask to prevent silicidation of the drain junction adjacent to the gate electrode. A prior art MOS transistor so constructed is depicted generally at40 in FIG. 2a. The equivalent circuit is shown at 42 in FIG. 2b, and in the schematic inset of FIG. 2a, where R1>R2>R3. The current distribution becomes more uniform, as is shown in the graph inset at 44. This structure is similar to that shown in FIG. 1, however, a silicide region 28 a does not extend fully across
drain region 18. The process to form such a device, however, requires one additional masking step during device construction, which increases production cost and complicates the construction process. - The present invention makes use of the fact that a silicide-to-silicon contact is ohmic only if the silicon is heavily doped. The contact resistance is strongly dependent on the doping density when the silicon doping density is relatively low. For low-to-medium doped silicon, wherein ions are implanted at a concentration generally in the range of 1.0·1018 cm−3 to 5.0·1019 cm−3, the contact resistance is large. A lower doping density results in a larger contact resistance. This characteristic is used in the present invention to fabricate devices having selected levels of contact resistance to create a robust ESD device. Used herein, a process step described as implanting ions using a low doping density process means implanting ions to a concentration generally in the range of 1.0·1018 cm−3 to 5.0·1019 cm−3.
- Referring now to FIG. 3a, a portion of an nMOS transistor is depicted at 50, while the equivalent circuit is depicted in FIG. 3b at 52.
Layers Layer 32 serves tospace drain region 18 fromgate channel 20. A silicide layer 28 b extends overdrain region 18 andlayer 32. In this embodiment of the invention, source region 16 and drainregion 18 are formed by a LDD process, by implanting arsenic ions at a dose of 5.0·1012 cm−2 to 5.0·1014 cm−2 at an energy of 20 kev to 50 kev. R1 is the sum of LDD resistance and the LDD to silicide contact resistance. R3 is equal to the n+ layer resistance and R2 is in between. Therefore, R1>R2>R3. As a result the current distribution in the drain n+junction is more uniform, similar to that of the prior art process. The same technique can be applied to the formation for SCR ESD protection, as shown in FIG. 8. - Referring now to FIG. 4, a CMOS transistor pair is provided as an example of device fabrication, generally at60.
Device 60 will include anMOS transistor 62 and apMOS transistor 64.Device 60 is formed on a substrate ofsingle crystal silicon 66. Two device areas are formed on the substrate: a p− well 68 and a n− well 70. State of the art processes are followed to form n− well, p− well. The device areas are isolated by STI or LOCOS isolation techniques. - A typical STI (Shallow Trench Isolation) process begins with the deposition of a thin layer of silicon oxide, in the range of 10 nm to 50 nm, onto
substrate 66, after which, a layer of silicon nitride is deposited to a thickness of between 50 nm to 200 nm. A pattern of photoresist is applied over the portion of the active area where the active devices are to be constructed. The nitride and the oxide layers are etched in the areas not covered by photoresist, after which, the underlying silicon is etched to a depth of 400 nm to 700 nm. The photoresist is stripped away and the wafer is cleaned. Next, a thin layer of silicon oxide is grown onto the surface of the etched silicon, and a layer of silicon oxide is deposited over the entire substrate. The thickness of this oxide layer is at least equal to the depth of the previously formed silicon trenches. The wafer is then subjected to a CMP process to polish the excessive silicon oxide away. The CMP stops at the level of the silicon nitride. The silicon nitride is etched with hot phosphorus acid H2PO3, and the oxide pads over the active areas are removed by BHF solution. This completes the formation of the STI structure. - LOCOS is a local oxidation process used to isolate a device area. As in the STI process, a thin oxide pad, having a thickness of 10 nm to 40 nm, is deposited on
substrate 66. Next, a silicon nitride layer is deposited to a thickness of between 100 nm to 200 nm. The active areas is masked with photoresist and the nitride in the field areas is removed by a hot phosphorus acid etching process. The photoresist is stripped and the wafer is subjected to a high temperature oxidation process. The oxidation temperature is typically between 950° C. to 1100° C. This process grows silicon dioxide on the exposed silicon surface area, i.e., those areas not covered with silicon nitride. No oxide will grow under the silicon nitride layers. After the growth of the oxide layer, the nitride and the pad oxide are removed. The active device areas are separated by a thick layer of oxide. The threshold voltage is adjusted by ion implantation. - After the growth of the gate oxide is completed, polysilicon is deposited, and is selectively etched to form
gate electrodes source region 72,gate channel 74 and drainregion 76 are formed fornMOS transistor 62.Source region 72 and drainregion 76 are formed by nLDD, by implanting arsenic ions at a dose of 5.0·1012 cm−2 to 1.0·1014 cm−2 at an energy of 20 kev to 50 kev.Oxide isolation regions - A
drain region 84, gate channel 86 andsource region 88 are formed forpMOS transistor 70.Source region 88 and drainregion 84 are, in this instance, formed by pLDD, by implanting BF2 ions at a dose of 5.0·1012 cm−2 to 1.0·1014 cm−2 at an energy of 20 kev to 50 kev. Gate electrode side wall oxide is formed by CVD of silicon oxide and a plasma etch-back process to form oxide cups 90, 92, aboutgate electrodes -
Structure 60 is covered with photoresist, as shown in FIG. 4 at 98, 100, for n+ ion implantation. This mask covers all of the pMOS areas and portion of nMOS drain region and adjacent gate channel area. - an n+ source region 104 and an n+ drain region 106 are formed by implanting arsenic ions at a dose of 1.0·1015 to 5.0·1015 cm−2 at an energy of 20 kev to 50 kev. The photoresist is stripped, resulting in the structure depicted in FIG. 5.
- Still referring to FIG. 5, photoresist,108, 109, is applied as shown for p+ ion implantation. This mask covers all nMOS areas and portion of pMOS drain area and adjacent gate area. P+ ion implantation includes BF2ions at a dose of 1.0·1015 cm−2 to 5.0·1015 cm−2 at an energy of 20 kev to 50 kev. This results in the formation of a p+ drain region 110 and a p+ source region 112 (FIG. 6). Again, the photoresist is stripped.
- Silicide layers114, 116, 118, 120, 122, and 124 are formed by a salicide process, wherein the wafer is cleaned, and the oxide on the source, drain and gate top surfaces is removed by a BHF etching process. A layer of Ti or Co, or other suitable refractory metal, is deposited onto the silicon wafer to a thickness of 5 nm to 20 nm. The wafer is then heated in a nitrogen ambient atmosphere, at 600° C. to 650° C. for Ti, and 500° C. to 600° C. for Co, for 10 to 30 seconds to form metal rich silicide onto the areas where silicon contacts the refractory metal. The un-reacted metal is removed by selective chemical dissolution, such as Piranha, or in HCI/H2O2 mixture. Additional heat treatment, at 700° C. to 900° C. in a nitrogen ambient atmosphere for 20 seconds to 1 minute converts the metal-rich silicide to low-resistance disilicide.
- The structure is covered with an oxide layer126 by CVD, and etched for metallization. Metallization forms source electrode 128, which is a Vss terminal, gate electrode 130, a common drain electrode 132, a gate electrode 134 and a
source electrode 136, which is a Vdd terminal. As is shown in FIG. 6, the silicide layers are laterally separated from the gate channel regions, thereby providing robust ESD protection. Specifically, silicide layers 118, 120 overlyingdrain regions gate channel 74, 86, by 20 nm to 150 nm, while silicide layers 114, 124overlying source regions - FIG. 7 depicts the layout of p/
n junction 140 having ESD protection.Junction 140 includes p-well structure 141 and n-well structure 142. A circuit schematic is overlaid on the cross section. The structures are formed on asubstrate 66. P− well 68 and n− well 70 are formed to thesubstrate 66.Oxide isolation regions layer 154 are formed simultaneously with the source/drain ion implantation. A lighted doped n− layer 156 and a p− layer 166 are formed at the same time of LDD ion implantation. - N+ layer 162, p+ layer 164 and lighted doped p− layer 166 are formed on n− well structure 142. Silicide layers 158, 160, 168 and 170 are formed as previously described.
- FIG. 8 depicts the layout of a
SCR 180 for ESD protection, with an overlaid circuit schematic. P− well 68 and n− well 70 are formed onsubstrate 66.STI regions - Thus, an ESD protected salicided device and a method of making the same have been disclosed. Although a preferred embodiment of the invention, and several variations thereof, has been disclosed, it will be appreciated by those of skill in the art that further variations and modifications may be made without departing from the scope of the invention as defined in the appended claims.
Claims (11)
1. A method of forming an electrostatic discharge protected salicided device comprising:
forming, on a single crystal substrate, a source region, a gate channel and a drain region, wherein the source region and drain region are formed by implanting ions of a first type using a low doping density process;
depositing a gate oxide layer over the gate channel;
masking at least a portion of the drain region and at least a portion of the gate channel and gate oxide layer;
implanting ions of a second type to form an area between the source region and gate channel and between the drain region and gate channel thereby to separate the drain region from the gate channel; and
forming salicide layers over the drain region and source region, wherein the salicide layers are separated from the gate channel.
2. The method of wherein said forming using a low doping density process includes implanting ions at a concentration generally in the range of 1.0·1018 cm−3 to 5.0·1019 cm−3.
claim 1
3. The method of wherein said using a low doping density process includes implanting As ions at a dose of between about 5.0·1012 cm−2 to 1.0·1014 cm−2 at an energy of 20 kev to 50 kev.
claim 2
4. The method of wherein said using a low doping density process includes implanting BF2 ions at a dose of between about 5.0·1012 cm−2 to 1.0·1014 cm−2 at an energy of 20 kev to 50 kev.
claim 2
5. The method of wherein said forming salicide layers includes separating, laterally, the salicide layer overlying the drain region from the gate channel by a distance of at least 20 nm.
claim 1
6. The method of wherein said forming salicide layers includes separating, laterally, the salicide layer overlying the source region from the gate channel by a distance of at least 20 nm.
claim 1
7. An ESD protected salicided device comprising:
an active area on a single crystal silicon substrate;
a gate channel formed on the active area;
a LDD source region and a LDD drain region formed on either side of said gate channel;
salicide layers at least partially overlaying said source region and said drain region, wherein said salicide layers are laterally spaced from said gate channel;
an oxide layer overlaying the remainder of the structure; and
electrodes connected to said source region, said gate channel and said drain region.
8. The ESD protected device of wherein said silicide layer overlaying said drain region is spaced from said gate channel by at least 20 nm.
claim 7
9. The ESD protected device of wherein said silicide layers overlaying said source region is spaced from said gate channel by at least 20 nm.
claim 7
10. The ESD protected device of wherein said source region and said drain region are nLDD with As ions at a dose of between about 5.0·1012 cm−2 to 1.0·1014 cm−2 at an energy of 20 kev to 50 kev.
claim 7
11. The ESD protected device of wherein said source region and said drain region are pLDD with BF2 ions at a dose of between about 5.0·1012 cm−2 to 1.0·1014 cm−2 at an energy of 20 kev to 50 kev.
claim 7
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/772,463 US6433395B2 (en) | 1998-07-24 | 2001-01-29 | Electrostatic discharge protection for salicided devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/122,494 US6211001B1 (en) | 1998-07-24 | 1998-07-24 | Electrostatic discharge protection for salicided devices and method of making same |
US09/772,463 US6433395B2 (en) | 1998-07-24 | 2001-01-29 | Electrostatic discharge protection for salicided devices |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/122,494 Division US6211001B1 (en) | 1998-07-24 | 1998-07-24 | Electrostatic discharge protection for salicided devices and method of making same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010012666A1 true US20010012666A1 (en) | 2001-08-09 |
US6433395B2 US6433395B2 (en) | 2002-08-13 |
Family
ID=22403028
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/122,494 Expired - Lifetime US6211001B1 (en) | 1998-07-24 | 1998-07-24 | Electrostatic discharge protection for salicided devices and method of making same |
US09/772,463 Expired - Lifetime US6433395B2 (en) | 1998-07-24 | 2001-01-29 | Electrostatic discharge protection for salicided devices |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/122,494 Expired - Lifetime US6211001B1 (en) | 1998-07-24 | 1998-07-24 | Electrostatic discharge protection for salicided devices and method of making same |
Country Status (6)
Country | Link |
---|---|
US (2) | US6211001B1 (en) |
EP (1) | EP0975023B1 (en) |
JP (1) | JP2000049347A (en) |
KR (1) | KR20000011257A (en) |
DE (1) | DE69934360T2 (en) |
TW (1) | TW507354B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6952039B1 (en) | 2002-03-12 | 2005-10-04 | National Semiconductor Corporation | ESD protection snapback structure for overvoltage self-protecting I/O cells |
US20090191707A1 (en) * | 2008-01-25 | 2009-07-30 | Renesas Technology Corp. | Method of manufacturing a semiconductor device |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997020348A1 (en) * | 1995-11-30 | 1997-06-05 | Micron Technology, Inc. | Structure for esd protection in semiconductor chips |
JP2000091574A (en) * | 1998-09-07 | 2000-03-31 | Denso Corp | Semiconductor device and manufacture of semiconductor device |
US6999290B1 (en) * | 1999-04-28 | 2006-02-14 | Hitachi, Ltd. | Integrated circuit with protection against electrostatic damage |
US6339005B1 (en) * | 1999-10-22 | 2002-01-15 | International Business Machines Corporation | Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET |
KR100364426B1 (en) * | 2000-04-21 | 2002-12-11 | 주식회사 하이닉스반도체 | Device for electro static discharging |
JP2001358227A (en) * | 2000-04-26 | 2001-12-26 | Sharp Corp | Use of lightly-doped resistor for electrostatic discharge protection of output stage |
US6303414B1 (en) * | 2000-07-12 | 2001-10-16 | Chartered Semiconductor Manufacturing Ltd. | Method of forming PID protection diode for SOI wafer |
KR100353817B1 (en) * | 2000-09-27 | 2002-09-27 | 주식회사 하이닉스반도체 | Semiconductor device capable of preventing degradation of ESD protection circuit using silicididation process and method for forming the same |
TW522542B (en) * | 2000-11-09 | 2003-03-01 | United Microelectronics Corp | Electrostatic discharge device structure |
US7157782B1 (en) * | 2004-02-17 | 2007-01-02 | Altera Corporation | Electrically-programmable transistor antifuses |
KR100617053B1 (en) * | 2004-12-30 | 2006-08-30 | 동부일렉트로닉스 주식회사 | Method for Forming Transistor Of Semi-conductor Device |
KR100698096B1 (en) * | 2005-08-11 | 2007-03-23 | 동부일렉트로닉스 주식회사 | ESD protecting cirsiut and method for fabricating the same |
US20100032753A1 (en) * | 2008-05-13 | 2010-02-11 | Micrel, Inc. | MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness |
KR101668885B1 (en) | 2011-07-01 | 2016-10-25 | 매그나칩 반도체 유한회사 | ESD protection circuit |
US9461032B1 (en) * | 2015-11-05 | 2016-10-04 | Texas Instruments Incorporated | Bipolar ESD protection device with integrated negative strike diode |
US9679888B1 (en) * | 2016-08-30 | 2017-06-13 | Globalfoundries Inc. | ESD device for a semiconductor structure |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69111096T2 (en) | 1990-03-05 | 1996-04-11 | Fujitsu Ltd | High voltage MOS transistor and its manufacturing method and semiconductor device with high voltage MOS transistor and its manufacturing method. |
EP0459770B1 (en) | 1990-05-31 | 1995-05-03 | Canon Kabushiki Kaisha | Method for producing a semiconductor device with gate structure |
US5283449A (en) | 1990-08-09 | 1994-02-01 | Nec Corporation | Semiconductor integrated circuit device including two types of MOSFETS having source/drain region different in sheet resistance from each other |
JP2953192B2 (en) * | 1991-05-29 | 1999-09-27 | 日本電気株式会社 | Semiconductor integrated circuit |
US5597758A (en) * | 1994-08-01 | 1997-01-28 | Motorola, Inc. | Method for forming an electrostatic discharge protection device |
JP2715929B2 (en) | 1994-08-18 | 1998-02-18 | 日本電気株式会社 | Semiconductor integrated circuit device |
US5545909A (en) * | 1994-10-19 | 1996-08-13 | Siliconix Incorporated | Electrostatic discharge protection device for integrated circuit |
TW359886B (en) * | 1997-09-02 | 1999-06-01 | United Microelectronics Corp | Electrostatic discharge protection device and production process therefor |
US5910673A (en) * | 1997-12-04 | 1999-06-08 | Sharp Microelectronics Technology, Inc. | Locos MOS device for ESD protection |
US6171891B1 (en) * | 1998-02-27 | 2001-01-09 | Taiwan Semiconductor Manufacturing Company | Method of manufacture of CMOS device using additional implant regions to enhance ESD performance |
-
1998
- 1998-07-24 US US09/122,494 patent/US6211001B1/en not_active Expired - Lifetime
-
1999
- 1999-02-04 JP JP11027376A patent/JP2000049347A/en active Pending
- 1999-02-19 TW TW088102425A patent/TW507354B/en not_active IP Right Cessation
- 1999-03-15 EP EP99301979A patent/EP0975023B1/en not_active Expired - Lifetime
- 1999-03-15 DE DE69934360T patent/DE69934360T2/en not_active Expired - Lifetime
- 1999-05-03 KR KR1019990015845A patent/KR20000011257A/en not_active Application Discontinuation
-
2001
- 2001-01-29 US US09/772,463 patent/US6433395B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6952039B1 (en) | 2002-03-12 | 2005-10-04 | National Semiconductor Corporation | ESD protection snapback structure for overvoltage self-protecting I/O cells |
US20090191707A1 (en) * | 2008-01-25 | 2009-07-30 | Renesas Technology Corp. | Method of manufacturing a semiconductor device |
US8039378B2 (en) * | 2008-01-25 | 2011-10-18 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device |
US8278199B2 (en) | 2008-01-25 | 2012-10-02 | Renesas Electronics Corporation | Method of manufacturing a semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2000049347A (en) | 2000-02-18 |
EP0975023A1 (en) | 2000-01-26 |
DE69934360T2 (en) | 2007-12-06 |
EP0975023B1 (en) | 2006-12-13 |
DE69934360D1 (en) | 2007-01-25 |
TW507354B (en) | 2002-10-21 |
US6211001B1 (en) | 2001-04-03 |
US6433395B2 (en) | 2002-08-13 |
KR20000011257A (en) | 2000-02-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5169794A (en) | Method of fabrication of pnp structure in a common substrate containing npn or MOS structures | |
US6211001B1 (en) | Electrostatic discharge protection for salicided devices and method of making same | |
EP1543546B1 (en) | Process for fabricating an isolated field effect transistor in an epi-less substrate | |
KR100220441B1 (en) | Manufacturing process of spacer in the semiconductor device | |
US5661046A (en) | Method of fabricating BiCMOS device | |
US6642088B1 (en) | Silicon-controlled rectifier structures on silicon-on insulator with shallow trench isolation | |
KR100230610B1 (en) | Bicmos device having self-aligned well tap and method of fabrication | |
US6284581B1 (en) | Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors | |
US7285830B2 (en) | Lateral bipolar junction transistor in CMOS flow | |
US5001073A (en) | Method for making bipolar/CMOS IC with isolated vertical PNP | |
JPH0799764B2 (en) | Integrated circuit and manufacturing method thereof | |
US5107321A (en) | Interconnect method for semiconductor devices | |
US5231042A (en) | Formation of silicide contacts using a sidewall oxide process | |
JPH0855924A (en) | Step of processing bicmos including surface channel pmos transistor | |
JP2001156290A (en) | Semiconductor device | |
EP0239216A2 (en) | CMOS compatible bipolar transistor | |
US5010034A (en) | CMOS and bipolar fabrication process using selective epitaxial growth scalable to below 0.5 micron | |
US6080612A (en) | Method of forming an ultra-thin SOI electrostatic discharge protection device | |
KR100429520B1 (en) | Using lightly doped resistor for output stage electrostatic discharge protection | |
US20090159982A1 (en) | Bi-CMOS Semiconductor Device and Method of Manufacturing the Same | |
JP3013784B2 (en) | Method for manufacturing BiCMOS integrated circuit | |
JP2617226B2 (en) | Method for manufacturing CMOS device | |
KR920000832B1 (en) | Method of fabricating bicmos transistor | |
JPH09134968A (en) | Manufacture of semiconductor device | |
JP2003124229A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |