JP2003124229A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend a depletion layer of an impurity diffusion layer under a gate electrode while suppressing an increase in the resistance of the impurity diffusion layer. SOLUTION: There are provided a gate electrode 12 formed via a gate oxide film 17 on a P well layer 3 defined by a field oxide film 6 for device isolation, and an N type source region 18 and drain region 19 provided on a P well layer 3 located on opposite sides of the gate electrode 12. At least the drain region 19 is provided from a position where it overlaps the gate electrode 12 to the field oxide film 6, and impurity diffusion concentration is adjusted by multiple ion doping such that the impurity diffusion concentration is lowest below the gate electrode 12, and the impurity diffusion concentration is distributed denser as it goes away from the gate electrode 12. The resistance of the impurity diffusion layer is substantially the same as in a prior art, and the N type drain region 19 where a depletion layer below the gate electrode 12 is extended can be provided on the P well layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for application to an integrated circuit or the like in which an analog circuit and a digital circuit are mixedly mounted on the same semiconductor substrate, and a manufacturing method thereof. Specifically, the impurity diffusion layer formed by implanting impurity ions of the opposite conductivity type into one semiconductor layer is injected with multiple impurity ions to adjust its diffusion concentration, and then the end portion of the impurity diffusion layer is included. A gate electrode is formed on the semiconductor layer in the region with an insulating film interposed so that the depletion layer of the impurity diffusion layer can be extended under the gate electrode.

[0002]

2. Description of the Related Art In recent years, MOS-IC (Metal Oxide Semi)
The manufacturing process of conducyor structure-integrated circuits) is becoming more and more miniaturized. With this,
The power supply voltage (Vdd) for driving the MOS transistor is
It tends to be set lower than 5V. Especially 0.35
The Vdd of a MOS transistor manufactured by a process finer than the μm rule is generally 3.3 V or less.

On the other hand, there are still many electronic components that require operation at 5V. In many cases, these electronic components and a MOS-IC are mixed and used.
As an example thereof, for example, BiC (Bipolar Complement
ary) MOS-IC.

This BiCMOS-IC is an integrated circuit in which an analog circuit and a digital circuit are mounted together. In this,
The analog circuit is composed of bipolar transistors and the like. In addition to the CMOS transistor, the digital circuit is composed of a low voltage drive type MOS transistor whose threshold voltage is set to be particularly low, a depletion type MOS transistor and the like. In addition, BiCMO
The S-IC may have a built-in driver for handling ON / OFF of the 5V power supply. This BiCMOS-
When the 0.35 μm rule is applied to the IC, the breakdown voltage of each MOS transistor corresponds to a voltage of 3.3 V or less.

Therefore, for example, when a MOS transistor having a rule of 0.35 μm is used as a driver and a voltage of 5 V is applied between the source and drain regions of the MOS transistor, a MOS transistor having a hot carrier resistance, an off breakdown voltage, or the like is used. Reliability is an issue.

Particularly, when an N-type MOS transistor is used as a driver, its hot carrier resistance becomes a serious problem. Therefore, in the drain region of the N-type MOS transistor, a low-concentration N-type diffusion layer for relaxing an electric field is formed at a lower concentration and deeper, and hot carriers are generated even when a drain voltage of 5 V is applied to the drain region. We need to be able to suppress it.

FIG. 8 shows a first semiconductor device 80 according to a conventional example.
3 is a cross-sectional view showing a configuration example of FIG. This semiconductor device 80 is
BiCMOS-IC, 5V voltage is turned on and off
High withstand voltage NMOS transistor (Hv-NMO
(Also referred to as S) 81 is provided on the semiconductor substrate 82.

The high breakdown voltage structure of the Hv-NMOS 81 is as follows. First, the field oxide film 84 is provided between the source diffusion layer 85 connected to the source electrode of the Hv-NMOS 81 and the drain diffusion layer 86 connected to the drain electrode. Under the field oxide film 84 and the drain diffusion layer 86, an N-type offset diffusion layer for relaxing the electric field is formed.
(Hereinafter, also referred to as Noffset) 87 is provided.

Further, the gate electrode 83 of the Hv-NMOS 81
Are provided so as to extend half over the field oxide film 84. With this structure, the Hv-NMOS 81
Is more resistant to hot carriers than other MOS transistors (not shown) mounted on the same semiconductor substrate 82.
The off breakdown voltage is high. Below, Hv-NMOS81
Such a high breakdown voltage structure is referred to as a LOCOS offset gate structure.

9 to 11 are process diagrams showing a method (Nos. 1 to 3) for manufacturing the semiconductor device 80. First, a silicon oxide film (not shown) of about 50 nm is formed on the semiconductor substrate 82 shown in FIG. 9A. Next, as shown in FIG. 9B,
By photolithography, on this silicon oxide film
Resist pattern 8 with an opening in the area where Noffset is formed
8 is formed. Then, using this resist pattern 88 as a mask, phosphorus is ion-implanted into the semiconductor substrate 82.
The implantation energy at this time is about 40 to 50 keV, and the implantation amount of phosphorus is 1.5E13 / cm ^{2 to} 2.0E1.
It is about 3 / cm ² .

Resist pattern 88 and semiconductor substrate 82
After removing the upper silicon oxide film, a silicon oxide film (not shown) of about 10 nm is formed again on the semiconductor substrate. Then, as shown in FIG. 9C, a silicon nitride film 89 is selectively formed on the semiconductor substrate 82. Then 1
A LOCOS process is performed at a temperature of 000 ° C. to 1050 ° C. to form a field oxide film 84 as shown in FIG. 10A. The thickness of the field oxide film 84 is 350 nm
It is about 500 nm. Also, by this heat treatment,
The phosphorus ions implanted previously diffuse to the lower part of the field oxide film 84 to form the Noffset 87.

Thereafter, as shown in FIG. 10B, boron is added from 1 MeV to 20 in only a region of the semiconductor substrate 82 where an N-type MOS transistor (hereinafter, also referred to as NMOS) is formed.
The P well layer 91 is formed by ion implantation with energy of keV divided into several times.

Next, the wafer surface including the P well layer 91 is cleaned by wet etching. Then, the wafer surface including the cleaned P well layer 91 is thermally oxidized to 7 to
A 10 nm gate oxide film (not shown) is formed. After forming the gate oxide film, a phosphorus-doped polysilicon film and tungsten silicide are sequentially deposited on the gate oxide film. Then, these tungsten silicide and polysilicon are patterned by photolithography and dry-etched. As a result,
0C gate electrode 83 and wiring pattern (not shown)
Can be formed. Further, the gate electrode 83 is overlapped on the field oxide film 84 to form a LOCOS offset gate structure.

Next, as shown in FIG. 11A, Hv-NMOS 8
A resist pattern 92 is formed on the semiconductor substrate 82 so that the first source region and the gate electrode 83 are opened. Then, using this resist pattern 92 as a mask, arsenic and boron are sequentially ion-implanted. This allows
A low-concentration N-type diffusion layer (hereinafter,
(Also referred to as NLDD) 93 for punch through stopper
P_Pocket 94 can be formed.

Thereafter, as shown in FIG. 11B, a spacer 95 of a silicon oxide film is formed on the side wall of the gate electrode 83. Then, a resist pattern 96 which opens an area where the Hv-NMOS 81 is formed is formed on the semiconductor substrate 82, and arsenic is ion-implanted using the resist pattern 96 as a mask. Thereby, the source diffusion layer 85 can be formed in the source region of the semiconductor substrate 82, and the drain diffusion layer 86 can be formed in the drain region.

Then, an interlayer insulating film is formed on the entire surface of the semiconductor substrate 82 to form a source electrode and a drain electrode, respectively. A predetermined wiring pattern is further formed on the source electrode and the drain electrode to complete the semiconductor device 80 shown in FIG.

As shown in FIG. 8, the gate length L2 of the Hv-NMOS 81 is about 3 μm. The diffusion depth of Noffset 87 is about 0.4 μm, and the surface concentration is 1.0E18 / cm ^3.
It is a degree. As a result, the off breakdown voltage of the transistor is 2
The on-state breakdown voltage is about 0V and the drain voltage is 5.5V.
High breakdown voltage is achieved.

FIG. 12 is a sectional view showing a structural example of a second semiconductor device 90 according to a conventional example. This semiconductor device 90 is similar to the above-described semiconductor device 80 in BiCMOS.
-IC, high breakdown voltage NMOS transistor (Hv-NMO
S) 99 is provided on the semiconductor substrate 82.

The Hv-NMOS 99 has Noffset 98 in the source region and the drain region. This Noffset98
Is a low concentration N type diffusion layer (NLDD) of another NMOS transistor (not shown) provided on the same semiconductor substrate 82.
And the impurity diffusion concentration is low. As a result, the Hv-NMOS 99 has a higher breakdown voltage than other NMOS transistors provided on the same semiconductor substrate 82.

FIGS. 13 and 14 are process diagrams showing a method (Nos. 1 and 2) for manufacturing the semiconductor device 90. As shown in FIG. 13A, first, the field oxide film 84 is formed on the semiconductor substrate 82.
And a P-well layer 91 are formed. Next, as shown in FIG. 13B, a gate oxide film and a gate electrode 97 are formed on the semiconductor substrate 82.
To form. Up to this point, there are no special additional steps as compared with the semiconductor device 80 described above.

After forming the gate electrode 97, an MO other than the Hv-NMOS 99 (see FIG. 12) formed on the semiconductor substrate 82.
An NLDD and a low-concentration P-type diffusion layer (hereinafter also referred to as PLDD) are formed in an S transistor formation region (not shown).

Thereafter, as shown in FIG. 13C, a resist pattern 59 having an opening only in a region of the semiconductor substrate 82 where the Hv-NMOS 99 is to be formed is formed.
Is used as a mask to implant phosphorus ions. The implantation energy at this time is about 50 keV, and the implantation amount of phosphorus is 8
It is about E12 / cm ^{2 to} 8E13 / cm ² . As a result, the Noffset 98 is added to the source / drain region of the Hv-NMOS 99.
Can be formed.

Next, a spacer is formed on the side wall of the gate electrode 97. Then, as shown in FIG. 14A, Noffset9
A resist pattern 79 having openings in the source / drain regions is formed so that the gate electrode side of 8 is left with a length of about 0.2 μm to 1.2 μm. This resist pattern 79 is used as a mask to form a mask in the region where the Hv-NMOS 99 is formed.
Arsenic of about E15 / cm ² is ion-implanted. As a result, the source diffusion layer 77 can be formed in the source region and the drain diffusion layer 78 can be formed in the drain region.

Thereafter, as shown in FIG. 14B, an interlayer insulating film 57 is formed on the semiconductor substrate 82. Then, similarly to the semiconductor device 80 described above, a source electrode and a drain electrode, and a wiring pattern following the electrodes are sequentially formed to complete the semiconductor device 90 shown in FIG.

As shown in FIG. 12, the gate length L3 of the Hv-NMOS 81 is about 1.5 μm. Also, Noffset98
Depth (Xj) is about 0.15 to 0.2 μm, and the surface concentration is 7.0E17 / cm ^{3 to} 1.0E18 / c.
It is about m ³ .

On the other hand, the depth of the NLDD of another NMOS transistor formed on the same semiconductor substrate 82 (X
j) is about 0.05 to 0.1 μm, and the surface concentration is 3
It is about E18 / cm ³ . That is, the Noffset 98 of the Hv-NMOS 99 is higher than that of the NLDD of other NMOS transistors.
Is deeper and the impurity diffusion concentration is thinner. As a result, the Hv-NMOS99 transistor has an off breakdown voltage of about 12 V and an on breakdown voltage of 5.5 V as its drain voltage.
At a voltage of about V, high breakdown voltage is achieved.

[0027]

By the way, according to the first semiconductor device 80 of the conventional method, the LOCOS offset structure is adopted in the Hv-NMOS 81 in order to enhance the hot carrier resistance and the off breakdown voltage. It was Therefore, the gate length L2 of the Hv-NMOS 81 becomes as long as about 3 μm, and there is a possibility that the semiconductor device 80 cannot be further downsized.

Further, according to the second semiconductor device 90 of the conventional method, in order to maintain high hot carrier resistance and to shorten the gate length as compared with the first semiconductor device 80, the Hv-NMOS 99 is provided. The impurity diffusion concentration of the obtained Noffset 98 was thinned to about 7E17 / cm ^{3 to} 1.0E18 / cm ³ . Therefore, the resistance value of the Noffset 98 becomes high, and there is a problem that the loss amount of the current flowing through the Hv-NMOS 99 is large.

Further, in order to reduce the resistance value of the Noffset 98, if the impurity diffusion concentration is adjusted to be high,
There is a problem that the extension of the depletion layer of Noffset 98 under the gate electrode 97 becomes short and the hot carrier resistance deteriorates.

Therefore, the present invention solves such a problem, and the depletion layer of the impurity diffusion layer is kept in the gate electrode while suppressing the increase of the resistance value of the impurity diffusion layer as compared with the conventional method. An object of the present invention is to provide a semiconductor device that can be stretched below and a manufacturing method thereof.

[0031]

SUMMARY OF THE INVENTION The above-mentioned problems are solved by a gate electrode provided on a semiconductor layer of one conductivity type defined by an insulating film for element isolation with an insulating film interposed, and on both sides of the gate electrode. A pair of opposite-conductivity-type impurity diffusion layers provided in the semiconductor layer, and at least one of the impurity diffusion layers is provided at a position from the position overlapping with the gate electrode to the insulating film for element isolation. The impurity diffusion concentration is adjusted by multiple ion implantation, and the impurity diffusion concentration is lowest under the gate electrode, and the impurity diffusion concentration is distributed deeper as the distance from the gate electrode increases.

According to the semiconductor device of the present invention, the resistance value is almost the same as that of the conventional method, and the impurity diffusion layer of the opposite conductivity type in which the depletion layer under the gate electrode is extended is of the one conductivity type. The semiconductor layer can be provided.

In the method of manufacturing a semiconductor device according to the present invention, a step of defining a transistor formation region by isolating a semiconductor layer of one conductivity type with an insulating film and both sides of the region where a gate electrode is formed in the transistor formation region are formed. A step of implanting impurity ions of opposite conductivity type into at least one of the semiconductor layers to form an impurity diffusion layer, and a step of multiply implanting impurity ions of opposite conductivity type into this impurity diffusion layer to adjust the impurity diffusion concentration And a step of forming a gate electrode with an insulating film interposed on the semiconductor layer in a region including at least an end portion of the impurity diffusion layer.

According to the method of manufacturing a semiconductor device of the present invention, the impurity diffusion concentration of the impurity diffusion layer can be the lowest under the gate electrode, and the impurity diffusion concentration can be increased as the distance from the gate electrode increases.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention.

In this embodiment, in the transistor formation region defined in the semiconductor layer of one conductivity type, impurity ions of the opposite conductivity type are implanted into at least one semiconductor layer on both sides of the region where the gate electrode is formed. Impurity ions are multiply injected into the impurity diffusion layer to adjust its diffusion concentration, and then a gate electrode is formed on the semiconductor layer in the region including the end portion of the impurity diffusion layer with an insulating film interposed therebetween. Of the impurity diffusion layer under the gate electrode so that the depletion layer of the impurity diffusion layer can be extended under the gate electrode while suppressing an increase in the resistance value of the impurity diffusion layer as compared with the conventional method. It was done.

The semiconductor device 100 shown in FIG. 1 is a BiCM.
A high breakdown voltage NMOS transistor (Hv-NMOS) 10 which is an OS-IC and is an example of a first field effect transistor.
And a depletion type NMOS (hereinafter, also referred to as Dep-NMOS) 20 which is an example of the second field effect transistor.
A low threshold voltage NMOS transistor (hereinafter also referred to as L-Vth-NMOS) 30 as an example of a third field effect transistor, and a logic NMOS (hereinafter simply referred to as NM).
Also called OS 40, and PMOS for logic (below,
The same semiconductor substrate is provided with (also simply referred to as PMOS) 50.

First, the semiconductor device 100 includes the semiconductor substrate 1
have. This semiconductor substrate 1 is, for example, a P-type (10
0) silicon wafer. An N-type isolation layer 2 is provided in a predetermined region of the semiconductor substrate 1, and the region is electrically separated from the semiconductor substrate 1. A first P-well layer 3 and a second P-well layer 4, which are an example of a semiconductor layer of one conductivity type, are further provided on the N-type isolation layer 2.

The above-mentioned Hv-NMOS 10 and Dep-NMOS 20
The L-Vth-NMOS 30 and the NMOS 40 are provided in the P well layer 3. In addition, the N well layer 5 is formed on the P well layer 4.
Is provided, and the PMOS 50 is provided on the N well layer 5. Each MOS transistor is, from the left side of FIG. 1, Hv-NMOS 10, NMOS 40, PMOS 50, L-Vth-NMOS.
30 and Dep-NMOS 20 are arranged in this order, and each MO
The S transistors are separated from each other by a field oxide film 6 which is an example of an insulating film for separating elements.

Among these, the Hv-NMOS 10 shown in FIG.
Has a gate oxide film 17 as an example of an insulating film on the P well layer 3. This gate oxide film 17 is, for example,
It is a silicon oxide film having a thickness of about 15 nm.

The Hv-NMOS 10 has a gate oxide film 17
It has a gate electrode 12 on it. This gate electrode 12
Is about 100 nm of phosphorus-doped polysilicon and 1
It has a polycide structure made of tungsten silicide of about 00 nm. When the gate length of the gate electrode 12 is L1, L1 = about 1.5 μm. A spacer 13 is provided on the side wall of the gate electrode 12.

Further, the P well layer 3 on both sides of the gate electrode 12 is provided with an N type source region 18 and a drain region 19 as an example of a pair of opposite conductivity type impurity diffusion layers. The source region 18 and the drain region 19 are provided at positions where they overlap with the gate electrode 12 and reach the field oxide film 6.

A source electrode 8 and a drain electrode 9 are provided on the source region 18 and the drain region 19, respectively, and reach the interlayer insulating film 57 covering the Hv-NMOS 10.

By the way, in the Hv-NMOS 10, the N-type first electric field relaxation layers 14 A and 1 are formed at the positions where the source region 18 and the drain region 19 overlap with the gate electrode 12.
4B are provided respectively. In addition, the gate electrode 12
A source region 18 between the gate electrode 12 and the source electrode 8;
In the drain region 19 between the drain electrode 9 and the drain electrode 9, N-type second electric field relaxation layers 15A and 15B are provided, respectively. Further, a source diffusion layer 11A and a drain diffusion layer 11B are provided in the source region 18 below the source electrode 8 and the drain region 19 below the drain electrode 9, respectively.

The N-type impurity ions constituting the electric field relaxation layers 14A and 14B and the electric field relaxation layers 15A and 15B are
For example, phosphorus ion. Electric field relaxation layers 14A and 14B
The diffusion concentration of phosphorus ion is, for example, 4.0E17 / c.
m is ^{3 ~5.0E17} / cm ³ about. The diffusion concentration of phosphorus ions in the electric field relaxation layers 15A and 15B is, for example, about 7.0E17 / cm ^{3 to} 1.0E18 / cm ³ . That is, the diffusion concentration of phosphorus ions in the electric field relaxation layers 14A and 14B overlapping the gate electrode 12 is
The diffusion concentration is lower than the diffusion concentration of the electric field relaxation layers 15A and 15B separated from the gate electrode.

When the semiconductor device 100 having such Hv-NMOS 10 is compared with the first semiconductor device 80 according to the conventional example (see FIG. 8), the semiconductor device 100 is Hv-NMOS.
Since the LOCOS offset structure is not used for the Hv-NMOS 10, the element size of the Hv-NMOS 10 is smaller than that of the Hv-NMOS 81 of the semiconductor device 80. That is, while the gate length L2 of the Hv-NMOS 81 is about 3.0 μm, the Hv-NMOS 81
The gate length L1 of 10 is about 1.5 μm.

When the semiconductor device 100 and the second semiconductor device 90 according to the conventional example (see FIG. 12) are compared, the diffusion concentration of phosphorus ions in the electric field relaxation layer overlapping the gate electrode is higher than that in the Hv-NMOS 99. Hv-NMOS10 is lower. That is, the phosphorus ion diffusion concentration of Noffset 98 of the Hv-NMOS 99 is about 7.0E17 / cm ^{3 to} 1.0E18 / cm ³ , while the diffusion concentration of the electric field relaxation layers 14A and 14B of the Hv-NMOS 10 is 4.0E17. / Cm ³ ~ 5.0E
It is about 17 / cm ³ . Also, Noffset98 and Hv-NMO
The impurity diffusion concentrations of the electric field relaxation layers 15A and 15B of S10 are set to be approximately the same.

Thus, for example, when a constant drain current is passed through the Hv-NMOS 99 and Hv-NMOS 10 having a constant gate length (about L3 = L1 = 1.5 μm), the loss amount of both drain currents is It is done about the same. Also,
The depletion layer under the gate electrode is Hv-NMOS1 rather than Hv-NMOS99.
0 is stretched. Therefore, rather than Hv-NMOS99, H
The v-NMOS 10 can suppress the generation of hot carriers.

Next, a method of manufacturing the semiconductor device 100 according to the present invention will be described. 3 to 7 show the semiconductor device 10.
It is process drawing which shows the manufacturing method (No. 1-5) of 0. Here, the above-mentioned Hv-NMOS 10, Dep-NMOS 20, and L-Vth
-NMOS 30, NMOS 40, and PMOS 50 are included in the semiconductor substrate 1.
It is assumed that they are simultaneously formed in parallel.

First, the semiconductor substrate 1 shown in FIG. 3A is prepared. Next, as shown in FIG. 3B, the MOS of the semiconductor substrate 1 is
Phosphorus ions are selectively implanted at an acceleration voltage of about 1 MeV in a region where a transistor is formed. As a result, the N-type separation layer 2 that is electrically separated from the semiconductor substrate 1 is formed on the semiconductor substrate 1.

Next, the buried collector of the NPN transistor is formed by vapor diffusion of antimony (not shown). And resistivity 1.0 Ω · cm to 5.0 Ω · c
3C, an N-type silicon crystal having a thickness of 0.5 μm to 1.0 μm is epitaxially grown on the entire surface of the semiconductor substrate 1.
The epitaxial layer 7 shown in is formed.

The epitaxial layer 7 is thermally oxidized to 1
After forming a pad oxide film (not shown) of about 0 nm,
A silicon nitride film of about 100 nm is formed on the pad oxide film. The silicon nitride film is formed by CVD.

Then, as shown in FIG. 4A, the silicon nitride film 23 is selectively etched so that the silicon nitride film 23 is left only in the formation region of the MOS transistor. After that, LOCO is performed at a temperature of 1000 ° C to 1050 ° C.
Carry out the S process. As a result, as shown in FIG. 4B, the field oxide film 6 defining the formation region of the MOS transistor can be formed on the epitaxial layer 7 of the semiconductor substrate 1. The film thickness of the formed field oxide film 6 is, for example, about 350 nm to 500 nm.

Next, as shown in FIG. 4C, N-type MOS
Boron is ion-implanted several times at 1 MeV to 20 keV only in the region where the transistor is formed, and the first P-well layer 3 is formed.

After forming the P well layer 3, the semiconductor substrate 1
Apply photoresist to the entire surface of. Next, this photoresist is exposed and developed by photolithography to form an L-Vth-NMOS on the semiconductor substrate 1 as shown in FIG. 5A.
A first resist pattern 60 having an opening in a region where 30 (see FIG. 1) is formed and in a region where the source region 18 and the drain region 19 (see FIG. 2) of the Hv-NMOS 10 are formed.
To form. Using this resist pattern 60 as a mask, phosphorus ions, which are an example of impurity ions of the opposite conductivity type, are implanted into the semiconductor substrate 1 (hereinafter, also referred to as first ion implantation).

As a result, the L-Vth-NMOS 3 of the semiconductor substrate 1 is
The N_Low_Vth diffusion layer 31 can be formed in the region where 0 is formed. The N_Low_Vth diffusion layer 31 is for adjusting the threshold voltage of the L-Vth-NMOS 30. Also, this N_Low_
At the same time when the Vth diffusion layer 31 is formed, the source region 18 and the drain region 19 can be formed in the Hv-NMOS 10. The implantation energy in the first ion implantation is 50 keV, and the phosphorus ion implantation amount is 3.5E12 / cm ² ~.
It is about 4.0E12 / cm ² .

After removing the resist pattern 60 by ashing, a photoresist is applied to the entire surface of the semiconductor substrate 1 again. Next, this photoresist is exposed to a predetermined pattern and developed to form a semiconductor substrate 1 as shown in FIG. 5B.
A second resist pattern 61 is formed on top.

The resist pattern 61 has an opening on the region of the semiconductor substrate 1 where the Dep-NMOS 20 (see FIG. 1) is formed. The resist pattern 61 is
Openings are also provided on the source region 18 and the drain region 19 other than the regions used as the first electric field relaxation layers 14A and 14B (see FIG. 2). In FIG. 5B, about 0.2 from one end of the source region 18 and the drain region 19 on the side where the gate electrode 12 (see FIG. 2) is formed.
The resist pattern 61 masks up to about μm to 0.6 μm.

Phosphorus ions are implanted into the semiconductor substrate 1 using the resist pattern 61 as a mask (hereinafter, also referred to as a second ion implantation). As a result, the N_Dep diffusion layer 21 is formed in the region of the semiconductor substrate 1 where the Dep-NMOS 20 is formed. This N_Dep diffusion layer 21 is a Dep-NMOS
It is for adjusting the threshold voltage of 20.

At the same time when the N_Dep diffusion layer 21 is formed, phosphorus ions are multiply injected into the unmasked regions of the source region 18 and the drain region 19 of the Hv-NMOS 10 to adjust the diffusion concentration thereof. The implantation energy in the second ion implantation is 50 keV, and the phosphorus ion implantation amount is 5.0E12 / cm ^{2 to} 6.0E12 / c.
It is about m ² . As a result, the electric field relaxation layers 14A and 14B are defined in the source region 18 and the drain region 19.

Returning to FIG. 5B, after removing the resist pattern 61, the semiconductor substrate 1 is coated with photoresist again. Then, as shown in FIG. 5C, a third resist pattern 62 having an opening only in the region where the PMOS 50 (see FIG. 1) is formed is formed on the semiconductor substrate 1.

Using the resist pattern 62 as a mask, boron ions are implanted into the semiconductor substrate 1 to form the P well layer 4. The ion implantation energy at this time is 85
It is about 0 keV, and the implantation amount of boron ions is 5.0E.
It is about 12 / cm ² .

Further, using the resist pattern 62 as a mask, phosphorus and arsenic are ion-implanted into the semiconductor substrate 1 in several times. Thereby, the P well layer 4 previously formed is formed.
The N well layer 5 can be formed thereon. The ion implantation energies of these phosphorus and arsenic are about 700 MeV to 200 keV.

Thereafter, using the resist pattern 62 as a mask, boron ions for adjusting the threshold voltage are implanted into the N well layer 5. The implantation energy of boron ions at this time is, for example, about 20 keV, and the implantation amount is 5E.
It is a ^{12 / cm 2 ~7E12 / cm 2} .

After the ion implantation for adjusting the threshold voltage of the PMOS 50 is completed, the resist pattern 62 is removed by ashing. Then, the pad oxide film covering the semiconductor substrate 1 is removed by wet etching.

After the entire surface of the wafer including the semiconductor substrate 1 is sufficiently cleaned by wet etching, the semiconductor substrate 1 is thermally oxidized to form a gate oxide film in at least the formation region of each MOS transistor described above. The thickness of the formed gate oxide film is about 7 nm to 10 nm.

Next, phosphorus-doped polysilicon (phosphorus-doped polysilicon) is deposited to a thickness of about 100 nm on the entire surface of the semiconductor substrate 1 having the gate oxide film formed thereon. Tungsten silicide is further deposited on the phosphorus-doped polysilicon by CVD to a thickness of about 100 nm to form a so-called polycide structure.

Thereafter, each M formed on the semiconductor substrate 1
The gate electrode and wiring of the OS transistor are covered with a resist pattern (not shown), and dry etching is performed. As a result, the gate electrode 12 and the wiring pattern (not shown) shown in FIG. 6A are formed.

Next, as shown in FIG. 6B, a fourth resist pattern 6 having an opening in the region where the PMOS 50 is formed.
5 is provided on the semiconductor substrate 1. Then, using the resist pattern 65 as a mask, boron ions are implanted into the semiconductor substrate 1.

As a result, in the region where the PMOS 50 is formed,
A low-concentration P-type diffusion layer (PLDD) 68 for relaxing an electric field can be formed. Ion implantation energy at this time is 60 keV
The amount of boron ion implantation is 3.0E13 / c
It is about m ^{2 to} 4.0E13 / cm ² .

Further, with the resist pattern 65 as a mask, the PLDD 6 is used as a punch-through stopper.
Phosphorus is ion-implanted at an angle of 8, and N_Pocket69
To form. The implantation energy of phosphorus ions at this time is, for example, about 30 keV, and the implantation amount is 1.
It is about 0E13 / cm ² .

Next, as shown in FIG. 6C, NMOS 40, L-
A fifth resist pattern 71 having an opening in a region where the Vth-NMOS 30 and Dep-NMOS 20 are formed is provided on the semiconductor substrate 1. Then, using this resist pattern 71 as a mask, arsenic is ion-implanted into the semiconductor substrate 1.

As a result, the NMOS 40, the L-Vth-NMOS 30,
A low concentration N for electric field relaxation is formed in the region where the Dep-NMOS 20 is formed.
A type diffusion layer (NLDD) 66 can be formed. The ion implantation energy at this time is about 60 keV, and the arsenic ion implantation amount is 3.0E13 / cm ^{2 to} 4.0E13 / c.
It is about m ² .

Further, the photoresist 71 is used as a mask for the purpose of a punch-through stopper, and the NLDD 66 is used.
Boron is obliquely ion-implanted to the P_Pocket67
To form. The implantation energy of boron ions at this time is, for example, about 30 keV, and the implantation amount is 1.
It is about 0E13 / cm ² .

Next, the photoresist 71 is removed by ashing. Then, the entire surface of the semiconductor substrate 1 is 250 nm
A silicon oxide film is deposited by CVD. This silicon oxide film is anisotropically etched to form the spacer 70 shown in FIG. 7A on the side wall of the gate electrode 12.

Then, a sixth resist pattern 37 is formed on the semiconductor substrate 1. This resist pattern 37 is
The NMOS 40, the L-Vth-NMOS 30, and the Dep-NMOS 20 have an opening on a region where they are formed. The resist pattern 37 also has openings on the source region 18 and the drain region 19 other than the region used as the electric field relaxation layer of the Hv-NMOS 10.

In FIG. 7A, 0.2 μm from one end of the source region 18 and the drain region 19 on the gate electrode 12 side.
Up to about 0.8 μm is masked by the resist pattern 37. Arsenic is ion-implanted into the semiconductor substrate 1 using the resist pattern 37 as a mask to form the N-type source diffusion layer 11A and the drain diffusion layer 11B. The implantation energy of arsenic ions at this time is 30 to 40 ke.
The dose of V and arsenic ions is about 5E15 / cm ² .

Further, by forming the source diffusion layer 11A and the drain diffusion layer 11B, the second electric field relaxation layers 15A and 15B are defined in the source region 18 and the drain region 19 of the Hv-NMOS 10.

By the way, in the method of manufacturing the semiconductor devices 80 and 90 according to the conventional example, the Hv-NMOS is provided with Noffset for electric field relaxation.
In order to form the layer, it was necessary to provide a dedicated photomask process and an ion implantation process, respectively.

On the other hand, in the method of manufacturing the semiconductor device 100, the step of forming the electric field relaxation layers 14A and 14B of the Hv-NMOS 10 can be combined with the step of forming the N_Low_Vth diffusion layer 31 for adjusting the threshold voltage. . In addition, the electric field relaxation layer 1
5A and 15B forming process, N_Dep for threshold voltage adjustment
It could be used also in the step of forming the diffusion layer 21.

That is, in order to form the electric field relaxation layer on the Hv-NMOS 10, it is not necessary to bother to provide a dedicated photomask step and ion implantation step. As a result, the cycle time in the manufacturing process of the semiconductor device can be surely shortened and the manufacturing cost thereof can be surely reduced as compared with the conventional method.

Next, the resist pattern 37 is removed.
Then, as shown in FIG. 7B, a seventh resist pattern 73 having an opening in a region where the PMOS 50 is formed is formed on the semiconductor substrate 1. Boron is ion-implanted into the semiconductor substrate 1 using the resist pattern 73 as a mask to form a P-type source diffusion layer 74A and a drain diffusion layer 74B. The implantation energy of boron ions at this time is 30
Is about 40 keV, and the injection amount is 3E15 / cm.
After forming the P-type source diffusion layer 74A and the drain diffusion layer 74B of about ² , the resist pattern 73 is removed. Then, the semiconductor substrate 1 is set to RTA (Rapid Thermal
Anneal) is performed at 1000 ° C. for about 10 seconds to activate the implanted impurity ions.

Next, as shown in FIG. 7C, BPSG (Bo
A ron phosphorous Silicate Glass) film 75 is deposited on the semiconductor substrate 1 to a thickness of about 600 nm. And this BPSG
The film 75 is annealed at 900 ° C. for about 10 minutes to be flattened.

After that, the BPSG film 75 is selectively dry-etched to form a contact hole on the electrode forming region of each MOS transistor described above. Then, TiN is formed on the entire surface of the BPSG film 75 in which the contact hole is formed.
Sputtering barrier metal such as A tungsten film of about 600 nm is further formed on this barrier metal by CVD. At this time, the contact hole provided in the BPSG film 75 is filled with the barrier metal and the tungsten film.

Next, this tungsten film is etched back to be flattened. Then, AlCu of about 0.5 μm is formed by sputtering on the flattened tungsten film. Thereafter, this AlCu is selectively etched to form a wiring pattern. As a result, the semiconductor device 100 shown in FIG. 1 is completed.

Thus, the semiconductor device 10 according to the present invention
0 indicates that the P well layer 3 on both sides of the gate electrode 12 has N
A source region 18 and a drain region 19 of a mold, and at least the drain region 19 is provided at a position where it overlaps with the gate electrode 12 to a field oxide film 6 for element isolation which defines the P well layer 3. The impurity diffusion concentration is adjusted by multiple ion implantation,
The impurity diffusion concentration is the lowest under the gate electrode 12, and the impurity diffusion concentration is distributed deeper as the distance from the gate electrode 12 increases.

Therefore, it is possible to provide the P-well layer 3 with the N-type drain region 19 having substantially the same resistance value as that of the conventional method and having the extended depletion layer under the gate electrode 12. This reduces the amount of current loss,
Moreover, the Hv-NMOS 10 having improved hot carrier resistance can be provided.

In this embodiment, the first electric field relaxation layers 14A and 14A are formed in the source region 18 and the drain region 19, respectively.
The case of forming B and the second electric field relaxation layers 15A and 15B has been described. However, since hot carriers are mainly generated near the interface between the channel region and the drain region 19, these electric field relaxation layers may be formed only in the drain region 19.

[0089]

According to the semiconductor device of the present invention, one conductivity type semiconductor layer on each side of the gate electrode is provided with a pair of opposite conductivity type impurity diffusion layers, at least one of which overlaps with the gate electrode. The impurity diffusion concentration is adjusted by multiple ion implantation, and the impurity diffusion concentration is the lowest under the gate electrode, and the impurity diffusion is performed as the distance from the gate electrode increases. It is composed of a dense distribution.

With this structure, the one conductivity type semiconductor layer can be provided with an impurity diffusion layer of the opposite conductivity type, which has substantially the same resistance value as that of the conventional method and in which the depletion layer under the gate electrode is extended. it can. Therefore, a transistor with a small amount of current loss and improved hot carrier resistance can be provided.

According to the method of manufacturing a semiconductor device of the present invention, after a semiconductor layer of one conductivity type is isolated by an insulating film to define a transistor formation region, a region where a gate electrode is formed is formed in the transistor formation region. Impurity ions of opposite conductivity type are implanted into at least one of the semiconductor layers on both sides to form impurity diffusion layers of opposite conductivity type in the impurity diffusion layer, and the diffusion concentration is adjusted.
A gate electrode is formed on the semiconductor layer in a region including at least an end portion of the impurity diffusion layer with an insulating film interposed.

With this structure, the impurity diffusion concentration of the impurity diffusion layer can be minimized below the gate electrode, and the impurity diffusion concentration can be increased as the distance from the gate electrode increases.

Therefore, as compared with the conventional method, the depletion layer of the impurity diffusion layer can be extended under the gate electrode while suppressing the increase of the resistance value of the impurity diffusion layer. As a result, it is possible to manufacture with good reproducibility a semiconductor device having a transistor with a small amount of current loss and improved hot carrier resistance. The present invention is extremely suitable when applied to a BiCMOS-IC in which an analog circuit and a digital circuit are mixedly mounted on the same semiconductor substrate.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device 100.

FIG. 2 is an enlarged cross-sectional view showing a configuration example of Hv-NMOS 10.

3A to 3C are process diagrams showing a manufacturing method (1) of the semiconductor device 100.

4A to 4C are process diagrams showing a manufacturing method (No. 2) of the semiconductor device 100.

5A to 5C are process diagrams showing a manufacturing method (3) of the semiconductor device 100.

6A to 6C are process diagrams showing a manufacturing method (4) of the semiconductor device 100.

7A to 7C are process diagrams showing a manufacturing method (5) of the semiconductor device 100.

FIG. 8 is a cross-sectional view showing a configuration example of a first semiconductor device 80 according to a conventional example.

9A to 9C are a manufacturing method (1) of a semiconductor device 80.
FIG.

10A to 10C are process diagrams showing a manufacturing method (No. 2) of the semiconductor device 80.

11A and 11B are process diagrams showing a manufacturing method (3) of the semiconductor device 80.

FIG. 12 is a cross-sectional view showing a configuration example of a second semiconductor device 90 according to a conventional example.

13A to 13C are process diagrams showing a manufacturing method (1) of the semiconductor device 90.

14A and 14B are process drawings showing the method of manufacturing the semiconductor device 90 (No. 2).

[Explanation of symbols]

1 ... Semiconductor substrate, 10 ... Hv-NMOS, 12 ...
Gate electrodes, 14A, 14B ... First electric field relaxation layer,
15A, 15B ... Second electric field relaxation layer, 18 ... Source region, 19 ... Drain region, 20 ... Dep-NM
OS, 30 ... L-Vth-NMOS, 40 ... NMOS, 50 ...
・ PMOS

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/8238 H01L 21/265 F 21/8249 21/90 C 27/06 21/76 J 27/08 331 27/06 321A 27/092 29/62 G 29/43 29/78 F term (reference) 4M104 AA01 BB01 BB30 BB40 CC01 CC05 DD19 DD26 DD43 FF14 FF18 GG09 GG10 GG14 5F032 AA13 AB03 CA01 CA03 CA17 CA18 CA20 CA24 CA25 DA02 DA12 DA43 DA53 5F033 HH04 HH09 JJ19 JJ33 KK01 LL04 MM07 NN07 PP06 QQ31 QQ37 QQ58 QQ65 RR15 5F048 AA05 AA09 AC01 AC03 AC05 BA02 BA12 BB06 BB08 BF08 BF08 BB12 AB16 AB16 AB16 AB05 AB06 AB16 AB05 AB06 AB16 AB06 AB16 AB05 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB06 AB16 AB16 BG02 BG08 BG12 BG28 BG38 BH13 BH15 BH49 BJ10 BJ11 BJ17 BJ27 BK02 BK05 BK13 BK21 BK26 BK29 BK30 BK39 CA03 CB01 CB08 CC07 CC20 CD02

Claims (4)

[Claims] 1. A gate electrode provided on a semiconductor layer of one conductivity type defined by an insulating film for element isolation with an insulating film interposed, and a pair of gate electrodes provided on both sides of the gate electrode in the semiconductor layer. An impurity diffusion layer of opposite conductivity type is provided, and at least one of the impurity diffusion layers is provided at a position from a position overlapping with the gate electrode to the insulating film for element isolation, and impurity diffusion is performed by multiple ion implantation. The semiconductor device is characterized in that the concentration is adjusted, and the impurity diffusion concentration is the lowest under the gate electrode, and the impurity diffusion concentration is densely distributed with increasing distance from the gate electrode. 2. A step of isolating an element of a semiconductor layer of one conductivity type by an insulating film to define a transistor formation region, and opposing at least one of the semiconductor layers on both sides of a region where a gate electrode is formed in the transistor formation region. Implanting conductivity type impurity ions to form an impurity diffusion layer, and multiply implanting impurity ions of opposite conductivity type into the impurity diffusion layer to adjust the impurity diffusion concentration, and at least the impurity diffusion layer And a step of forming a gate electrode on the semiconductor layer in a region including an end portion with an insulating film interposed therebetween, a method of manufacturing a semiconductor device. 3. When the impurity ions of the opposite conductivity type are multiply implanted, in the impurity diffusion layer, the impurity diffusion concentration on the region side where the gate electrode is formed is the lowest, and the impurity diffusion layer is separated from the region where the gate electrode is formed. The method of manufacturing a semiconductor device according to claim 2, wherein the impurity diffusion concentration is increased. 4. When the transistor is a first transistor, a semiconductor layer of one conductivity type is isolated by an insulating film to form a first transistor.
Defining a transistor forming region, a second transistor forming region, and a third transistor forming region, and forming a gate electrode in the first transistor forming region on at least one of both sides of the opposite conductivity type. While implanting impurity ions to form an impurity diffusion layer,
Implanting the impurity ions into the second transistor formation region to form an impurity diffusion layer for adjusting a threshold voltage, and multiplying impurities of opposite conductivity type in the impurity diffusion layer formed in the first transistor formation region. A step of implanting ions to adjust the impurity diffusion concentration and implanting the impurity ions into the third transistor formation region to form an impurity diffusion layer for adjusting the threshold voltage. 2. The method for manufacturing a semiconductor device according to 2.