TW501256B - Method of manufacturing a copper metal wiring in a semiconductor device - Google Patents

Method of manufacturing a copper metal wiring in a semiconductor device Download PDF

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Publication number
TW501256B
TW501256B TW090114671A TW90114671A TW501256B TW 501256 B TW501256 B TW 501256B TW 090114671 A TW090114671 A TW 090114671A TW 90114671 A TW90114671 A TW 90114671A TW 501256 B TW501256 B TW 501256B
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Taiwan
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copper
manufacturing
item
semiconductor device
patent application
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TW090114671A
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English (en)
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Sung-Gyu Pyo
Si-Bum Kim
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Hynix Semiconductor Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

501256 A7 五、發明說明(,) 發明之技術領域: 本發明係有關於一種在半導體元件中製造鋼導線之方 法。更特別地是,本發明係有關於一種在半導體元件中製造 銅金屬導線的方法,該方法在藉由化學辅助化學氣相沈積 (CECVD)法沈積銅而形成金屬導線時,可增加化學輔助劑 的吸附位置。 發明之背景: 由於下一世代之半導體元件性能之增加,所以接觸的尺 寸將被降低且縱橫比亦將增加。因此’當一金屬導線形成時, 良好的接觸填充性質與階梯覆蓋為所需。 目前在半導體元件中之金屬導線製造所使用的方法為 在一個鈦薄膜沈積後,藉由物理氣相沈積(以下稱為PVD) 法及化學氣相沈積(CVD)法沈積鋁於其上;或者藉由ρν〇 法形成组或氮化钽薄膜作為防擴散膜,並藉由電鍍法沈積 銅。然而’在應用於下-世代之紐能的半導體元件時,目 前的方法為有問題的,因為鋁的電阻率較銅為高。在後面的 方法中’基於接觸尺寸的急遽降低及縱橫比的增加,銅的填 充性質為有限的。此外’作為銅之防擴散膜的氣化组薄膜必 須極薄,當相較於未施加防擴散膜的鋁時,其將增加電阻率。 因此’將銅導線應用於下-世代的半導體元件或者使用紹導 線及電鑛將引起諸多問題。為了解決這些問題,將化學氣相 沈積(CVD)法使用於銅導線沈積之方法的研究近來已漸受到 重視。然而’基於較低的沈積速率,該綠在體填充(恤 I----.------Aw --------^--------I (請先閱讀t面之主意事項再填寫本頁) 本紙張尺度關家鮮(CNS)A4祕(21Q X 公釐) 501256 濟 部 智 慧 財 產 局 員 X 消 費 合 作 社 印 製 A7 五、發明說明(>〇 filling)方面為有限的。 产近來,藉由使用包含破(1)之镯媒的金屬有機物化學 氣相沈積(以下稱為M0CVD)法沈積銅薄膜的方法已被研 究。使用該觸媒的MOCVD法被稱為化學辅助化學氣相沈積 (以下=為CECVD)法。該化學辅助劑(亦即峨)取決於 紐阻障層的表面性質。此外,若該化學辅助劑在無種子沈 積的情況下被直接地沈積於該擴散組障層上,則該化學辅助 劑的吸附性質將被劣化。換句話說,在非晶質層或緻密薄膜 (並不提供該擴散阻障層可以一穩定的方法被沈積的位置) 的狀況下,該化學辅助劑將難以黏著於該擴散阻障層,而該 化學辅助效麟被降低。因此,具有鋼金屬導線 將會有被劣化的問題。 、 、 發明之簡要說明: 本發明揭示一種在半導體元件中製造銅導線之方法,其 所包含有之步驟為:形成一個介層絕緣膜於下層結構被形成 於其的一基板上;形成一個鑲嵌圖案;進行一道清洗製程,· 形成-個擴散阻障層於該鑲嵌圖案被形成於其的整個結構 上’·在該擴散阻障層被形成於其的整個結構上進行一道電浆 製程;使用該擴散阻障層(該電聚製程被進行於的化風 辅助劑進行化學預製程;沈積銅於該整個結構上,、以使^ 鑲嵌圖案可娜充;錢進行化學顧抛光餘,以使得= 鑲嵌圖案可被填充,因而僅在該舰圖案中形成銅金屬導線: —本紙張尺度朝巾關家鮮(cns)A4—雜(21〇 χ
Aw --------^--------- (請先閱讀r面之;^意事項再填寫本頁) 3 i A7 B7
經濟部智慧財產局員工消費合作社印製 501256 五、發明說明(π 圖式之簡要說明·· 前述之主要特性及其他特徵將被說明於 的說明,其中: 卜歹]配合附圖 第1Α圖至第1Ε圖為用於說明根據— 種在半導體元件中製造銅金屬導線的方法之剖面t例之- 圖號說明: 11- 基板 12- 介層絕緣膜 13_擴散阻障層 14-銅金屬導線 較佳實施例之詳細說明: 本發明揭露-種在半導體元件中製造銅導線之方 銅金屬導線藉由化學辅助化學氣相沈積CECVD _成時虽 f該化學辅助繼沈雜進行-道電雜程,錢得在擴散阻 障層表面上之化學辅助劑的黏著性增加,因而改良鋼的填充 性質,本發明簡由參相_較佳實_作-詳細地說明。 明參閱第1A圖所示,形成一個介層絕緣膜於下層 結構被形成於其的-基板n上。其次,藉由單鑲嵌或雙镶被 製程將該介層絕緣膜12刻劃,而形成包含有一個接觸a與 一個溝渠B的一個鑲喪圖案。其次,進行一道清洗製程。此 時’該介層絕緣膜12係藉由沈積具有低介電常數的絕緣材料 而被形成。當該底層為諸如鎢、鋁及適當的類似金屬等金屬 本紙張尺度適用中國國家標準(CNS)A4規格(21“ 297公爱)
A7
501256 五、發明說明( 層時,該清洗製程係使用賴電漿進行;而當該底層為銅製 的金屬層時,則使用活性清洗法進行。 、如第1B圖所示,在形成一個擴散阻障層13於該鑲嵌圖 案被形成於其的整個結構上之後,進行一道電漿製程。 該擴散阻障層13的形成係藉由以包含有離子化PVD、 CVD與M0CVD法之方法沈積氮化鈦,以離子化PVD法或 CVD法沈積紐或氮化钽,以CVD法沈積氮化鎢,以及以以① 或CVD法沈積包含有鈦鋁氮化物(ΉΑ1Ν)、鈦矽氮化物 (TiSiN)與麵石夕氮化物(TaSiN)的鈦複合物。 、在忒擴散阻障層13形成後所進行的該電漿製程係用於 增加後續製程所沈積之化學辅助劑的黏著效果,該電漿製程 右非稀電漿法則為電毁侧法。在使用該稀電漿法的狀況 中^係使用活性處理以增加該化學辅助劑的黏著位置。在使 用u玄電襞姓刻方法的狀況中,得為單或雙頻兹刻。 製 程y使用包含氫氣、氬氣航氣的―單—氣體,或使用氮氣 與氬氣的氣體混合物而被進行。該電漿製程可以一單一步驟 進行,或可以一至十個步驟之間的多步驟進行。 該電漿製程所使用的功率範圍為約50瓦至約1〇千瓦, 而該製程時間麵為約i秒至約1Q分鐘。再者,在使用諸如 氫氣、氮氣、氬氣魏氣之單-氣體進行電漿製程的狀況中, 各該單一氣體的流速範圍為約50標準立方公分每分鐘 —(seem)至約500Seem。在使用該混合氣體的狀況中,該氮 氣含量範_約95%,喊氣含量範_約5%至 約 95% 〇 (請先閱讀t面之;^音?事項再填寫本頁) 裝 --------訂---------· 濟 部 智 慧 財 產 局 員 X 消 費 合 作 社 印 製
發明說明(f) 同時’在使用該單步驟的狀況中,一單一氣體或該單一 氣體的混合物皆可被使用。在使用該多步驟製程的狀況中, 在該鼠氣之早一氣體或該混合物氣體先被使用後,該使用氫 氣的製程將被重複一至約十次。 在該電漿製程期間,在該包含有喷頭與基板的腔室中, 該基板的溫度被維持在約10°C至約350°c之間;該基板與噴 頭間#距離為約5 mm至約50 mm,以及該腔室中的壓力範 圍為約0·3托耳至約1〇托耳。 如第1C圖所示,在該擴散阻障層13上進行使用觸媒(亦 即化學辅助劑)的化學預製程,其係如上所述般進行該電漿 製程。此時,該化學辅助劑可使用含填液態複合物,其包含 有:Hhfac :氏0 (1 : 2)、Hhfac與TMVS、純碘、含碘氣體、 含碘水蒸氣,VII族元素(諸如氟、氯、溴、碘與鍔)的液 態與氣態,以及其複合物的液態與氣態。其中該製程時間範 圍為約1秒至約10分鐘。再者,該觸媒的製程溫度範圍為約 -20°C 至約 300°C。 如第1D圖所示,一個銅金屬導線14被形成於該整個 結構上,以使得該鑲嵌圖案可被填充。 該銅填充的形成可藉由使用所有使用hfac的銅預製 體,諸如(hfac)CuVTMOS系列、(hfac)CuDMB系列以及 (hfac)CuTMVS系列;並藉由使用一諸如直接液體注入(Du) 之液體傳輪系統(LDS)、一孔洞與一喷嘴被安裝於其上之所 有的該沈積設備的MOCVD法而被沈積。該銅預製體的流速 範圍為約0.1 seem至約5.0 seem。 501256
五、發明說明(& ) 再者’當該銅導線被形成時,係使用流速約 seem 至約700 sccm之包含氦氣、氫氣與氬氣的一傳輸氣體。反應 腔内的壓力麵為約〇5托耳至約5托耳,而該反應腔中的 溫度被維持在約與該沈積設備相同,且該噴嘴的溫度被控制 在定值。 此外,該鋼沈積的溫度範圍為約50。〇至約3〇〇°c之間, 而該反應腔中之該喷頭與晶座間的距離被維持在約5 mm至 約50 mm之間。 在銅以上述的方法被填充後,在約室溫至約450°C的氫 氣還原氣氛中進行約一分鐘至約三小時的熱製程,以便改變 晶粒組織的形狀。此時的氫氣還原氣氛可使用氫氣,或者包 含約〇至約95%氬氣或氮氣混入氫氣中的氫氣混合物。 如第1E圖所示,進行化學機械拋光(CMP)製程,以 使得該銅金屬導線14被維持在該鑲嵌圖案中,因而將該介層 絕緣膜13表面暴露出。再進行一次清洗製程。 綜上所述,本發明之結構特徵及各實施例皆已詳細揭 示’充分顯示出本發明案在目的及功效上均深富實施之進步 性’極具產業之利用價值,且為目前市面上前所未見之運用, 依專利法之精神所述,本發明寒完全符合發明射#要件。 | 唯以上所述者,僅為本發明之較佳實施例而已,當不能 量 以之限定本發明所實施之範圍。即大凡依本發明申請專利範 | 圍所作之均等變化與修飾,皆應仍屬於本發明專利涵蓋之範 | 圍内’謹請貴審查委員明鑑,並祈惠准,是所至禱。 社 印 製 Lr___7 本'私队没欄τ國國家標準(CNS)A^••⑵ο X挪公)-—-—
裝---- tr---------争 (請先閱讀r面之生咅?事項再填寫本頁)

Claims (1)

  1. 501256 六 Λ 8 Βδ CS ___ D8 申請專利範圍 種於半導體元件巾製造鋼導線b法,包含有下列步 驟: ’ 形成一個介層絕緣膜於下層結構被形成於其的一 上; 、土假 形成一個鑲嵌圖案; 進行一道清洗製程; 形成-個讎啡胁魏嵌_娜餘其的整個 結構上; 在該擴散阻障層被形成於其的整個結構上進行一道電 裝製程, 使用該擴散阻障層(該電漿製程被進行於其)的化學 辅助劑進行化學預製程; 沈積銅於該整個賴上,峨魏職圖案可被填 充;以及 〃 進行化學機麵光製程,以使龍鑲嵌圖案可被填 充,因而僅在該鑲嵌圖案中形成銅金屬導線。 、 2. 如申請專利細”項所述之於半導體元件中製造銅導線 之方法’其中該下層結構包含由鎢與鋁组成之金屬層的一 底層,以及該清洗製程包含使用射頻電漿。 3. 如申讀專利範圍第i項所述之於半導體元件中製造銅導線 之方法’其中該下層結構包含由鋼級成之一底層,以及該 清洗製程包含活性清洗法。 4. 如申請專利範圍帛!項所述之於半導體元件中製造銅導線 (請先間讀背面之注意事項再填¾本頁) 、1T 經濟部智慧財4AP、工消費合作社印製 本紙張足度適用中國國家標準(CNS ) A4規格(210X297公嫠)
    I利範圍 經濟部智慧財4局Μ工消費合作社印製 Λ8 B8 CS D8 之方法,其中形成該擴散阻障層的該步驟包含有: 以由離子化物理氣相沈積(PVD)、化學氣相沈積 (CVD)與金屬有機物化學氣相沈積(MOCVD)法組成 的族群中所選擇的方法沈積氮化鈦; 以離子化PVD法或CVD法沈積鈕或氮化鈕; 以CVD法沈積氮化鶴,以及 以PVD或CVD法沈積由鈦鋁氮化物(TiAIN)、鈦 石夕氮化物(TiSiN)與鈕砍氮化物(TaSiN)所組成的族群 中選擇的複合物。 5·如申請專利範圍第1項所述之於半導體元件中製造銅導線 之方法,其中該進行電漿製程的步驟係使用稀電漿法則為 電漿/钱刻法。 6·如申凊專利範圍第1項所述之於半導體元件中製造銅導線 ^方法,其中該進行電漿製程的步驟係使用由氫氣、氬 氣氮氣與氦氣所組成的族群中選擇的的一單一氣體。 7·如申請專利範圍帛㈣所述之於半導體元件中製造銅導線 之方法,其中該進行電漿製程的步驟包含將該單一氣體以 約50 seem至約500 seem流速進行傳輸。 8. 如申請專利範圍第[項所述之於半導體元件中製造銅導線 ^方法’其巾麵行電賴程的步驟係仙包含氫氣斑氬 氣的氣體混合物。 9. =請專利範_項所述之於半導體树中製造銅導線 之方法’其中該氣體混合物包含有約桃至約95%的氮氣 从及約5%至約95%的氬氣。 (請先間讀背面之注意事項再填寫本頁)
    申請專利範 圍 經濟部t慧时4局員工消費合作社印製 AS B8 C8 D8 •凊專利範圍第1項所述之於半導體元件中製造銅導線 =方法,其中該進行電漿製程的步:驟係以一個單一步驟, 或以包含有一至约十個步驟的多步驟而被進行。 11.如申凊專利範圍第!項所述之於半導體元件中製造銅導線 ^方法’其中該進行電賴程的轉包含有使用範圍為約 5〇瓦至約10千瓦的功率供給,以及約1秒至約10分鐘的 製程時間。 如申明專利$|圍第1項所述之於半導體元件巾製造銅導線 之方法,其中該電漿製程係以一個單一步驟進行,並使用 氣體混合物。 13.如申請專利範圍第〗項所述之於半導體元件中製造銅導線 =方法,其中該進行電漿製程的步驟係以多步驟而被進 行’以及在使用氬氣之單_•氣體或氣體混合物的—第一步 驟之後’ 1¾在後續步驟中使用氫氣的製程將被重複約一至 約十次。 I4·如申凊專利範圍第i項所述之於轉體元件中製造銅導線 之方法’其中該電漿製程係於包含有一個喷頭的腔室令進 行,以及該電漿製程包含有: 將該基板的溫度維持在约1〇〇C至約35〇〇c之間丨 將該基板與噴頭間的距離維持在約5 mm至約50 _ 之間;以及 將容納該基板之腔室中的壓力維持在約03托耳至約 10托耳之間。 / 15.如申請專利範圍第!項所述之於半導體元件中製造鋼導線 本紙張尺度適用ΪΓ國國家標準(CNS) A4規格( (請先閲讀背而之注意事項再填寫本頁)
    S法,其中該化學辅助劑包含由含破液態複合物, 經濟部智慧时4-P?員工消費合作社印製 一、條體、-成=群有少—種仰族元素的任何複合物所組 專利細第1項所述之於半導體元件中製造銅導線 、,射該化學預製錢行的_範 1〇分鐘。 J 如申明專利範圍第1項所述之於半導體元件中製造銅導線 〇方法’其中該化學預製程係於溫度範__2叱至約300 c之間進行。 18·如申請專利範圍第i項所述之於半導體元件中製造銅導線 -方去,其中該銅沈積步驟包含使用具有虹如的銅預製 ^^tMhfac#^(hfac)CuVTMOS ^ (hfac)CuDMB 系列以及(hfac)CuTMVS系列組成的族群中選擇。 9·如申凊專利範圍帛丨項所述之於轉體元件中製造銅導線 之方法,其中該銅沈積步驟包含使用流速範圍為約0.1 seem至約5·〇 sccm的銅預製體。 20·如申請專利翻第1項所述之於半導體元件中製造銅導線 之方法,其中該銅沈積步驟包含流速範圍約100 seem至約 7〇〇 seem之由氦氣、氫氣與氬氣組成的族群中所選擇的傳 輸氣體。 21·如申凊專利範圍第1項所述之於半導體元件中製造銅導線 之方法,其中該銅沈積步驟包含將反應腔内的壓力範圍維 持在約0·5粍耳至約5托耳。
    甲諳專利範圍 8 8 8 8 Λ BCD 22·如申晴專利範圍第i項所述之於半導體元件中製造銅導線 之方法’其巾該銅沈積步驟包含齡統件的溫 5〇°C至約30(TC之間。 23·如申請專利範圍第1項所述之於半導體元件中製造銅導線 之方法’其巾該銅沈積步驟包含將飯應财之該喷頭與 曰曰座間的距離維持在約5mm至约5〇mm之間。 24·如申請專利範圍第!項所述之於半導體元件中製造銅導線 之方法’其中該銅沈積步驟包含在約室溫至約4耽溫产 範圍的氫氣還原氣氛中進行約—分鐘至約三小時的熱& 程0 25.如申請專利範圍第24項所述之於半導體元件中製造銅導 線之方法’其中該銅沈積步驟包含使用氫氣,或者包含氯 氣、氬氣與氮氣的氣體混合物,或者包含氫氣與氮氣的氣 體混合物。 ' 請先閱讀背面之注意事項再填寫本頁) 、1T f 經濟部智慧时44Μ工消費合作社印製
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