TW201120955A - Method of providing stable and adhesive interface between fluorine-based low-k material and metal barrier layer - Google Patents

Method of providing stable and adhesive interface between fluorine-based low-k material and metal barrier layer Download PDF

Info

Publication number
TW201120955A
TW201120955A TW099134060A TW99134060A TW201120955A TW 201120955 A TW201120955 A TW 201120955A TW 099134060 A TW099134060 A TW 099134060A TW 99134060 A TW99134060 A TW 99134060A TW 201120955 A TW201120955 A TW 201120955A
Authority
TW
Taiwan
Prior art keywords
fluorine
layer
based dielectric
metal
dielectric layer
Prior art date
Application number
TW099134060A
Other languages
Chinese (zh)
Inventor
Lee Chen
jian-ping Zhao
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/574,101 external-priority patent/US20110081500A1/en
Priority claimed from US12/574,117 external-priority patent/US20110081503A1/en
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW201120955A publication Critical patent/TW201120955A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners

Abstract

A method of integrating a fluorine-based dielectric with a metallization scheme is described. The method includes forming a fluorine-based dielectric layer on a substrate, forming a metal-containing layer on the substrate, and adding a buffer layer or modifying a composition of the fluorine-based dielectric layer proximate an interface between the fluorine-based dielectric layer and the metal-containing layer.

Description

201120955 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於氟基低介電常數(低k)材料之界面之製 備方法，尤有關於一種於半導體與電子裝置中將氟基低k材料與" 金屬内連線結合之方法。 [先前技術】 當極大型積體(ULSI)電路之維度持續地縮小，由寄生電容所 引起之互連延遲逐漸大於閘延遲，而因此互連延遲支配了具有通 用Al/Si〇2金屬化機構之裝置性能。關於使用較低電阻金屬⑽如， Cu)與較低電容層間介電(ILD)材料之重要的 實施幾十年。賴低k(低介電常數)介紐料不僅^低線間H (lme-to-lme capacitance)，亦使串音雜訊(cr〇ss4alkn〇ise)最小化並 降低功率消耗。吾人已仔細地研究大範圍之低k材料，包含氟化 Si〇2有機t合物或混合聚合物、有機$酸鹽玻璃、毫微多孔性 f石、及非晶系氟碳。此外，吾人已研究相關特性，如 …與，與化學品抗性、黏著力、及間隙填充能力。 ΐ 具2似7介電常叙π聚合物或 =非喊)之作業已顯不其對層間介電 ^氣ΐίΪ料之電、熱、糊二 化物鈦令鑛其氮 題係化減狀主要問 ?、于知肩—個關鍵性的角色。發明者明 201120955 白f2一非常易反應且具腐I虫性的元素 ，而因此，他們推測F原 其中F原子最初存在於介於金屬阻障層與氟基 料主或在涉及裝置高溫處理期間由氟基低让材 ‘之聚積於界面。因此，介於金屬阻障層與氟基低让材 二:S變成非常低強度腐_，且因此，可能表現不 立每當將金屬阻障層沈積於這些氟基低k材料之下或之上，阻 障層之金屬元素可㈣地絲基低k材料巾自由且可之 子^應⑽成金屬氟化物，其通f具#高蒸氣壓及對_qh官能基 •^兩敏感度。此界面的化學反應製程大大地_界職度，致^ ，重=©黏f性問題，而終究由於水分子的渗透使仏明顯增 加。再者，金屬層作為氟原子匯點(s址），而因此，可 層之—棘度。此擴散製程會降低於氟基低k 材枓中F對C原子之_ ’且更造成k值增加及變得較不穩定。 【發明内容】 本發明係關於帛於氟基低介電數(低k)材料之界面之製備方 本發明侧於種於半導體與電子I置中將低k 材料與金屬内連線結合之方法。 根據-實施例，敘述-種將氟基介電質與金屬化機構結合之 方法。此方法包含於基板上形成氟基介電層，於此基板上形成含 金屬層，及修改絲介電層與含金屬賴之界_近之該氣基介 電層之組成。 根據另一實施例’敘述-用以製備氟基介電質金屬化麵之 平臺。此平臺包含一用以於基板上形成氟基介電層之第一成膜系 統、-用贈此基板上形成含金屬層之第二成齡統、_用以修 改氟基介電層與含金屬層間之界面附近之該氟基介電層之組成之 處理系士及-連？到第-細祕、第m统、及處理系 統之輸送糸統，輸送系統並用來將基板在其間輸送。 根據另-實施例，敘述-種將氟基介^質與金屬化機構結合 201120955 之方J：。此方法包含於基板上形成絲介電層，於此 ί佘K此基i!層與含金屬層之間之界“成緩衝 ? ^此緩衝層t含一含碳層，此含碳層係選自於 面體非晶碳㈣)、非晶碳化仆氫化非晶碳(a_C:H)、 之方^ _氟基介電質與金屬化機構結合 t方法此方去包含於基板上形成氣基介電層，於 =ls 含金屬層之間之界面形：緩衝層 金===_，竭軸㈣Ν,、或抓合 之方^據例’敘述—種將氟基介電f與金屬化機構結合 成ΐίμ i含於基板上形成化系介電層，於此基板上形 =層層之間之界面形成金 組成之族群3==-=^ 何二或多個組合。 ⑷口孟Nl合金、Cu合金、或其任 ，敘述—用以製備氟基介電質金屬化機構之 絲,ΙΪ平$包含—用以於基板上形成氟基介電層之第-成膜系 氣美二此基板上形成含金屬層之第二成膜系統、一用以於 接至^c含金屬層之間沈積緩衝層之第三成膜系統、及一連 送系茲板統、及處理系統之輸送系統，輸 【貧施方式】 制備2個實施例中揭露—種關於在氟基介電層與含金屬層之間 之方法與系統。然而’習知相關技藝者將明白可在益-下定巧’或以其他替代及/或額外的方法、材料、或元件 結二订二:,’施,卜在其赌況下，並*詳細地齡或敘述熟知 ;:斗、或刼作，以避免混淆本發明多個實施例之實施樣態。 201120955 同樣地，為了說明之目的，五 造以提供本發明完整的理解。^ j數目，料、與構 明。再者’吾人應理解衫悔穌 _ :特$細節下實行本發 示而未必依比例繪製。 圖不中之貫施例係說明性表 參考遍及本說明書之「―個眚祐 化意味著_本實施例所描述特實關」或其變 徵係包含於至少-個本發明特=結=料、或特 中結構、物質、或：=== 敌述本㈣本質之―般贿，包含於 意指口於一詞通常 構，尤其半導體或其他電子;置，或裝置結 在rir構上錢蓋底部基二導體 Ϊ 板並非限制於任何特定底部結構、® -結構，= 但此僅為說_意而細^：41^參相定_之基板， 同或示且彳 4φ m ρ» y- >i=r . 及圖2根據一貫施例言兄明— 該^Ϊ電層120可包含合金“UMin=二)氟 而5 U介電層⑽可包含一氟化非晶碳介電材料。卜半歹 亂土，丨電層120可包含低介電常數(即，低幻或超低介電常數 6 201120955 (即，超低k)介電層’其具有低於以〇2介電常數之標稱(n〇minal) 介電常數值，其中Si〇2介電常數約為4(例如，對於熱二氧化矽介 電常數範圍可從3.8至3.9)。更具體地，薄膜可具有低於3.7之介 電常數，或範圍從1.6至3.7之介電常數。再者，氟基介電層120 可為非多孔性或多孔性。 产可使用氣相沈積技術或塗旋式技術形成氟基介電層120;其中 氣相沈積技術如化學氣相沈積(CVD)、電漿促進cvd(PECVD)、 原子層沈積(ALD)、電聚促進ALD(PEALD)、物理氧相沈穑 (P腎或離子化PVD(iPVD);而旋塗式技)術如由^=ectr〇n Limited(TEL)於市面上所販售之cleanTrackACT 8 s〇D(塗旋式介 電質）、ACT I2 SOD、及LITHIUS塗佈系統所提供者。Clean Track ACT 8(200 mm)、ACT 12(300 mm)、及 LITHIUS(300 mm)塗佈系 ，提供可用於SOD材料之塗佈、烘烤、及硬化(cure)工具。軌道 系統可用來處理100 mm、200 mm、300 mm、與更大之基板尺寸。 其他用以於基板上形成薄膜之系統與方法為習知塗旋與氣相沈 兩技術者所熟知。 、 於22〇中，於基板110上形成含金屬層160。舉例而言，如g 1C所示，含金屬層16〇係形成於氟基介電層12〇上。於二個範会 二js 3 3層可包含金屬層、金屬晶種層、金屬潤歷層、金屬阻 、金屬黏著層’或其任何二或多傭組合。於另一201120955 VI. Description of the Invention: [Technical Field] The present invention relates to a method for preparing an interface of a fluorine-based low dielectric constant (low-k) material, and more particularly to a fluorine-based one in a semiconductor and an electronic device. A method of combining low-k materials with " metal interconnects. [Prior Art] When the dimension of the Maximal Integral (ULSI) circuit is continuously reduced, the interconnection delay caused by the parasitic capacitance is gradually larger than the gate delay, and thus the interconnection delay dominates the metallization mechanism having the general Al/Si〇2 Device performance. Important implementations of using lower resistance metal (10) such as Cu) and lower capacitance interlayer dielectric (ILD) materials for decades. Lai low k (low dielectric constant) media not only reduces the H (lme-to-lme capacitance), but also minimizes crosstalk noise (cr〇ss4alkn〇ise) and reduces power consumption. We have carefully studied a wide range of low-k materials, including fluorinated Si〇2 organic t- or mixed polymers, organic acid-silicate glasses, nanoporous f-stones, and amorphous fluorocarbons. In addition, we have studied related properties such as ... and chemical resistance, adhesion, and gap filling ability. The work of ΐ 2 like 7 dielectric π polymer or = non-screaming has not been shown to be the main reason for the dielectric, heat, and paste of the titanium. Ask?, knowing the shoulders - a key role. The inventors clarify that 201120955 white f2 is a very reactive and rot-inhibited element, and therefore, they speculate that F atoms in which F atoms originally existed between the metal barrier layer and the fluorine-based material master or during high-temperature processing involving the device The fluorine-based low yield material accumulates at the interface. Therefore, between the metal barrier layer and the fluorine-based barrier material: S becomes a very low-strength rot, and therefore, may not stand up whenever a metal barrier layer is deposited under these fluorine-based low-k materials or The metal element of the barrier layer can be (4) the ground-based low-k material towel is free and can be (10) into a metal fluoride, which has a high vapor pressure of # and a sensitivity of _qh functional group. The chemical reaction process of this interface is greatly _ boundary degree, causing ^, heavy = © sticky f-problem, and after all, the enthalpy is obviously increased due to the penetration of water molecules. Furthermore, the metal layer serves as a sinking point (s site) of the fluorine atom, and therefore, the layer can be a spine. This diffusion process is reduced by the _' of F to C atoms in the fluorine-based low-k material, and the k value is increased and becomes less stable. SUMMARY OF THE INVENTION The present invention relates to the preparation of an interface between a fluorine-based low dielectric (low-k) material. The present invention is directed to a method of combining a low-k material with a metal interconnect in a semiconductor and an electron I. . According to an embodiment, a method of combining a fluorine-based dielectric with a metallization mechanism is described. The method comprises forming a fluorine-based dielectric layer on the substrate, forming a metal-containing layer on the substrate, and modifying a composition of the gas-based dielectric layer and the metal-based dielectric layer. A platform for preparing a fluorine-based dielectric metallization surface is described in accordance with another embodiment. The platform comprises a first film forming system for forming a fluorine-based dielectric layer on the substrate, and a second adult system for forming a metal-containing layer on the substrate, for modifying the fluorine-based dielectric layer and Processing of the composition of the fluorine-based dielectric layer near the interface between the metal layers. To the fine-grained, m-th, and processing systems of the transport system, the transport system is used to transport the substrate therebetween. According to another embodiment, it is described that the fluorine-based medium is combined with the metallization mechanism. The method comprises forming a silk dielectric layer on the substrate, wherein the boundary between the base layer and the metal-containing layer is “buffered”. The buffer layer t comprises a carbon-containing layer, and the carbon-containing layer Selected from the surface amorphous carbon (4), amorphous carbonized hydrogenated amorphous carbon (a_C: H), the square ^ _ fluorine-based dielectric combined with the metallization mechanism t method to be included in the substrate to form gas The base dielectric layer, the interface shape between the metal layers of =ls: buffer layer gold ===_, the exhaust axis (four) Ν, or the square of the grasping ^ Instances - description of the fluorine-based dielectric f and metal The chemical mechanism is combined with ΐμμμ to form a chemical dielectric layer on the substrate, and the interface between the layers on the substrate forms a group of gold composition 3==-=^ or two or more combinations. Nl alloy, Cu alloy, or any of them, for preparing a filament of a fluorine-based dielectric metallization mechanism, comprising: a first-film-forming system for forming a fluorine-based dielectric layer on a substrate a second film-forming system comprising a metal layer on the substrate, a third film-forming system for depositing a buffer layer between the metal-containing layers, and a continuous connection system and processing Conveying system, transmission [poor application method] Preparation of two examples disclosed in the method and system between the fluorine-based dielectric layer and the metal-containing layer. However, the skilled artisan will understand that it can be beneficial - the next set of 'or other alternatives and / or additional methods, materials, or components to set two two:, 'Shi, Bu in their gambling, and * detailed age or narrative is well known;: bucket, or 刼In order to avoid obscuring the implementation of various embodiments of the present invention, 201120955 Similarly, for the purpose of explanation, five are provided to provide a complete understanding of the present invention. The number, material, and composition of the invention.衣衣悔如_: The special implementation of this presentation is not necessarily drawn to scale. The example of the diagram is a description of the stipulations throughout the specification. "实关" or its variants are included in at least one of the inventions, or the special structure, substance, or: === the essence of the enemy (4), which is included in the meaning of The word is usually constructed, especially semiconductor or other electronic; set, or device knotted on the rir structure The base-based two-conductor raft is not limited to any particular bottom structure, о-structure, = but this is only for the meaning of _ meaning and fine ^: 41 ^ 相 phase _ the substrate, the same or show 彳 4φ m ρ» y- >i=r . and Figure 2, according to a consistent example, the electrical layer 120 may comprise an alloy "UMin = di" fluorine and the 5 U dielectric layer (10) may comprise a fluorinated amorphous carbon dielectric material. The germanium layer 120 may comprise a low dielectric constant (ie, a low or ultra low dielectric constant 6 201120955 (ie, ultra low k) dielectric layer 'which has a lower dielectric than 〇 2 The nominal value of the constant (n〇minal), where Si〇2 has a dielectric constant of about 4 (for example, the dielectric constant for thermal cerium oxide can range from 3.8 to 3.9). More specifically, the film may have a dielectric constant of less than 3.7 or a dielectric constant ranging from 1.6 to 3.7. Furthermore, the fluorine-based dielectric layer 120 can be non-porous or porous. The vapor-based deposition technique or the spin-on technique can be used to form the fluorine-based dielectric layer 120; among them, vapor deposition techniques such as chemical vapor deposition (CVD), plasma-promoted cvd (PECVD), atomic layer deposition (ALD), and electricity Poly-promoting ALD (PEALD), physical oxygen phase deposition (P-kidney or ionized PVD (iPVD); and spin-on technique) such as cleanTrackACT 8 sold by ^=ectr〇n Limited (TEL) s〇D (coated spin dielectric), ACT I2 SOD, and LITHIUS coating systems are available. Clean Track ACT 8 (200 mm), ACT 12 (300 mm), and LITHIUS (300 mm) coating systems provide coating, baking, and cure tools for SOD materials. The track system can be used to handle substrate sizes of 100 mm, 200 mm, 300 mm, and larger. Other systems and methods for forming thin films on substrates are well known to those skilled in the art of spin coating and vapor deposition. A metal-containing layer 160 is formed on the substrate 110 in 22 Å. For example, as shown by g 1C, the metal-containing layer 16 is formed on the fluorine-based dielectric layer 12A. The two Js 3 3 layers may comprise a metal layer, a metal seed layer, a metal layer, a metal barrier, a metal adhesion layer or any combination thereof. On another

St 包含金屬、金屬合金、金屬氧化物、金屬氮化物、 人屬见乳化物、金屬碳化物、金屬魏^、或其任何二或多個組 牛例而δ，含金屬層160可包含含銅(Cu)物質、含晳 質、含维)物質 '含糊層、含銖(Re;層 二含:=,含華)層、或含雖§)層、或上： 山口此夕卜舉例而言’含金屬層160可包含這些金屬盘氧 '氮 ΐ，含二ίΐΐ:二或多個組合之化合物。再者，舉例而 j層160可包含Cu、Cu合金、八卜A1合金、此、Ru、 g、或其任何二或多個組合。又再者，舉例而言，含金 201120955 屬層160可包含W、Ti、Ta、其氧化物、其氮化物、其氮氧化物、 其碳化物、其碎化物、或其任何二或多個組合。 可使用氣相沈積技術形成含金屬層，如化學氣相沈、 電漿促進CVDiPECVD)、原子層沈積(ALD)、電漿促進八 ALD(PEALD)、物理氣相沈積(PVD)、或離子化pv〇(ip 任何二或多個組合。 於230中’於氟基介電層12〇與含金屬層·之間製備界面 140。然後’可於含金屬層16〇上形成介電層18〇，且可於芦 180，金屬層160之間形成第二界面17〇。介電層18〇之材料1 ，可與基介電層12G相同’或介電層⑽之材料組成可盘氣基 ^電層12=同。此外’第二界面17〇之材料組成可與界面14〇 ，同’或第二界面170之材料組成可與界面14〇不同。又此外， 第二界面170可以與界面140相同之方式製備，絲二界面 可以與界面140不同之方式製備。再者，界面14 17〇可為氟(F)擴散阻障層。 飞弟一界面 开所顯f ’可在形成氟基介電層12G期間及/或在 I ίί2 及在形成含金屬層160之前製備界_ Ϊ S ) °或者及/或同時’如圖1D所顯示，可在形成含金 期在形成介電層18G之前及/或在形成介電層180 期間製備界面(例如，第二界面17〇^ 包人，於氣基介電層與含金屬狀間製備一界面 二1改?基”电層與含金屬層間之界面附近之氣基介電層之組 X二二改5齡電層之城可包含增加於界面附近、於界面、或 肉夕上缚(C)相對濃度’及/或減少於界面附近、於界面、口戈界面 内之氟(F)相對濃度。 A界面 ，據^-實施例’於氟基介電層與含金屬層之間製備 修故？ ΐ巧轉電漿浸沒之高能的帶電粒子照職基介電層， " ii與含金屬層間之界面附近之氟基介電層之組成， 帶電粒子可包含電子、離子、或氣體_離子、或盆 了一或夕個組合。高能的帶電粒子之通量(flux)可經準直或未經 201120955 準直。舉例而言，高能的帶 或氣體團蔡離子源、或其電子源、離子源、 蔟離子束源、或其任何二或多:離子束源、或氣體團 以非電之高能的帶·子昭射氣 r處理嶋“ 界面、將材料“γ 材料生成於氟基介電層表面以形成 ::將材，積於絲介電層表面以形St comprises a metal, a metal alloy, a metal oxide, a metal nitride, an emulsifier, a metal carbide, a metal, or any two or more groups thereof, and the metal-containing layer 160 may comprise copper. (Cu) Substance, substance containing smear, containing dimension, smeared layer, layer containing yttrium (Re; layer 2 containing: =, containing hua), or layer containing §), or above: Yamaguchi The metal-containing layer 160 may comprise these metal disk oxygen 'azepines, containing two compounds: two or more combinations of compounds. Further, for example, the j layer 160 may comprise Cu, a Cu alloy, an octa A1 alloy, this, Ru, g, or any combination thereof. Still further, for example, the gold-containing 201120955 genus layer 160 can comprise W, Ti, Ta, its oxides, its nitrides, its nitrogen oxides, its carbides, its fragments, or any two or more thereof. combination. Vapor deposition techniques can be used to form metal-containing layers such as chemical vapor deposition, plasma enhanced CVDiPECVD, atomic layer deposition (ALD), plasma enhanced eight ALD (PEALD), physical vapor deposition (PVD), or ionization. Pv〇(ip any two or more combinations. The interface 140 is prepared between the fluorine-based dielectric layer 12 and the metal-containing layer in 230. Then, a dielectric layer 18 can be formed on the metal-containing layer 16〇. And forming a second interface 17〇 between the reed 180 and the metal layer 160. The material 1 of the dielectric layer 18 can be the same as the base dielectric layer 12G or the material of the dielectric layer (10) can be composed of a gas base ^ The second layer 170 may be different from the interface 14 〇. The material composition of the second interface 17 可 may be different from the interface 14 〇, the same or the second interface 170 may be different from the interface 14 。 In addition, the second interface 170 may be interface 140 In the same manner, the silk interface can be prepared differently from the interface 140. Further, the interface 14 17 can be a fluorine (F) diffusion barrier layer. The Feidi interface can be formed in the form of fluorine. During the electrical layer 12G and/or in the case of I ίί2 and before the formation of the metal-containing layer 160, the boundary _ Ϊ S ) ° or and / or simultaneously As shown in FIG. 1D, an interface may be prepared prior to formation of the dielectric layer 18G and/or during formation of the dielectric layer 180 during the formation of the gold-containing period (eg, the second interface 17 〇 包 包, in the gas-based dielectric layer The group of the gas-based dielectric layer near the interface between the electrical layer and the metal-containing layer prepared by the interface between the metal-containing and the metal-containing layers may be added to the vicinity of the interface at the interface. Or, on the eve of the meat (C) relative concentration 'and / or reduced in the vicinity of the interface, the relative concentration of fluorine (F) in the interface, mouth interface. A interface, according to ^-example 'in the fluorine-based dielectric layer The preparation of the repair with the metal-containing layer? The high-energy charged particle service-based dielectric layer immersed in the plasma immersion, " ii and the composition of the fluorine-based dielectric layer near the interface between the metal-containing layers, charged particles can be Contains electrons, ions, or gas-ions, or a combination of one or a combination of high-energy charged particles that can be collimated or collimated without 201120955. For example, high-energy bands or gas clusters Cai ion source, or its electron source, ion source, helium ion beam source, or any two or more thereof: ion beam The source or the gas group is treated with a non-electric high-energy band, a sub-epitope r, "the interface, the material "gamma material" is formed on the surface of the fluorine-based dielectric layer to form: the material, accumulated on the surface of the silk dielectric layer Shape

層表面以形成界面、或將材料 ⑽鼠H 面、或其任何二或多個組=入於鼠基Μ電層表面以形成界 如圖1C所示’當將含金屬層形成於氟基介 將含金屬層160形成魏基介電層⑽頂部^合 梵子照射介電層。於其中 ^电粒子可猎由鏡子解離或離子雜而形成富含c之表面。 j積金屬阻障層(如含金屬層)於氟基介電層上時，會於界面形成 金屬碳化物’而這些碳化物提供一非常穩定且具黏著性之界面層。 根據另一實施例，於氟基介電層與含金屬層之間製備一界 面，包含藉由調整用以形成氟基介電層之沈積製程，修 電層與含金觸間之界_近之氟基介電層之組成，氣」| 调整用以形成氟基介電層之沈積製程可包含調整一或多個下 列條件：（1)用以形成氟基介電層之電漿放電條件；（2)用以形成氟 基介電層之壓力；（3)CF自由棊密度；（4)CF2自由基密庋；（5)CF3 自由基密度；（6)成膜前導化合物之流量；（7)基板溫度；或⑻稀釋 氣體之流量；或(9)二或多個其組合、 成膜前導化合物可包含含CxFy前導化合物，其中X與y係大 於或等於一之整數。此外，稀釋氣體可與成膜前導化合物一起引 201120955 入。稀釋氣體可包含惰性氣體(如氬(Ar))或含氫氣體(如H2、或 NH3、或兩者）。 調整關於沈積製程之電漿放電條件可包含調整與支撐基板之 電極耦合之功率，或調整與未支撐基板之電極耦合之功率，或兩 者0 當將含金屬層沈積於氟基介電層頂部，如圖lc所示(例如， 於氟基;I電層120頂部形成含金屬層ι6〇)，或當將氟基介電層沈 積於含金屬層頂部，如圖1D所示(例如，將介電層18〇形成於含 金屬層160頂部）’適合調整沈積製程。舉例而言，若將氟基介電 層形成於含金制上，使用非電漿浸沒之高能的帶電粒子照射而 ，飾表面⑽成於界面具有富含c材料之界面係有織性而不可 4干的。 猎由改變氟基介電層沈積條件(如電漿放電條件），可執行一 5 夕個調整以分級界面並產生富含c之界面，該等調整令 (但不限於）：⑴增加柄合至支樓基板之電極及/或未支撐基板 力?、;1?曾厂加對於支撐基板之電極之_功率；⑽增加基未 (v)增加cf自由基密度；及域⑽減少cf2 自由基密度。因此，可降原子與金屬原子之間鍵結之 H ’且亦可降低於主體觀巾總F原子對c原子之比例。急 tit，推測“ &及/或H2稀釋成膜前導化合物(即，cxfx前起 結果不i 2據另見施例，於氟基介電層與含金屬層之間製備一界 基介=======修改氟 氣體NQ、_、Ν。2、或細:或多個組合- 電《(例如使用N2形鮮)處理氟基介f層可減 子，μ子結合於表社，其可改善黏著性。 根據另一貫施例，於氟基介電層與含金屬層之間製備一界 201120955 面’包含於氟基介電層與含金屬層間之界面沈積緩衝層。形 衝層可k供一與含金屬層穩疋且具黏著性之界面，且亦可對氟基 介電層提供強鍵結。較佳地，緩衝層不應大幅修改氟基介電層^ 根據另-實施例’於敦基介電層與含金屬層間之界面沈積 衝層包含沈積-含碳層，其係選自下列所組成之族群：四面體非 晶碳(ta-C)、非晶碳(a-C)、氫化非晶碳(a_c:H)、類鑽碳(DLC)、氮 化，晶碳(a-C:N)、氮化碳((¾)、非晶型氮化碳(a_CN)、氫化非晶 型氮化碳(a-CN:H)、或其任何二或多個組合。 可使用氣相沈積技術沈積緩衝層，如化學氣相沈積 漿促進CVD(PECVD)，原子層沈積(ALD)、電漿促進 ALD(PEALD)、物理氣相沈積(pvj))、離子化pvD(ipvD)、直 ^殿積(VAD)、或過濾式彻，或其任何二或多個組合。舉例而 =，當使職t以提高及/或促進緩衝層沈積，可使用下列方式形 蔣電漿.f谷式耦合電漿(CCP)、電感式麵合電漿财）、表面波電 7、輻射線槽孔天線(RLSA)電漿、或真空電弧電漿、或其任何二 於^土；丨电層與含金屬層之間含有下列物質之緩衝層：四面 J ’或稱作無晶鑽石）、或常見的非晶碳(a-C或a-C:H) =;頃石厌(DLC)、或氮化非晶碳(a_c:N)、或氮化碳(a-CN、七CN:H、 ’其可扮演此二不同物質層之間之化學緩衝層。缓衝層可 =反^’或甚雖隔含金觸之金屬元素減基介電層之F 原子之間的反應。因此，可於界面形成金屬碳化物。 ’舉例而言，目C_C鍵結(最好是Sp3混成)僅比C_F鍵結 尚值，含非晶碳之緩衝層不會大大地影響氟基介電層 舉例而吕’含氮化非晶碳(a-C:N)之緩衝層亦可作 可使用運用電聚之CVD(例如，藉由CCP、肌从等之 R χη氣電製氮化非晶碳層以沈積氮化非晶石炭 想的雜放電條件、基板溫度、功率、與壓力， 又付-早鍵而移除C=N與C=N鍵結。因為C-N鍵結具有 201120955 短之鍵長，發明者預期可形成較密集的緩衝層，其 inn子與含金屬層反應。在這種情況下，高度SP3鍵結之 去:2 t晶石反t於室溫下使用由金屬真空電弧電师慮過或 單—能讀能階之雜子所沈積。較低品質之非晶 反類ϋί，PVD或CVD法沈積，如寬離子束輔助沈積。 ㈣ίίί—貫施例，於氟基介電層與含金屬賴之界面沈積緩 沈積-金屬，該金屬係選自於下列所組成之族群：A1、 1、金、N1合金、Cu合金、或其任何二或多個組合。 將二上?:相沈積技術沈積緩衝層，如化學氣相沈積(CVD)、電 漿促進CVD(PECVD)、原子層沈積(ALD)、電驗進 ALD(PEALD)、物理氣相沈積(p、或離子化p(奶① i ϊΐί或合。舉當使用電漿以提高及/或促進緩衝 if H使訂财式軸錢1容執合賴(㈣}、電感 =口電水(ICP)、表面波電聚、或魏線槽孔 戌 或其任何二或多個組合。 ^电水 與I基介電層接觸之缓衝層可作為化學缓衝及/或Cu阻障 衝層係使用包含A1、Ni、Cu、Ni-Cu合金(如M0顺L®) 寻金屬。將上述緩衝層沈積於氟基介電層頂部或底部，可於 定？^機械）、非揮發性、具黏著性、及/或低W之金屬 i t f ，在將A1沈積而與氣基介電層接觸之後，A1 亂化物(例如AIF3)可或不可於界面形成。 若未形成A1氟化物，含A1緩衝層可提供一堅固之黏 該膜在溫度高達約係穩定的(對Ni約㈣。c ;對c 、 =i;、狐⑧約55(rc等）。若形成A1敗化物(如於高溫、 = 物之缓衝層可於氟基介電層與含金屬層之間提 —’金屬1化_如’ A1氣化物)之期望的特 破值(例如，約2.2)，其較接近氟基介電層之k值。總之， 金屬氣化物具有良好的黏著特性與低k值。 含金屬氟化物之緩衝層於超過約1〇〇叱之溫度下係穩定的。 12 201120955 可以任何蒸發塗層法、PVD(例如，喷鍍），或cvd/pec f法沈積緩衝層。-個A1 CVD之範例係制三甲基Layer surface to form an interface, or material (10) mouse H surface, or any two or more groups thereof = on the surface of the ruthenium based ruthenium layer to form a boundary as shown in FIG. 1C 'When a metal-containing layer is formed on a fluorine-based medium The metal containing layer 160 forms a top dielectric layer of the Wei-based dielectric layer (10). Among them, the electro-particles can be detached by mirrors or ion-mixed to form a surface rich in c. When a metal barrier layer (e.g., a metal-containing layer) is formed on the fluorine-based dielectric layer, metal carbides are formed at the interface and these carbides provide a very stable and adhesive interface layer. According to another embodiment, an interface is formed between the fluorine-based dielectric layer and the metal-containing layer, including a deposition process for forming a fluorine-based dielectric layer, and a boundary between the repair layer and the gold-containing contact layer. The composition of the fluorine-based dielectric layer, the gas" adjustment process for forming the fluorine-based dielectric layer may include adjusting one or more of the following conditions: (1) plasma discharge conditions for forming a fluorine-based dielectric layer (2) the pressure used to form the fluorine-based dielectric layer; (3) CF free germanium density; (4) CF2 radical enthalpy; (5) CF3 radical density; (6) the flow rate of the film-forming lead compound; (7) substrate temperature; or (8) flow rate of diluent gas; or (9) two or more combinations thereof, the film-forming lead compound may comprise a CxFy-containing lead compound, wherein X and y are greater than or equal to an integer. In addition, the diluent gas can be combined with the film-forming lead compound to introduce 201120955. The diluent gas may comprise an inert gas such as argon (Ar) or a hydrogen containing gas (such as H2, or NH3, or both). Adjusting the plasma discharge conditions for the deposition process may include adjusting the power coupled to the electrodes of the support substrate, or adjusting the power coupled to the electrodes of the unsupported substrate, or both. When depositing the metal containing layer on top of the fluorine-based dielectric layer , as shown in FIG. 1c (eg, forming a metal-containing layer ι6 顶部 on top of the I-electrode layer 120), or depositing a fluorine-based dielectric layer on top of the metal-containing layer, as shown in FIG. 1D (eg, The dielectric layer 18 is formed on top of the metal containing layer 160)' is suitable for adjusting the deposition process. For example, if a fluorine-based dielectric layer is formed on a gold-containing system, the high-energy charged particles that are not plasma-impregnated are used, and the decorative surface (10) has an interface rich in c-material at the interface, and is not woven. 4 dry. Hunting changes the fluorine-based dielectric layer deposition conditions (such as plasma discharge conditions), can perform a five-night adjustment to grade the interface and produce a c-rich interface, such adjustments (but not limited to): (1) increase the handle The electrode to the support substrate and/or the unsupported substrate force?,; 1? has added _ power to the electrode supporting the substrate; (10) increases the base (v) increases the cf radical density; and the domain (10) reduces the cf2 radical density. Therefore, the H ' of the bond between the atom and the metal atom can be lowered and can also be lowered by the ratio of the total F atom to the c atom of the main body. Urgent tit, speculate that " & and / or H2 diluted into a film lead compound (ie, cxfx from the previous results are not i 2 according to another example, between the fluorine-based dielectric layer and the metal-containing layer to prepare a boundary medium = ======Modify the fluorine gas NQ, _, Ν.2, or fine: or multiple combinations - electricity "(for example, using N2 shape fresh) treatment of fluorine-based layer f layer can be reduced, mu is combined with the table According to another embodiment, a boundary layer 201120955 is prepared between the fluorine-based dielectric layer and the metal-containing layer, and is deposited on the interface between the fluorine-based dielectric layer and the metal-containing layer. The layer may be provided with a stable and adhesive interface with the metal-containing layer, and may also provide a strong bond to the fluorine-based dielectric layer. Preferably, the buffer layer should not substantially modify the fluorine-based dielectric layer. - Embodiment 'Interfacial deposition between the dielectric layer and the metal-containing layer. The deposited layer comprises a deposition-carbonaceous layer selected from the group consisting of tetrahedral amorphous carbon (ta-C), amorphous carbon ( aC), hydrogenated amorphous carbon (a_c: H), diamond-like carbon (DLC), nitriding, crystalline carbon (aC: N), carbon nitride ((3⁄4), amorphous carbon nitride (a_CN), hydrogenation Amorphous carbon nitride (a- CN:H), or any combination thereof, may be deposited using a vapor deposition technique such as chemical vapor deposition slurry promoted CVD (PECVD), atomic layer deposition (ALD), plasma promoted ALD (PEALD) , physical vapor deposition (pvj)), ionized pvD (ipvD), straight memory (VAD), or filter, or any combination of two or more. For example, when the job t is improved / or promote buffer layer deposition, can be used in the following ways to form Jiang plasma. f valley coupled plasma (CCP), inductive surface acoustic plasma), surface wave electricity 7, radiation slot antenna (RLSA) plasma , or vacuum arc plasma, or any of its two layers; a buffer layer containing the following between the tantalum layer and the metal containing layer: four sides J 'or called an amorphous diamond), or a common amorphous carbon (aC) Or aC:H) =; a stone anaerobic (DLC), or nitrided amorphous carbon (a_c: N), or carbon nitride (a-CN, seven CN: H, 'which can act as two different layers of matter a chemical buffer layer. The buffer layer can be reversed or even separated by a metal element containing a gold touch to reduce the reaction between the F atoms of the base dielectric layer. Therefore, a metal carbide can be formed at the interface. Words, The C_C bond (preferably Sp3 mixture) is only worth more than the C_F bond, and the buffer layer containing amorphous carbon does not greatly affect the fluorine-based dielectric layer as an example. Lu's containing amorphous carbon (aC: N) The buffer layer can also be used as a CVD which can be used for electropolymerization (for example, a nitriding amorphous carbon layer by R χ 气 gasification of CCP, muscle ray, etc.) Temperature, power, and pressure, and pay - early key to remove C = N and C = N bond. Because the CN bond has a short bond length of 201120955, the inventor expects to form a dense buffer layer, its inn Reacts with the metal containing layer. In this case, the height of the SP3 bond is removed: 2 t spar is deposited at room temperature using a metal vacuum arc electrician or a single-energy-reading impurity. Lower quality amorphous anti-class ϋ, PVD or CVD deposition, such as wide ion beam assisted deposition. (d) an embodiment of depositing a slow deposition-metal at an interface between a fluorine-based dielectric layer and a metal-containing layer, the metal being selected from the group consisting of: A1, 1, gold, N1 alloy, Cu alloy, or Any two or more combinations. The second layer: phase deposition technique deposit buffer layer, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), electrophoresis into ALD (PEALD), physical vapor deposition (p Or ionized p (milk 1 i ϊΐί or combination. When using plasma to improve and / or promote buffer if H so that the financial axis of the axis 1 tolerance (4)}, inductance = mouth water (ICP) , surface wave electropolymerization, or Wei wire slot or any combination of two or more. ^The buffer layer of electro-hydraulic and I-based dielectric layer can be used as a chemical buffer and / or Cu barrier layer Contains A1, Ni, Cu, Ni-Cu alloys (such as M0 sL®) for metal search. The above buffer layer is deposited on the top or bottom of the fluorine-based dielectric layer, which can be fixed, non-volatile, and adhesive. And / or low W metal itf, A1 disorder (such as AIF3) may or may not be formed at the interface after deposition of A1 and contact with the gas-based dielectric layer. If A1 fluoride is not formed, A1 buffer layer is included. Provides a strong bond that is stable at temperatures up to about (four) c for c, =i; fox 8 about 55 (rc, etc.). If A1 is formed (eg at high temperatures, = Object The stamping layer may provide a desired extra breaking value (for example, about 2.2) between the fluorine-based dielectric layer and the metal-containing layer, which is closer to the fluorine-based dielectric layer. The value of k. In summary, the metal vapor has good adhesion characteristics and low k. The buffer layer containing metal fluoride is stable at temperatures above about 1 12 12 201120955 Any evaporation coating method, PVD ( For example, sputtering, or cvd / pec f deposition buffer layer - an example of A1 CVD system trimethyl

Al2(CH3)6。僅須用一A1薄層形成A1氟化物。任 思地或右品要，依照該應用可蝕刻過量A1。然而，由於 了藉由於而3或N2 t回火(annealing)，或藉由氮氣電漿處= 成扁’過量A1為受歡迎的。A1N提供-良好的铜擴散章^ 而因此，不須另—金屬或金屬氮化物阻障層，如丁aN早材枓 現在轉到圖3A至3E，根據-實施例提供在金屬 氣基^電層與含金屬層之間製備界面之方法之簡易示意圖。 知技藝者將輕易地瞭解，本發明實施例可應用於含一 窗、或渠溝、或其組合之圖案化基板。® 3A ®示說明於基板3曰1〇 上形成於絕緣層320(如上述之氟基介電層）中之渠溝_介層窗圖 33〇，其中將使金屬線(其將形成於渠溝_介層窗圖案33〇準中 經由金屬介層窗(其將形成於渠溝-介層窗圖案330之介層窗部、八 中)與另一金屬線312達到電性及物理接觸。 胃。刀 如於圖3B中所說明，界面34〇係製備於絕緣層32〇之表面。 吾人可使用上述任—方法製備界面340。舉例而言，對絕緣層32〇 而言’界面340可作為—F阻障層。此外，另一界面可製備曰於 於絕緣層320與下方基板31〇之間之邊界314。 、 如於圖3C中所說明，以一或多個共形薄膜350覆蓋渠溝_介 =窗圖案330。一或多個共形薄膜350可包含金屬阻障層、金屬黏 著層、或金屬晶種層、或其任何二或多個組合。然後 ^ 窗圖案330係以金屬355填滿，如Cu。 、 曰 如於圖3D中所說明，磨平以金屬355填滿之渠溝-介層窗圖 案以形成平坦化金屬填充渠溝-介層窗結構360。可使用化學機械 平坦化(CMP)執行平坦化。 予俄铖 如於圖3E中所說明，可使用一或多個覆蓋層38〇覆蓋平坦化 金屬填充渠溝介層窗結構36〇，且可形成另一絕緣層37〇於其 上。此外’又另—界面390係製備於絕緣層370表面上。可使用 任一上述方法製備界面39〇。舉例而言，對絕緣層37〇而言，界面 13 201120955 390可作為F阻障層。 基/^2:’=^1_提供—肋處理基板及製備敗 ^電質金屬化機構之平$ 400之俯視圖 f；l2^ 含全屬屬層之第一成膜系統420、用以修改氟基介電層與 iii ^ 近之&amp;基介電層組成之處理系統柳，及一連 來蔣其如y·甘t41 〇、第二成膜系 '统420、及處理系統430並用 統㈣。處理系統43。概射系 沈二i;系'=含ξ來，基介電層與含編之間 絲Μ :巧一成膜系、，、先。苐二成膜系統可包含氣相沈積系 目沈積(PM系統、離子化Μ '系統、化學氣相沈 Ϊ 賴促進Μ线、原子層沈積(从_統、或 電漿促進ALD糸統、或其任何二或多個組合。 、佳ψί於f 4巾所况明’輸送系統制來輸送—或多個基板 Ϊ f ί 一成膜系統410、第二成膜系統420、及處理系統430，且 製造系統440交換-或多個基板。多元製造系统44〇可 匕3負載緊固元件(load-lock element)以容許基板晶圓匣盒 (cassettes)在大氣條件與低壓條件之間循環。 輸送系統470可包含專屬載具46〇，其用以將一或多個基板於 成膜系統410、第二成膜系統420、處理系統43〇、及多元製 ^统440之間移動。於一個實施例中，多元製造系統44〇容許 將基板輸送至處理元件及從處理元件輸送基板，處理元件包含如 钮刻系統、沈積系統、塗佈系統、圖案化系統、計量系統等裝置。 /為隔離發生於第-成膜系統、第二成膜系統42〇、及處理 糸，《0中之製程，利用隔離組件45〇將各個系統與輸送系統47〇 及〈元製造系統440搞合。例如，隔離組件450可包含至少一個 熱Pw離組件以提供熱隔離，及一閘閥組件以提供真空隔離。當然， y以任何序列設置第一成膜系統·、第二成膜系、統42〇、及處理 糸統430。 14 201120955 明睁可於ΐϋ貝於上’熟知此技藝者將容易地 教ΐΐΐ 中實行許多修改，*未實質地奴本發明新穎的 〜、優點。耻’所有腿修JL係意欲包含於本利之範嘴中。 【圖式簡單說明】 於所附圖示中： 圖1Α至1D根據一實施例，呈現一種在急茸人 層之間製備-界面之方法之㈣示意圖；在m層與含金屬 圖2根據另一實施例，說明一種在氟基介rt3 ^ 間製備—界面之方法； 销細電層與含金屬層之 一種在氣基介電層=屬i之 圖3A至3E根據一實施例，呈現一種在今 介電層與含金屬層之間製備-界面之方屬内中之氟基 圖4掩祕—叙am 一人·乃間易不意圖；及 間 製備 【主要元件符號說明】 110基板 i20氟基介電層 140界面 160含金屬層 170第二界面 180介電層 200流程圖 210於一基板上形成一氟基介電層 220於遠基板上形成一含金屬層 230在該氟基介電 310基板 層與該含麵層之間製備—界面 312金屬線 314邊界 320絕緣層 15 201120955 330渠溝-介層窗圖案 340界面 350薄膜 355金屬 360平坦化金屬填充渠溝-介層窗結構 370絕緣層 380覆蓋層 390界面 400平臺 410第一成膜系統 420第二成膜系統 430處理系統 440多元製造系統 442基板 450隔離組件 460專屬載具 470輸送系統 16Al2(CH3)6. It is only necessary to form an A1 fluoride with a thin layer of A1. If you want to use it, you can etch excess A1 according to the application. However, it is popular because of the 3 or N2 t annealing, or by the nitrogen plasma = flattened 'excess A1'. A1N provides - good copper diffusion chapter ^ and therefore, no additional metal or metal nitride barrier layer, such as D-AN, is now transferred to Figures 3A to 3E, according to the embodiment - provided in the metal gas base A simplified schematic representation of a method of preparing an interface between a layer and a metal containing layer. Those skilled in the art will readily appreciate that embodiments of the present invention are applicable to patterned substrates having a window, or a trench, or a combination thereof. ® 3A ® shows a trench-via window 33 形成 formed on the substrate 3 曰 1 于 in an insulating layer 320 (such as the above-described fluorine-based dielectric layer), in which a metal line (which will be formed in the channel) The trench-via window pattern 33 is in electrical and physical contact with another metal line 312 via a metal via (which will be formed in the via, eight of the trench-via window pattern 330). The knife 34 is prepared on the surface of the insulating layer 32. As described above, the interface 340 can be prepared using any of the above methods. For example, for the insulating layer 32, the interface 340 can be As a barrier layer, another interface may be formed between the insulating layer 320 and the lower substrate 31A. 314. As illustrated in FIG. 3C, covered with one or more conformal films 350. The trench pattern may include a metal barrier layer, a metal adhesion layer, or a metal seed layer, or any combination of two or more thereof. The window pattern 330 is then The metal 355 is filled, such as Cu. As described in Figure 3D, the trench-via window pattern filled with metal 355 is smoothed. The trench-via window structure 360 is filled with a planarized metal. The planarization can be performed using chemical mechanical planarization (CMP). As illustrated in Figure 3E, one or more cap layers 38 can be used to cover. The planarized metal-filled trench via structure 36 is formed and another insulating layer 37 can be formed thereon. Further, an interface 390 is prepared on the surface of the insulating layer 370. The interface can be prepared using any of the above methods. For example, for the insulating layer 37, the interface 13 201120955 390 can be used as the F barrier layer. Base / ^ 2: '= ^ 1_ provide - rib processing substrate and preparation failure metallization metallization mechanism The top view of the flat $400; l2^ The first film forming system 420 containing all the genus layers, the processing system for modifying the fluorine-based dielectric layer and the iii ^ near &amp; dielectric layer, and a connection Come to Jiang Qiru y· Gan t41 〇, the second film forming system 420, and the processing system 430 and use the system (4). The processing system 43. The general system is Shen II; the system is = ,, the base dielectric layer and the inclusion Between the silkworms: the film system, the first, the film system can contain vapor deposition system (PM system, away Μ 'System, chemical vapor deposition depends on promoting the Μ line, atomic layer deposition (from the _ system, or plasma to promote ALD system, or any combination of two or more. 佳 ψ 于 in f 4 The delivery system is configured to deliver - or a plurality of substrates Ϊ f ί a film forming system 410, a second film forming system 420, and a processing system 430, and the manufacturing system 440 exchanges - or a plurality of substrates. The multi-component manufacturing system 44 3 load-lock elements to allow substrate wafer cassettes to circulate between atmospheric and low pressure conditions. Conveying system 470 can include a dedicated carrier 46A for moving one or more substrates between film forming system 410, second film forming system 420, processing system 43A, and multi-component system 440. In one embodiment, the multi-component manufacturing system 44 allows the substrate to be transported to and from the processing element, the processing element including devices such as buttoning systems, deposition systems, coating systems, patterning systems, metrology systems, and the like. / for isolation occurs in the first film forming system, the second film forming system 42 〇, and the processing 糸, the process in the 0, using the isolation module 45 〇 to integrate each system with the transport system 47 〈 and the <meta fabrication system 440 . For example, the isolation assembly 450 can include at least one thermal Pw isolation assembly to provide thermal isolation and a gate valve assembly to provide vacuum isolation. Of course, y sets the first film forming system, the second film forming system, the system 42, and the processing system 430 in any sequence. 14 201120955 Alum can be found on the top of the ’ ’ ’ 此 此 此 技 技 技 此 此 此 此 此 此 此 此 此 此 此 此 此 ’ 此 ’ ’ ’ 。 。 。 。 。 。 。 。 。 Shame All JL lines are intended to be included in the mouth of Benley. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: FIG. 1A to FIG. 1D are schematic diagrams showing a method of preparing an interface between layers of a violent human body according to an embodiment, in which the m layer and the metal containing FIG. An embodiment illustrates a method of preparing an interface between fluorine-based dielectric layers; a pin-like electrical layer and a metal-containing layer in a gas-based dielectric layer = genus of FIGS. 3A to 3E according to an embodiment, presenting a Fluorine group in the preparation of the interface between the dielectric layer and the metal-containing layer. Figure 4 Masking - Syrian one person · 乃易易意意; and preparation [main component symbol description] 110 substrate i20 fluorine The dielectric layer 140 interface 160 includes a metal layer 170. The second interface 180 dielectric layer 200. The flow chart 210 forms a fluorine-based dielectric layer 220 on a substrate to form a metal-containing layer 230 on the far substrate. Between the 310 substrate layer and the containing layer - interface 312 metal line 314 boundary 320 insulating layer 15 201120955 330 trench - via window pattern 340 interface 350 film 355 metal 360 flattening metal filled trench - via window structure 370 Insulation layer 380 cover layer 390 interface 400 platform 410 first Membrane system 420 second film forming system 430 processing system 440 multi-component manufacturing system 442 substrate 450 isolation component 460 exclusive carrier 470 conveyor system 16

Claims (1)

201120955 七、申請專利範圍： 1. 一種基介電質結合金屬化機構之方法 於一基板上形成一氟基介電層； 於該基板上形成一含金屬層；及 屬層 間之===:改該氣基介電層與含金 介電層， 將該氟基介電層暴露至包含呢之氮氣電衆。 2. 如申請專利範圍第i項之職基介電質处 附近、於該界面、或該界面内之:及/或減少於該界面 結合金屬化機構之方 多個組合照射該氟基介電層。 、子束、或八任何二或 ==，，，質結合金屬化機構之方 驟，係在用 執行 以於該基板上職該氟基介電層之相_沈積I統$ 電層之步 電質結合金屬化機構之方 之沈積製程之步驟，包含調 電條件， 5·如申請專利範圍第1項之將氟基介 法，其中調整用以形成該氟基介電層 整一或多個下述條件： 用以形成該氟基介電層之電漿敌 用以形成該氟基介電層之壓力， 17 201120955 CF自由基密度， CF2自由基密度， CF3自由基密度， 成膜前導化合物之流量， 基板溫度* 稀釋氣體之流量，或 其二或多個組合。 6·如申請專利範圍第5項之將氟基介電質結合金屬化機構之方 法，其中該成膜則導化合物包含一含CxF前導化合物，其中χ與 y係大於或等於一之整數。 =申請專利範圍第5項之將氟基介電質結合金屬化機構之方 / ’八中雜職體包含1性氣體或—含氫氣體、或其組合。 專，圍第5項之將氣基介電質結合金屬化機構之方 叙^ !^魏電漿放€條件包含：調整與—支_基板之電極 ^之功率、或調整與-未支禮該基板之電_合之功率、或兩 如申5月專利範圍第8項之將氟基介電質結合金屬化機構之方 ^其中調魏沈積齡之步含：增續於支板之該 之功率、增加對於未支撐該基板之該電極之功率、降低用以 ^成，氟，介電層之壓力、增加該基板溫度、增加該CF自由基密 二二減少該口?2自由基密度、或減少該自由基密度、或其任 何一或多個組合。 =如：請專利範圍第1項之將介電質結合金屬化機構之方 個該氮氣電漿包含风、N0、N2〇、N〇2、或其任何二或多 201120955 11.如申請專利篇圖笛，= 法，其中該氟基介t 介f質結合金屬化機，方 料。 曰已3 s盈鼠、混合氟、或掺雜氟之介電材 法，结合金屬化機構之方 二申以二第= =如 Ιίί利範圍第1項之將氟基介電質結合金屬化機構之方 於該氟基介電層與該含金屬層之_成—金屬阻障層。 15. 一備氟基介金屬化機構之平臺，包含. ^ t膜系統’用以於一基板上形成一氟基介 ΐΐΐϊ系統’用以於祕板上形成—含金屬層厂 近之該氟基介電層之組成；及 /、、’屬g間之界面附 輸送糸統，連接至該第一成膜丰餅、兮當_ 處理系統，且用來將基板於其間輸送。W〜成膜系統、與該 16. ，申請專利範圍第15項之用以製備氟基介 平堂’其中該氟基介電層包含合金I、混合氟、=屬化機構之 材料。 或摻雜氟之介電 Π.如申請專利範圍第i5項之用以製備I基介 平臺，其中該處理系統包含一輻射系統，該輻系氣屬化機構之 電漿浸沒之高能帶電粒子照射該氟基介電層。’、统係用來以非 19 201120955 18. 如申請專利範圍帛17項之用 其 平臺，其中該輻射系統包含一 鼠基電質金屬化機構之 團簇離子束源、或其任何二或多個: 一離子束源、或-氣體 19. 如申請專利範圍第15 平臺，其中該第二成膜基介電質金屬化機構之 形成該氟基介電層⑵-控制器，該控制器係用來調整 20. 如肀請專利範圍第15項之用以製備 平臺，其中該處理系統包含—錢處t 1質金屬化機構之 用來形成含氮電該含氮電漿含有^、而^電系= 任何二或多個組合。 JN2〇 N02或其 21·—種將氟基介電質結合金屬化機構之方法，包含： 於一基板上形成一氟基介電層； 3 於該基板上形成一含金屬層；及 於該絲介電層與該含金屬層H面形成—声 f衝層包含—選自於下_組叙鱗之含韻··叫^晶碳/ ΐί)、非晶碳(a_C)、氮化非晶碳(a-C:H)、類鑽碳(DLC)、氮1非 曰曰石反㈣州、氮化碳(c3n4)、非晶型氮化碳(a_CN) 化碳(a-CN:H)、或其任何二或多個組合。 ^曰^•亂 22.如申請專利範圍第21項之將介電質結合金屬化機構之方 法’其中該氟基介電層包含合金氟、混合氟、或掺雜氣之介電材 料0 23. 如申請專利範圍第21項之將氟基介電質結合金屬化機構之方 法，其中該氟基介電層包含一含CFX材料。 24. 如申請專利範圍第21項之將氟基介電質結合金屬化機構之方 20 201120955 • 法，其中該氟基介電層包含一敦化非晶石炭介電材料。 如利乾圍第21項之將氣基介電質結合金屬化機構之方 於該氟基介電層與該含金屬層之間形成—金屬阻障層。 26.如申請專利範圍第21項之將氟基介電質处人今眉仆機構之方 法，其中該緩衝層係使用氣相沈積製程^成y金屬化機構之方 公如第21項之將氟基介電質結合金屬化機構之方 程、離成：物理氣相沈積(_製 程、電漿促進助製程、真空電孤殿 s 式VAD製程、或其任何二或多個組合。 =其項之將氣基介電質結合金屬化機構之方 式耦合t*tcrcFl /财式械’電容故合賴(CCP)、電感 真空電弧^ 雜^電聚、或 结合金屬化機構之方法，包含： ，板上形成—氟基介電層； 含金屬層；及 屬缓衝該含金屬層間之界面形成一緩衝層，該金 、自由Ni、Ni合金、或兩者所組成之族群之金屬。 法’其中ίίπϋι之將5基介電質結合金屬化機構之方 料。 土书θ匕έ合金氟、混合氟、或摻雜氟之介電材 21 201120955 3二= 介r包 如利乾圍第29項之將氣基介電質結合金屬化機構之方 於該氟基介電層與該含金屬層之間形成—金屬阻障層。 Ϊ如第f項之將介電質結合金屬化機構之方 ，、中3亥緩衝層係使用氣相沈積製程形成j ί如項之將敗基介電質結合金屬化機構之方 ΐ、離用下列製程形成：物理氣相沈積_)製 製程、；^子# 、化學氣相沈積(CVD)製程、電聚促進cvd iL層沈積()製程、電漿促進ald製程、直空電弧殿 積(VAD)製程、過渡式製程、或其任何=多個組 =弧瓜 式耦八雷H法形成.电合式耦合電漿(ccp)、電感 真或槽孔天線_顺、或 37·-種將氟基介電質結合金屬化機構之方法，包含. 於一基板上形成CFX系介電層； 於該基板上形成一含金屬層；及 於該*^基介電層與該含金屬層之間 金層包含—選自於下列所組成之族ί之』1 u 、Nl合金、Cu合金、或其任何二或多個組合。 22 201120955 38. —種用以製備氟基介電質金屬化機構之平臺，包含： 第一成膜系統，用以於一基板上形成一氟基介電層； 第一成膜系統’用以於邊基板上形成一含金屬層； 第三成膜系統，用以於該氟基介電層與該含金屬層之間沈積 一缓衝層，該缓衝層包含一選自於下列所組成之族群之含礙層： 四面體非晶碳(ta-C)、非晶碳(a-C)、氫化非晶碳(a_c:H)、類鑽碳 (DLC) ’氮化非晶破(a-C:N)、氮化碳(C3N4)、非晶型氮化碳(a_Qq)、 氫化非晶型氮化碳(a-CN:H)、或其任何二或多個組合，或一選自於 下列所組成之族群之金屬：Ni、Ni合金、Al、A1合金、Cu、Cu 合金、或兩者；及 “ 輸送糸統，連接至§玄第一成膜糸統、該第二成膜系統與該第 三成膜系統，且該輸送系統係用來將基板於其間輸送'。' ^ 39. 如申睛專利範圍第38項之用以製備氟基介電質金屬化機構之 系統，其中該第三成膜系統包含一氣相沈積系統。 40. 如申明專利範圍第38項之用以製備氟基介電質金屬化機構之 糸、、充/、中„亥氧相沈積糸統包含一物理氣相沈積系統、一離 子化PVD系統、一化學氣相沈積(CVD)系統、—電喂促進cvd 系統、一原子層沈積(ALD)系統 '一電漿促進ALD 7 一直空 電弧殿積(VAD)製程、或一過渡式VAD製程、或盆任何二或 組合。 八、圖式： 23201120955 VII. Patent application scope: 1. A method for forming a fluorine-based dielectric layer on a substrate by a method of combining a dielectric material and a metallization mechanism; forming a metal-containing layer on the substrate; and between the genus layers ===: The gas-based dielectric layer and the gold-containing dielectric layer are modified to expose the fluorine-based dielectric layer to the contained nitrogen gas. 2. illuminating the fluorine-based dielectric in the vicinity of the dielectric-based dielectric region of the i-th application of the patent scope, at the interface, or within the interface: and/or by reducing the combination of the interface and the metallization mechanism Floor. , sub-beam, or eight any two or ==,, the combination of the metallization mechanism is used to perform the phase of the fluorine-based dielectric layer on the substrate. The step of the deposition process of the electric material combined with the metallization mechanism, including the electric adjustment condition, 5. The fluorine-based dielectric method according to the first application of the patent scope, wherein the fluorine-based dielectric layer is adjusted to form one or more The following conditions: The plasma used to form the fluorine-based dielectric layer is used to form the pressure of the fluorine-based dielectric layer, 17 201120955 CF radical density, CF2 radical density, CF3 radical density, film formation lead The flow rate of the compound, the substrate temperature * the flow rate of the diluent gas, or a combination of two or more thereof. 6. A method of bonding a fluorine-based dielectric to a metallization mechanism according to claim 5, wherein the film-forming compound comprises a CxF-containing lead compound, wherein χ and y are greater than or equal to an integer. = The party that applies the fluorine-based dielectric to the metallization mechanism in the fifth application of the patent scope / the eight-in-one miscellaneous body contains a monogas or a hydrogen-containing gas, or a combination thereof. Specialized, the fifth section of the gas-based dielectric combined with the metallization mechanism of the ^ ^ ^ Wei plasma placed € conditions include: adjustment and - support _ substrate electrode ^ power, or adjustment and - unsupported The power of the substrate, or the method of combining the metallization mechanism of the fluorine-based dielectric with the metallurgical mechanism of the eighth paragraph of the patent scope of the application of the fifth aspect of the invention, includes the step of adjusting the deposition age of the substrate: Power, increase the power of the electrode that does not support the substrate, reduce the pressure for the fluorine, the dielectric layer, increase the temperature of the substrate, increase the density of the CF radical, and reduce the density of the 2? Or reducing the free radical density, or any one or more combinations thereof. = For example, please refer to the first paragraph of the patent scope that combines the dielectric material with the metallization mechanism. The nitrogen plasma contains wind, N0, N2, N2, or any two or more of them 201120955 11. If you apply for a patent Figure flute, = method, in which the fluorine-based medium is combined with a metallizer, a square material.曰 has 3 s squirrel, mixed fluorine, or fluorine-doped dielectric material method, combined with the metallization mechanism of the second two = = Ι ίί 利 range of the first item of the fluorine-based dielectric metallization The mechanism is formed on the fluorine-based dielectric layer and the metal-containing layer-metal barrier layer. 15. A platform for a fluorine-containing metallization mechanism, comprising: a film system for forming a fluorine-based dielectric system on a substrate for forming on a secret plate - a metal-containing layer near the fluorine The composition of the base dielectric layer; and/or, the interface between the genus g and the transport system, connected to the first film forming cake, the _ processing system, and used to transport the substrate therebetween. W~ film forming system, and 16. The patent application scope 15 is used for preparing a fluorine-based dielectric layer, wherein the fluorine-based dielectric layer comprises a material of alloy I, mixed fluorine, and a chemical grouping mechanism. Or a fluorine-doped dielectric Π. For the preparation of the I-based platform according to the scope of claim i5, wherein the processing system comprises a radiation system, and the high-energy charged particle irradiation of the plasma immersion mechanism of the radiation gasification mechanism The fluorine-based dielectric layer. ', the system used to non-19 201120955 18. The platform for applying the patent scope 帛17, wherein the radiation system comprises a cluster ion beam source of a murine-based electric metallization mechanism, or any two or more thereof An ion beam source, or a gas 19. According to the fifteenth platform of the patent application, wherein the second film-forming dielectric metallization mechanism forms the fluorine-based dielectric layer (2)-controller, the controller Used to adjust 20. For the preparation of the platform according to Item 15 of the patent, wherein the treatment system comprises - the metallization mechanism of the money is used to form the nitrogen-containing electricity, the nitrogen-containing plasma contains ^, and ^ Electrical system = any two or more combinations. JN2〇N02 or a method thereof for bonding a fluorine-based dielectric material to a metallization mechanism, comprising: forming a fluorine-based dielectric layer on a substrate; 3 forming a metal-containing layer on the substrate; The silk dielectric layer and the H-side of the metal-containing layer are formed - the acoustic f-press layer comprises - selected from the group consisting of the rhymes of the lower group, the crystal carbon / ΐί), the amorphous carbon (a_C), and the non-nitriding Crystalline carbon (aC:H), diamond-like carbon (DLC), nitrogen 1 non- vermiculite anti-four (state), carbon nitride (c3n4), amorphous carbon nitride (a_CN) carbon (a-CN: H) Or any two or more combinations thereof. ^曰^•乱22. The method of combining a dielectric-bonding metallization mechanism according to claim 21 of the patent application, wherein the fluorine-based dielectric layer comprises alloy fluorine, mixed fluorine, or doped gas dielectric material. A method of bonding a fluorine-based dielectric to a metallization mechanism according to claim 21, wherein the fluorine-based dielectric layer comprises a CFX-containing material. 24. The method of claim 21, wherein the fluorine-based dielectric layer comprises a Dunhua amorphous carbon-carbon dielectric material. The metal-based dielectric bonding metallization mechanism of the 21st item of Liganwei forms a metal barrier layer between the fluorine-based dielectric layer and the metal-containing layer. 26. The method of claim 21, wherein the buffer layer is a vapor-based deposition process using a vapor deposition process; The dielectric is combined with the equation of the metallization mechanism, separation: physical vapor deposition (_process, plasma promotion assisted process, vacuum electric solitary VAD process, or any combination of two or more thereof. The method of coupling a gas-based dielectric in combination with a metallization mechanism to t*tcrcFl/Finance Machinery's Capacitor (CCP), Inductive Vacuum Arcing, Hybridization, or a metallization mechanism, including: Forming a fluorine-based dielectric layer; a metal-containing layer; and a metal buffering the interface between the metal-containing layers to form a buffer layer, the gold, the free Ni, the Ni alloy, or a group of the two. The method 'where ίίπϋι The 5 base dielectric is combined with the material of the metallization mechanism. The soil θ 匕έ alloy fluorine, mixed fluorine, or fluorine-doped dielectric material 21 201120955 3 2 = Intermediary package such as Li Ganwei item 29 The gas-based dielectric is bonded to the metallization mechanism to the fluorine-based dielectric Forming a metal barrier layer between the metal-containing layer. For example, in the item f, the dielectric is bonded to the metallization mechanism, and the medium-buried buffer layer is formed by using a vapor deposition process. The ruthenium-based dielectric combined with the metallization mechanism is formed by the following processes: physical vapor deposition _) manufacturing process, ^子#, chemical vapor deposition (CVD) process, electropolymerization to promote cvd iL layer deposition ( Process, plasma-promoted ald process, direct-arc arc-dwelling (VAD) process, transition process, or any of its = multiple groups = arc-gull-coupled eight-ray H method. Electro-coupled plasma (ccp), An inductor or a slot antenna _ cis, or a method for bonding a fluorine-based dielectric to a metallization mechanism, comprising: forming a CFX dielectric layer on a substrate; forming a metal containing layer on the substrate; And the gold layer between the dielectric layer and the metal-containing layer comprises - a group selected from the group consisting of 11 u , an alloy of Nl, a Cu alloy, or any combination thereof. 22 201120955 38. A platform for preparing a fluorine-based dielectric metallization mechanism, comprising: a first film formation system for forming a fluorine-based dielectric layer on a substrate; a first film formation system Forming a metal-containing layer on the edge substrate; a third film formation system for depositing a buffer layer between the fluorine-based dielectric layer and the metal-containing layer, the buffer layer comprising a layer selected from the group consisting of The barrier layer of the group: tetrahedral amorphous carbon (ta-C), amorphous carbon (aC), hydrogenated amorphous carbon (a_c: H), diamond-like carbon (DLC) 'nitrided amorphous (aC: N), carbon nitride (C3N4), amorphous carbon nitride (a_Qq), hydrogenated amorphous carbon nitride (a-CN: H), or any combination thereof, or one selected from the following Metals of the group consisting of: Ni, Ni alloy, Al, Al alloy, Cu, Cu alloy, or both; and "transportation system, connected to § Xuan first film-forming system, the second film-forming system and The third film forming system, and the conveying system is used to transport the substrate therebetween. ^ 39. The system for preparing a fluorine-based dielectric metallization mechanism according to claim 38 of the scope of the patent application, wherein The third film-forming system comprises a vapor deposition system. 40. For the preparation of a fluorine-based dielectric metallization mechanism according to claim 38 of the patent scope, the charge/discharge system contains a physics. Vapor deposition system, an ionized PVD system, a chemical vapor deposition (CVD) system, an electric feed-promoting cvd system, an atomic layer deposition (ALD) system, a plasma-promoting ALD 7 constant arc arc product (VAD) ) Process, or a transitional VAD process, or any combination or combination of basins. Eight, schema: 23
TW099134060A 2009-10-06 2010-10-06 Method of providing stable and adhesive interface between fluorine-based low-k material and metal barrier layer TW201120955A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/574,101 US20110081500A1 (en) 2009-10-06 2009-10-06 Method of providing stable and adhesive interface between fluorine-based low-k material and metal barrier layer
US12/574,117 US20110081503A1 (en) 2009-10-06 2009-10-06 Method of depositing stable and adhesive interface between fluorine-based low-k material and metal barrier layer

Publications (1)

Publication Number Publication Date
TW201120955A true TW201120955A (en) 2011-06-16

Family

ID=43857077

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099134060A TW201120955A (en) 2009-10-06 2010-10-06 Method of providing stable and adhesive interface between fluorine-based low-k material and metal barrier layer

Country Status (2)

Country Link
TW (1) TW201120955A (en)
WO (1) WO2011044053A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI505360B (en) * 2011-09-24 2015-10-21 Tokyo Electron Ltd Method of forming metal carbide barrier layers for fluorocarbon films

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6051321A (en) * 1997-10-24 2000-04-18 Quester Technology, Inc. Low dielectric constant materials and method
US8053171B2 (en) * 2004-01-16 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Substrate having film pattern and manufacturing method of the same, manufacturing method of semiconductor device, liquid crystal television, and EL television
US20060054279A1 (en) * 2004-09-10 2006-03-16 Yunsang Kim Apparatus for the optimization of atmospheric plasma in a processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI505360B (en) * 2011-09-24 2015-10-21 Tokyo Electron Ltd Method of forming metal carbide barrier layers for fluorocarbon films

Also Published As

Publication number Publication date
WO2011044053A1 (en) 2011-04-14

Similar Documents

Publication Publication Date Title
US20140127902A1 (en) Method of providing stable and adhesive interface between fluorine based low k material and metal barrier layer
KR102542758B1 (en) Ruthenium metal feature filling for interconnects
TW575930B (en) Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics
US7910476B2 (en) Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop
TWI402887B (en) Structures and methods for integration of ultralow-k dielectrics with improved reliability
US6566246B1 (en) Deposition of conformal copper seed layers by control of barrier layer morphology
TWI645511B (en) Doped tantalum nitride for copper barrier applications
TWI374482B (en)
TW201030173A (en) Densification process for titanium nitride layer for submicron applications
TW200939394A (en) Method for forming an air gap in multilevel interconnect structure
TW201022466A (en) Dielectric barrier deposition using oxygen containing precursor
TWI827553B (en) Ruthenium metal feature fill for interconnects
TW200524042A (en) Structures with improved interfacial strength of sicoh dielectrics and method for preparing the same
JP7309697B2 (en) Method and apparatus for filling features of a substrate with cobalt
US20140151097A1 (en) Method and Structure to Improve the Conductivity of Narrow Copper Filled Vias
TWI295485B (en) Method of improving low-k film property and damascene process using the same
TW201201278A (en) Chemical vapor deposition of ruthenium films containing oxygen or carbon
US9938622B2 (en) Method to deposit CVD ruthenium
US20110081503A1 (en) Method of depositing stable and adhesive interface between fluorine-based low-k material and metal barrier layer
JP5025679B2 (en) Semiconductor device
TW529065B (en) Semiconductor device and method for manufacturing the same
TW201120955A (en) Method of providing stable and adhesive interface between fluorine-based low-k material and metal barrier layer
WO2015184573A1 (en) Ultra-low dielectric constant insulating film and method for manufacturing same
JP4447438B2 (en) Manufacturing method of semiconductor device
TW574409B (en) Method for incorporating silicon into CVD metal films