TW494528B - Method for filling gaps on a semiconductor wafer - Google Patents
Method for filling gaps on a semiconductor wafer Download PDFInfo
- Publication number
- TW494528B TW494528B TW089103781A TW89103781A TW494528B TW 494528 B TW494528 B TW 494528B TW 089103781 A TW089103781 A TW 089103781A TW 89103781 A TW89103781 A TW 89103781A TW 494528 B TW494528 B TW 494528B
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- Prior art keywords
- semiconductor wafer
- gap
- patent application
- reaction chamber
- dielectric material
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Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 13
- 230000008021 deposition Effects 0.000 claims abstract description 11
- 239000003989 dielectric material Substances 0.000 claims abstract description 11
- 238000006243 chemical reaction Methods 0.000 claims description 19
- 239000007789 gas Substances 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 18
- 238000005137 deposition process Methods 0.000 description 9
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000002079 cooperative effect Effects 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 208000021236 Hereditary diffuse leukoencephalopathy with axonal spheroids and pigmented glia Diseases 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 239000004327 boric acid Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 208000036969 diffuse hereditary with spheroids 1 leukoencephalopathy Diseases 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- -1 halogen ions Chemical class 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- DQWPFSLDHJDLRL-UHFFFAOYSA-N triethyl phosphate Chemical compound CCOP(=O)(OCC)OCC DQWPFSLDHJDLRL-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Description
494528 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(< ) 本發明係關於一種用介電質材料塡充半導體晶圓之方 法,其係使用CVD製程設備,在上升溫度之電漿和真空 條件下執行C V D沈積。 製造積體半導體電路之製程技術,需要塡充在半導體 晶圓表面之間隙。在執行完某製程步驟之後,晶圓會產 生許多積體電路組件。塡充間隙之需求尤其是要將〇 . 2 5 次微米設計法則應用到半導體晶圓的製造中。間隙可位 在電晶體之間,依淺溝渠絕緣技術(S TI)作絕緣,或可位 在多晶砂sJl號線之間’ g亥訊號線係事先經過金屬化製程 步驟(預金屬介電質,PMD )。此介電質材料可以任何已 知的介電質材料塡充間隙,如S i 0 2、B P S G、P S G、B S G、 SiN等等。 在已知的ICs製程中,寧可使用合成或無效率的CVD 沈積製程塡充間隙。例如,使用在約3 5 0到4 0 0 °C下,基 於矽烷/氬氣混合氣體之高密度電漿(HDP)-CVD反應 腔,同時沈積和濺鍍氧化物。此外,也可以使用在6 0 0 P下,基於矽烷/氨氣混合氣體之HDP-CVD-製程塡充間 隙。但是,氨氣的離子很輕,所以其濺鍍效率幾乎爲零.。 使其導致塡充間隙底部的上面。 另一種使用的製程係後沈積重新流動技術,即,先在 硼磷矽酸玻璃(BPSG)或原矽酸四乙酯(TEOS)基底上,沈 積一玻璃,然後再在8 5 Ot下作退火。還有另一種使用的 製程係在大於7 5 (TC之轉變溫度下,在玻璃上同步重新流 動的技術,例如在低壓(LP)-CVD-反應腔之中;該玻璃本 (請先閱讀背面之注意事項再填寫本頁) -dm 訂· 線· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 494528 A7 B7 五、發明說明(> ) 身也會流動。當玻璃轉變溫度約低於400到600 °c時’要 使用一種次常壓(SA)-CVD反應腔。SACVD反應腔之操作 壓力範圍通常是20到60〇T〇rr · H D P - C V D反應腔係操作在非常低的壓力之下,範圍通 常是從1到2S mTorr。此種反應腔體有點昂貴。SACVD反 應腔使用生效臭氧分子。晶圓之反轉時間有點低,使得 一些SACVD反應腔必須並聯操作。因此,HDP-CVD-或 SACVD爲主之製程相當昂貴。 美國專利第5,643,640號揭露一種使用電漿增強式 (PE)-CVD沈積之氯摻雜磷矽酸玻璃製程(FPSG),用以塡 充間隙或空隙。這些間隙會有很高的外觀比。該製程係 約在4 0 0到5 0 0 °C之間的溫度下完成。但是,使用氯氣會 有污染,傷害閘極氧化物的缺點,或氯氣會進一步氧化 的缺點。在深四分之一微米製程技術之線準位的下前 端,並不希望使用氯摻雜沈積材料。 本發明之目的在於提供一種塡充半導體晶圓間隙之改 良方法’即,以適度之成本提供一種良好無空穴之具有 介電質的間隙塡充。 該目的係藉由根據申請專利範圍第1項之特徵的方法 加以解決。 本發明之方法係使用電漿增強式(p E ) - C V D沈積設備, 上升溫度尚於5 0 0 °C。該溫度之範圍特別是在5 0 0到7 0 0 °C之間。在這PECVD製程中,不需要使用鹵素離子或基。 根據本發明之PECVD沈積製程,可以應用到任何常見之 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) (請先閱讀背面之注咅?事項再填寫本頁) ή^τ· -丨線· 經濟部智慧財產局員工消費合作社印製 494528 A7 B7 五、發明說明(3 ) 介電質材料,如Si〇2、BPSG、PSG、BSG、SiN’並可提 (請先閱讀背面之注意事項再填寫本頁) 供共形塡充間隙。PECVD反應腔係操作在適當的溫度和 真空壓力下,使得此反應腔之成本低於HDP-CVD設備。 PECVD反應器的產量高於SACVD反應腔。事實上,根據 本發明之PECVD腔體,其成本約爲HDP-CVD腔體的一 半,而產量則約爲SAC VD腔體的一倍。 宜在5 00 °C和7〇〇 °C之間的反應溫度,係藉由位在載送 半導體晶片之容器下的陶質加熱組件加熱而得。真空係 由真空泵產生。而壓力則在1〇〇 mTorr到10 Torr之間。 在腔體中的電漿氣體係由射頻訊號產生。該訊號之頻 率大於10MHz,以13.5MHz爲佳。該射頻訊號耦合進入 到相對於晶圓正面之腔體中。根據本發明之較佳實施 例,也是耦合第二射頻訊號進入到腔體中。該第二射頻 訊號之頻率小於ΙΟΟΚΗζ,以約ΙΟΚΗζ爲佳。此意味著這 兩個射頻訊號的頻率大小,至少差兩個階次。第一射頻 訊號的功率有幾百瓦。第二射頻訊號則具有較低的功 率。兩訊號可透過不同的耦合裝置進入到腔體,或透過 相同的耦合裝置進入到腔體之中。 經濟部智慧財產局員工消費合作社印製 在腔體中的反應氣體可爲任何已知種類之成分。由於 高溫,不需要增加鹵素元素或臭氧基元素。反應氣體或 先質氣體成分包含下列組成其中之一: 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
五、 發明說明(4 ) 要沈積之介電質材料 Si〇2 S iN BSG PSG BPSG BSG/PSG/BPSG :硼— 先質 TE0S、0 SiH 4 SiH 4 TEOS、TEB、Ο N 20、N 2 N 20、NH 3
N
SiH 4、B 2H 6、N 20、N 2 TE0S、ΤΕΡ0
SiH
PH TEOS、TEB、TEPO、〇2、N2或 SiH4、PH3、B2H6、N20、N2 /磷矽酸一 /硼磷矽酸玻璃 (請先閱讀背面之注意事項再填寫本頁) τ E B :硼酸三乙酯 TEPO :磷酸三乙酯 要根據本發明的方法處理之半導體晶圓,在其表面上 具有要塡充之間隙。此間隙爲已蝕刻進入矽基板之淺溝 渠,例如’蝕刻係利用任何乾蝕刻技術。溝渠係要彼此 相互隔離和絕緣相同型式之電晶體。此種佈局結構常稱 爲淺溝渠絕緣(STI)。 本發明另一個應用的領域係藉由多晶矽導線結構,建 立間隙之塡充。在個別的製程步驟期間,在晶圓的頂部, 沈積一由多晶矽,矽化鎢和氮化物所構成之多層結構。 在製作圖案之後,爲了要產生區域連接,如DRAMs之聞 極電極連接和溝渠電容器連接,間隙係留在多層次多晶 矽導線結構之間,根據本發明之P E C V D製程,用介電f 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 線· 經濟部智慧財產局員工消費合作社印製 494528 A7 B7 五、發明說明(r ) (請先閱讀背面之注意事項再填寫本頁) 材料塡充間隙。在多晶矽結構中的間隙具有高達1 7之外 觀比。在塡充的平坦多晶矽一介電質表面上,爲了導線, 要再沈積一金屬層。因此,上述之介電質被稱爲預金屬 介電質(PMD)。 在根據本發明之PECVD沈積製程的條件下,由於上升 溫度,反應的分子具有足夠的移動率,使得它們可以到 達間隙的底部,而沈積在那裡。由於該上升溫度,分子 的較高移動率會減少角效應,即分子主要沈積在間隙上 部邊緣之現象。耦合進入到反應腔體之第二射頻,會在 間隙上部邊緣造成濺鍍效應。即藉由第二射頻訊號的應 用,分子空易沈積在再鬆掉的位置。 本發明將參考下面的圖式,作進一步的說明,其中 第1圖爲根據習知技術塡充之間隙; 第2圖爲根據本發明塡充之間隙。 經濟部智慧財彦局員工消費合作社印製 在不定的圖式中,個別的組件以相同的參考符號標 式。要被塡充之間隙1係位在兩相同型式之C Μ 0 S電晶 體之間,其係位在半導體晶圓2之上表面之上。爲了防 止耦合在電晶體之間,在電晶體之間的基板被溝渠1切 割。此種技術稱爲淺溝渠絕緣(S Τ I )。第1圖爲習知P EC V D 沈積製程,約操作在4 0 0 °C下之應用。例如,在兩個範例 中,塡充間隙之材料係由二氧化矽(S i 0 2)構成。在沈積製 程期間,二氧化物會成長在晶圓表面上。圖式之連續層 3 a、3 b、3 c和3 d表示,在瞬間之後,沈積材料的最終厚 度。注意,在正常的PECVD反應參數之下,在間隙1之 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公f ) 經濟部智慧財彦局員工消費合作社印製 494528 A7 B7 五、發明說明(t ) 上部邊緣4的沈積速率高於間隙1之側壁5或底部6。結 果’在間隙1之上部邊緣4的S i 0 2成長快於底部6。因 此,間隙在完全和齊性的塡滿之前,間隙的表面會先 封閉。而使在間隙的中心留下一空穴7。 根據本發明的P E C V D沈積製程,係即使間隙具有很高 的外觀比,也要提供沒有任何空穴的間隙齊性塡充。根 據弟2圖’將半導體晶圓插入到p e c V D沈積設備的反應 腔之中,而放置在容納晶圓的容器上。在沈積製程期間, 利用真空泵將腔體之壓力抽降到100 mTorr和10 Torr之 間。該腔體含有用於沈積SiO 2之反應氣體,成份包含 TEOS、〇2、N2或SiH4、N20、N2。該腔體之溫度被加熱 到高於5 0 0 t,如600 °C。加熱係藉由在容器下之陶質加 熱組件完成。將RF訊號,如13.56 MHz,耦合到腔體, 以產生電漿。最好,也將1 0 0 Κ Η z之RF訊號耦口到腔體。 第一 RF訊號和第二RF訊號之功率,對於200mm單片晶 s圓反應器而言,分別爲1 〇 0到1 0 0 0瓦。在執行沈積製程 期間,分子會平均的沈積在晶圓的表面上。所有沈積位 置之SiO 2層的成長速率大致相同。間隙1在上部邊緣4, 側壁5和底部6之成長速率的大小大致相同。這是爲什 麼在上部邊緣4之角圍繞效應消失的原因。由於其具有 很高的移動率,所以反應氣體分子到達進入間隙,且以 大致相同的速率沈積在其底部和其側壁上。因此,可以 用SiO 2很齊性地塡充間隙,而沒有任何空穴。在第2圖 中,層8a.....8e表示以連續時間沈積SiO 2而沒有角效 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁)
^4528 A7 B7 1、發明說明(7 ) 應之層。但是,在沈積結束的時候,會在間隙1中心上 方留下一小的凹痕。此凹痕將會在後續的硏磨步驟期間 平坦化。該凹痕並不會受到晶圓表面的平坦度很大的影 響,且可以在進一步的製程中被忽略。 第二上JLJJI.號的應甩可以改善間隙的塡充行爲。第二 RF訊號可以提供一種濺鍍效應,所以沈積在角落區域4 之材料可以再次立即地被濺離。 總之,本發明提供一種特殊的PECVD沈積製程,用介 電質材料,以均勻之無空穴之方式塡充在半導體晶圓表 面上之間隙。由於PECVD性質的關係,較之習知的間隙 塡充技術,製程設備相當的便宜,且具有很高的產出率。 符號說明 1…間隙 2…半導體晶圓 3 a…層 3 b…層 3 c…層 3 d…層 4…上部邊緣 5…側壁 6…底部 7…空穴 8 a…層 8 b ··.層 8 c…層 -9- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公f ) (請先閱讀背面之注意事項再填寫本頁)
--------訂---------—I 經濟部智慧財彦局員工消費合作社印制农 「Γ· 494528 A7 B7 五、發明說明( 層層 痕凹 (請先閱讀背面之注意事項再填寫本頁) ;線_ 經濟部智慧財彦局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 494528六、申請專利範圍 第89103781號「用於塡充半導體晶圓間隙的方法」專利案 (91年3月修正) 六申請專利範圍 1. 一種用於介電質材料塡充半導體晶圓間隙之方法,其步驟 包含: 一將該半導體晶圓(2)插入電漿增強化學氣相沈積製程 設備之反應腔體中, 一在電漿條件下和在真空條件下,完成C VD沈積,以 沈積該介電質材料(3a.....3d ; 8a.....8e)在該半導體 晶圓(2)之上, 一在高於500°C的溫度下,完成CVD沈積步驟。 2·如申請專利範圍第1項之方法,其中在該設備之該反應腔 體中之該溫度,其範圍係從500°C到700°C。 3·如申請專利範圍第1項之方法,其中在該設備之該反應腔 體中之氣體壓力,其範圍係從100 mTorr到lOTorr。 4·如申請專利範圍第2項之方法,其中在該設備之該反應腔 體中之氣體壓力,其範圍係從100 mTorr到lOTorr。 5·如申請專利範圍第1至4項中任一項之方法,其中包含將 第一和第二射頻訊號耦合進入到該腔體,且產生對應該射 頻訊號之電漿的步驟,該第二射頻訊號頻率的大小至少比 該第一射頻訊號小兩個階次。 6. 如申請專利範圍第5項之方法,其中該第一頻率大於10 MHz,而該第二頻率則小於1〇〇 KHz。 7. 如申請專利範圍第1至4項中任一項之方法,其中在CVD 494528六、申請專利範圍 沈積步驟期間,塡充該腔體之反應氣體成份包含一群含有 TE〇S、SiH4、TEB、b2h6、TEP〇、Ph3、〇2、n2〇、Nh3、 N 2之任何氣體。 8·如申請專利範圍第1至4項中任一項之方法,其中由 該 介電質材料(3a.....3d ; 8a.....8e)塡充之該半導體晶 圓(2)的該間隙,係形成在該半導體晶圓(2)上的電晶體之 間。 9.如申請專利範圍第1至4項中任一項之方法,其中由該介 電質材料塡充之該半導體晶圓的該間隙,係形成在該半導 體晶圓上部之部份金屬化層間。 -2
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EP (1) | EP1169733A1 (zh) |
JP (1) | JP3492634B2 (zh) |
KR (1) | KR100420753B1 (zh) |
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US20040016962A1 (en) * | 2002-04-30 | 2004-01-29 | Hideki Okumura | Semiconductor device |
JP2004165405A (ja) * | 2002-11-13 | 2004-06-10 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
KR100540637B1 (ko) * | 2002-12-28 | 2006-01-11 | 동부아남반도체 주식회사 | 반도체 소자의 제조 방법 |
DE10361697B4 (de) * | 2003-12-30 | 2011-08-11 | Infineon Technologies AG, 81669 | Verfahren zum Herstellen einer Grabenstruktur mit Oxidationsauskleidung, zum Herstellen einer integrierten Halbleiterschaltungsanordnung oder eines Chips, zum Herstellen eines Halbleiterbauelements sowie mit diesem Verfahren hergestellte integrierte Halbleiterschaltungsanordnung, hergestellter Chip, hergestelltes Halbleiterbauelement |
US7884030B1 (en) | 2006-04-21 | 2011-02-08 | Advanced Micro Devices, Inc. and Spansion LLC | Gap-filling with uniform properties |
EP2507823B1 (en) * | 2009-12-04 | 2018-09-26 | Semiconductor Energy Laboratory Co. Ltd. | Manufacturing method for semiconductor device |
KR102117506B1 (ko) | 2009-12-04 | 2020-06-01 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제조 방법 |
US9257274B2 (en) | 2010-04-15 | 2016-02-09 | Lam Research Corporation | Gapfill of variable aspect ratio features with a composite PEALD and PECVD method |
US8637411B2 (en) | 2010-04-15 | 2014-01-28 | Novellus Systems, Inc. | Plasma activated conformal dielectric film deposition |
US9997357B2 (en) | 2010-04-15 | 2018-06-12 | Lam Research Corporation | Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors |
JP6538300B2 (ja) | 2012-11-08 | 2019-07-03 | ノベラス・システムズ・インコーポレーテッドNovellus Systems Incorporated | 感受性基材上にフィルムを蒸着するための方法 |
SG2013083241A (en) * | 2012-11-08 | 2014-06-27 | Novellus Systems Inc | Conformal film deposition for gapfill |
US9564312B2 (en) | 2014-11-24 | 2017-02-07 | Lam Research Corporation | Selective inhibition in atomic layer deposition of silicon-containing films |
US10566187B2 (en) | 2015-03-20 | 2020-02-18 | Lam Research Corporation | Ultrathin atomic layer deposition film accuracy thickness control |
US9644271B1 (en) * | 2016-05-13 | 2017-05-09 | Lam Research Corporation | Systems and methods for using electrical asymmetry effect to control plasma process space in semiconductor fabrication |
US9773643B1 (en) | 2016-06-30 | 2017-09-26 | Lam Research Corporation | Apparatus and method for deposition and etch in gap fill |
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US10037884B2 (en) | 2016-08-31 | 2018-07-31 | Lam Research Corporation | Selective atomic layer deposition for gapfill using sacrificial underlayer |
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TWI764008B (zh) * | 2018-06-19 | 2022-05-11 | 美商應用材料股份有限公司 | 高品質間隙填充的高偏壓沉積 |
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US5204138A (en) * | 1991-12-24 | 1993-04-20 | International Business Machines Corporation | Plasma enhanced CVD process for fluorinated silicon nitride films |
US5356722A (en) * | 1992-06-10 | 1994-10-18 | Applied Materials, Inc. | Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity |
EP0759481A1 (en) * | 1995-06-23 | 1997-02-26 | Novellus Systems, Inc. | Method of depositing a stable fluorinated TEOS film |
US5643640A (en) | 1995-11-27 | 1997-07-01 | International Business Machines Corporation | Fluorine doped plasma enhanced phospho-silicate glass, and process |
WO1997024761A1 (en) * | 1995-12-27 | 1997-07-10 | Lam Research Corporation | Methods and apparatus for filling trenches in a semiconductor wafer |
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US6004873A (en) * | 1996-06-19 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing the pattern sensitivity of ozone assisted chemical vapor deposited (CVD) silicon oxide insulator layers |
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US5741740A (en) * | 1997-06-12 | 1998-04-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer |
US6153261A (en) * | 1999-05-28 | 2000-11-28 | Applied Materials, Inc. | Dielectric film deposition employing a bistertiarybutylaminesilane precursor |
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US20020042186A1 (en) | 2002-04-11 |
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