TW466482B - Synchronous semiconductor memory device - Google Patents
Synchronous semiconductor memory device Download PDFInfo
- Publication number
- TW466482B TW466482B TW089104020A TW89104020A TW466482B TW 466482 B TW466482 B TW 466482B TW 089104020 A TW089104020 A TW 089104020A TW 89104020 A TW89104020 A TW 89104020A TW 466482 B TW466482 B TW 466482B
- Authority
- TW
- Taiwan
- Prior art keywords
- data
- data line
- aforementioned
- memory cell
- bit
- Prior art date
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000872 buffer Substances 0.000 claims abstract description 53
- 230000002093 peripheral effect Effects 0.000 claims abstract description 48
- 230000004913 activation Effects 0.000 claims description 17
- 230000005540 biological transmission Effects 0.000 claims description 12
- 230000000295 complement effect Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 5
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 239000010977 jade Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000002079 cooperative effect Effects 0.000 description 3
- 230000000875 corresponding effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- KQPKMEYBZUPZGK-UHFFFAOYSA-N 4-[(4-azido-2-nitroanilino)methyl]-5-(hydroxymethyl)-2-methylpyridin-3-ol Chemical compound CC1=NC=C(CO)C(CNC=2C(=CC(=CC=2)N=[N+]=[N-])[N+]([O-])=O)=C1O KQPKMEYBZUPZGK-UHFFFAOYSA-N 0.000 description 1
- 101001111984 Homo sapiens N-acylneuraminate-9-phosphatase Proteins 0.000 description 1
- 102100023906 N-acylneuraminate-9-phosphatase Human genes 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11060440A JP2000260181A (ja) | 1999-03-08 | 1999-03-08 | 同期型半導体記憶装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW466482B true TW466482B (en) | 2001-12-01 |
Family
ID=13142344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089104020A TW466482B (en) | 1999-03-08 | 2000-03-07 | Synchronous semiconductor memory device |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6163501A (enExample) |
| EP (1) | EP1035548B1 (enExample) |
| JP (1) | JP2000260181A (enExample) |
| KR (1) | KR100368368B1 (enExample) |
| DE (1) | DE60037846T2 (enExample) |
| TW (1) | TW466482B (enExample) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100499623B1 (ko) * | 1998-12-24 | 2005-09-26 | 주식회사 하이닉스반도체 | 내부 명령신호 발생장치 및 그 방법 |
| DE19934500C2 (de) * | 1999-07-22 | 2001-10-31 | Infineon Technologies Ag | Synchroner integrierter Speicher |
| US6392935B1 (en) * | 2000-04-03 | 2002-05-21 | Maxtor Corporation | Maximum bandwidth/minimum latency SDRAM interface |
| KR100372247B1 (ko) * | 2000-05-22 | 2003-02-17 | 삼성전자주식회사 | 프리페치 동작모드를 가지는 반도체 메모리 장치 및 메인데이터 라인수를 줄이기 위한 데이터 전송방법 |
| US6756823B1 (en) * | 2000-06-28 | 2004-06-29 | Intel Corporation | Differential sense latch scheme |
| JP4684394B2 (ja) * | 2000-07-05 | 2011-05-18 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
| JP4514945B2 (ja) * | 2000-12-22 | 2010-07-28 | 富士通セミコンダクター株式会社 | 半導体装置 |
| US6515914B2 (en) * | 2001-03-21 | 2003-02-04 | Micron Technology, Inc. | Memory device and method having data path with multiple prefetch I/O configurations |
| KR100468719B1 (ko) * | 2002-01-11 | 2005-01-29 | 삼성전자주식회사 | Ｎ 비트 프리페치 방식과 2ｎ 버스트 길이를 지원할 수있는 반도체 메모리 장치 |
| US20030182208A1 (en) * | 2002-03-19 | 2003-09-25 | Eloda Inc. | Method and system for assisting consumer decision making and providing on-demand viewing access to broadcast and rich media ads |
| US6678201B2 (en) * | 2002-04-08 | 2004-01-13 | Micron Technology, Inc. | Distributed FIFO in synchronous memory |
| DE10260647B3 (de) * | 2002-12-23 | 2004-08-26 | Infineon Technologies Ag | Integrierter Halbleiterspeicher, insbesondere DRAM-Speicher, und Verfahren zum Betrieb desselben |
| WO2005045846A1 (ja) * | 2003-11-06 | 2005-05-19 | International Business Machines Corporation | 半導体記憶装置及びそのバースト動作方法 |
| KR20110088947A (ko) * | 2010-01-29 | 2011-08-04 | 주식회사 하이닉스반도체 | 반도체 메모리의 데이터 출력 회로 |
| US10025532B2 (en) * | 2015-09-11 | 2018-07-17 | Sandisk Technologies Llc | Preserving read look ahead data in auxiliary latches |
| US10642513B2 (en) | 2015-09-11 | 2020-05-05 | Sandisk Technologies Llc | Partially de-centralized latch management architectures for storage devices |
| TWI749823B (zh) * | 2020-10-23 | 2021-12-11 | 美商矽成積體電路股份有限公司 | 內部鎖存器電路及其鎖存信號產生方法 |
| KR20240177547A (ko) | 2023-06-20 | 2024-12-27 | 나영호 | 정화통을 구비한 용접 마스크 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3599334B2 (ja) * | 1991-08-16 | 2004-12-08 | マルティチップ テクノロジー， インコーポレイテッド | 高性能ダイナミックメモリシステム |
| JP2907074B2 (ja) * | 1995-08-25 | 1999-06-21 | 日本電気株式会社 | 半導体記憶装置 |
| JP3351692B2 (ja) * | 1995-09-12 | 2002-12-03 | 株式会社東芝 | シンクロナス半導体メモリ装置 |
| JP2817679B2 (ja) * | 1995-09-20 | 1998-10-30 | 日本電気株式会社 | 半導体メモリ |
| US5784705A (en) * | 1996-07-15 | 1998-07-21 | Mosys, Incorporated | Method and structure for performing pipeline burst accesses in a semiconductor memory |
| US6011748A (en) * | 1996-10-03 | 2000-01-04 | Credence Systems Corporation | Method and apparatus for built-in self test of integrated circuits providing for separate row and column addresses |
| JP4221764B2 (ja) * | 1997-04-25 | 2009-02-12 | 沖電気工業株式会社 | 半導体記憶装置 |
-
1999
- 1999-03-08 JP JP11060440A patent/JP2000260181A/ja active Pending
-
2000
- 2000-03-07 TW TW089104020A patent/TW466482B/zh not_active IP Right Cessation
- 2000-03-07 KR KR10-2000-0011203A patent/KR100368368B1/ko not_active Expired - Fee Related
- 2000-03-08 EP EP00104469A patent/EP1035548B1/en not_active Expired - Lifetime
- 2000-03-08 US US09/520,720 patent/US6163501A/en not_active Expired - Fee Related
- 2000-03-08 DE DE60037846T patent/DE60037846T2/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000062766A (ko) | 2000-10-25 |
| JP2000260181A (ja) | 2000-09-22 |
| EP1035548A1 (en) | 2000-09-13 |
| DE60037846D1 (de) | 2008-03-13 |
| KR100368368B1 (ko) | 2003-01-24 |
| US6163501A (en) | 2000-12-19 |
| EP1035548B1 (en) | 2008-01-23 |
| DE60037846T2 (de) | 2009-01-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |