TW455960B - Semiconductor device and mounting structure of a semiconductor device - Google Patents
Semiconductor device and mounting structure of a semiconductor device Download PDFInfo
- Publication number
- TW455960B TW455960B TW089105276A TW89105276A TW455960B TW 455960 B TW455960 B TW 455960B TW 089105276 A TW089105276 A TW 089105276A TW 89105276 A TW89105276 A TW 89105276A TW 455960 B TW455960 B TW 455960B
- Authority
- TW
- Taiwan
- Prior art keywords
- component
- solder
- metal block
- electrode
- melting point
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 229910000679 solder Inorganic materials 0.000 claims abstract description 102
- 230000008018 melting Effects 0.000 claims abstract description 31
- 238000002844 melting Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005476 soldering Methods 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 90
- 239000002184 metal Substances 0.000 claims description 90
- 239000004020 conductor Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 238000003466 welding Methods 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 230000002079 cooperative effect Effects 0.000 claims description 4
- 238000009434 installation Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000003112 inhibitor Substances 0.000 claims 1
- 230000005496 eutectics Effects 0.000 abstract 6
- 230000035939 shock Effects 0.000 description 17
- 238000012360 testing method Methods 0.000 description 11
- 238000011156 evaluation Methods 0.000 description 10
- 239000007769 metal material Substances 0.000 description 9
- 238000005336 cracking Methods 0.000 description 8
- 239000000203 mixture Substances 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000002349 favourable effect Effects 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 229910052745 lead Inorganic materials 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910052778 Plutonium Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000006184 cosolvent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 235000012054 meals Nutrition 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920002098 polyfluorene Polymers 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
4 5 5 9 6 0 A7 五、發明說明(1 ) ’ 發明背景 1. 發明領域 本發明係有關用以將半導體元件安裝至安裝基材(諸 如,印刷電路板)之結構,及其半導體元件。 2. 相關技藝之描述 用以使半導體元件安裝至印刷電路板之習知技藝結構 之基本觀念於下述將參考第4圖描述之。 首先,半導體元件10及印刷電路板12之一般結構將被 解釋。 電極14被形成而被曝露於半導體元件1〇之表面上。 金屬塊16係事先被附接至電極μ之表面上。金屬境16 係由共鎔焊料製得’以具有一般為球形或柱狀。 桿18係於印刷電路板π之表面積上形成,而半導體元 件係以相對應至於半導體元件丨〇上形成之電極14之位置而 被安裝至印刷電路板12。 其次’用以安裝半導體元件1〇(至印刷電路板12)之結 搆漿被解釋。 半導體元件10被置於印刷電路板12之安裝區域上,如 此,附接至半導體元件10之個別電極14之個別金屬塊16係 置放於印刷電路板12之相對應墊18上。 於保持此位置關係時,熱被施於共鎔焊料之金屬塊16 〇 因此,半導體元件10被置於印刷電路板12上。 於上述之用以安裝半導體元件之習知技藝結構中,共 本紙張尺度適用中國國家標準(CNTS)A4規格(210 X 297公釐) f請先閱讀背面之注意事項再填寫本頁) 裝-------ί 訂---------^, 經濟部智慧財產局員工消費合作社印製 4 A7 B; 經濟部智慧財產局員工消費合泎钍扣契 五、發明說明( 鎔焊料之球形或柱狀金屬塊16被熔融而於印刷電路板12側 上之整個墊12上流動。藉此,金屬塊〖6如第4圖所示產生 形狀崩裂’降低高度Η » 特別地,當半導體元件係小尺寸時,如第5圖所示之 參考編號10所示者,其中絕緣保護獏3〇係於鈍性膜28上形 成,鋁之電極端子26經其曝露,且電接連至電極端子“之 電路圖案32係於保護膜30上形成,且其中(第5圖之柱形) 電極14係於電路圖案32上形成,其係被包覆於模樹脂妬内 而僅曝露出個別電極14之頂端,且金屬塊16係與其附接之 ,或如第6圖所示,其中金屬塊16係直接附接至於半導體 晶片24之活性元件表面上形成之電極14,其需使金屬塊之 直徑變小,因為電極14之配置間距係小的3作為例子,當 約〇.45 mm直彳;l之球形金屬塊16被形成時,於被您融後之 高度係於約0.3至〇.32mm之範圍。 但是,發現於接連可靠性評估測試(其中,半導體元 件1 〇接受熱沖擊,且同時被安裝至印刷電路板12)中,其 具有之趨勢係於安裝至印刷電路板12後之金屬塊16之高度 愈南,測試結果愈佳。因此,期欲使金屬塊16之高度儘可 能保持大,以實現高可靠性。 再者.當半導體元件接受熱沖擊時,疲勞(例如,破 裂)會產生於半導體元件丨〇上之金屬塊丨6端部或印刷電路 板12上之其端部附近’造成連接失敗。因此,有幫助者係 乓加具有低強度之端部區域之強度’以實施高可靠性, 衧別地.於第5或6圖岬示之丰導體元沣丨〇内之金屬塊 -------------裝--------訂---------線 (請先閱讀背面之沈意事項再填寫本頁)
經濟部智慧財產局員工消费合作社印製 4 5 5 9 6 Ο Α7 __Β7 五、發明說明(3 ) 16之原始高度係低的’其最重要係儘可能保持原始高度以 促進連接可靠性。 發明综述 本發明之目的係提供用以使半導體元件安裝至印刷電 路板之結構,及能進一步穩定半導體元件與印刷電路板間 之連接之半導體元件本身s 本發明之另一目的係解決上述之習知技藝中之問題。 依據本發明’其提供一種用以使具有電極之半導想元 件安裝於具有導電墊之安裝基材上之安裝結構,該結構包 含.金屬塊’其係使該半導體元件之電極電連接至該導電 墊;第一共錯焊料,其用於該金屬塊與該半導體元件之該 電極間之焊接;第二共鎔焊料,其用於該金屬塊與該基材 之該導電墊間之焊接; 該金屬塊之熔點係高於該第一及第二共鎔烊料,且對 於該第一共錄焊料之疲勞之抗性係不同於第二共嫁焊料者 〇 依據如上所述之本發明,因為金屬塊係由具有高於第 一及第二共鎔焊料者之熔點之金屬物料製得,當半導體元 件於其女裝期間加熱時,金屬塊係未被熔融以保持原始高 度。藉此,有利之結果可於連接可靠性評估中獲得,其中 ,半導體元件接受熱沖擊,且同時被安裝至印刷電路板。 再者’為使金屬塊之端部之一者連接至半導鱧元件側上或 於印刷電路板侧上,其甲被認為疲勞(諸如,破裂)係易於 產生於曝露至熱沖擊時,具有較高之抗疲勞之共鎔焊 本纸張尺度適用中關家標準(CNS>A.l規格公复) 6 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 I. Λ, B7 五、發明說明(4 使用之(其係指相較於用於連接另一端部者而言),如此, 對熱沖擊之耐久性整體被促進,而產生高可靠性s 具有較高之抗疲勞性之共鎔焊料之例子係主要甴Sn 組份及Pb組份組成,且亦由Ag組份、[n組份、Sb組份及 組份之至少二者組成,例如,包含63質量%之化組份叫u 質量。/。之Pb組份、!質量%之1:1组份、〇 7質量%之处組份 及1質量%之Ag組份組成。 具有較高之抗疲勞性<共録焊料之其它例子係如下述 第I表所不.(1)添加至如及朴之二金屬(選自Ag,卜及外) :⑺添加至Sn及Pb之三金屬(Ag,InMb):及⑴添加至Sn 及抑之四金屬(Ag,in,Sb及Cu)。 第I表 1 _ --------- (物料之%丨 Sn Pb Ag ----- In Sb Cu 丨添加二金屬 63 L餘量 ,1.0 _ 1,0 A 0 添加二金屬 餘量 -----— 0 j 1.0 0 0.7 0 添加二金屬 63 餘量 0 1.0 0.7 0 : 添加二金屬 63叫 餘量― 1.0 0 1.0 0 添加二金屬 63 餘量 1.0 ----j 1.0 0.7 〇 添加四金屬 63 餘d ·. —1-1 1.0 1.0 1.0 0.1 作為金屬塊之物料之々,丨;总—a , 丁叶千係南熔點焊料,Cu或Ni ' 其具有r^j於共嫁焊料者之溶點。 依據本發3月之半導艚亓杜^ 守萌7L件之實施例,其中絕緣保護獏 係於半導體元件表面上形忐' $成·且電極瑞子係於其上形成, 旦電連接至電極端子之雷#片 '电路圖案係於絕緣保護琪上形成、 請 先 閱 讀 背 面 注 意 事 項 再 填 1 I裝 訂 線 經濟邹智慧財產局員工消費合作社印絜 ; 4 559, A7 B7 五、發明說明(5 ) ; 且其中該金屬塊係附接至於電路圖案上形成之電極,用於 金屬塊及電極間之共鎔焊料係由63質量%之811組份、343 質量%之Pb組份、1質量。/。之比组份及i質量%之人§組份組 成’以具有高的抗疲勞性,且金屬塊係由具有高於共鎔焊 料者之溶點之金屬物料製得a 依據本發明之半導體元件之另一實施例,其中金屬塊 被附接至於半導體元件上形成之電極端子,用於金屬塊及 電極間之共鎔焊料係由63質量%之Sn組份、14.3質量%2Pb 組份、1質量%之In組份、〇.7質量%之訃組份及1質量ΰ/〇之 Ag組份組成’以具有高的抗疲勞性,且金屬塊係由具有 高於共鎔焊料者之熔點之金屬物料製得。 此等半導體元件對熱沖擊具有高耐用性,於連接可靠 性評估測試中形成高可靠性,其中,半導體元件於被安裝 至印刷電路板後接受熱沖擊’因為用於半導體元件側上之 金屬塊之端部之共鎔焊料(其一般被認為易產生疲勞(諸如 ,破裂))具有比用於印刷電路板侧上之金屬塊端部之另一 共鎔焊料者更高之抗疲勞性。 圖示簡要說明 第1圖係用以解釋依據本發明之半導體元件之安裝結 構之一方面之例示; 第2圖係用以解釋依據本發明之晶片尺寸之半導體元 件之一方面及用以解釋其中此半導體元件被安裝至印刷電 路板之結構之例示; 第3圊係用以解釋依據本發明之晶片尺寸之半導體元 本紙張尺度適用111國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 經濟部智慧財產局員工消費合作社印製 ;濟 丨部 .智 :慧 ϊί )局 .肖 ::; .丨让 ::卬 Λ7 B7 五、發明說明(6 ) 件及用以解釋其丰導體元件被安裝至印刷電路板之結構之 另一方面之例示; 第4圖係用以解釋用於半導體元件之習知技藝安裝结 構之例子之例示; 第5圖係用以解釋習知技藝半導體元件之例子之例示 第6圖係用以解釋習知技藝之半導體元件之另一例子 之例示; 第7圖係圖示與習知技藝有關之本發明功效之比較實 驗資料;及 第8圖係顯示用於第7圖實驗之高溫焊料球之載面圖。 實施例之詳細描述 完成本發明之最佳模式將於下述參考附圖作詳細描述 首先’用以安裝半導體元件之結構係參考第丨圖朝 之。於此關係中,半導體元件及印刷電路板之基本結相 質上係相同於有關習知技藝所描述者,相同之參考編號 用於此圖示心表示相㈣件,且其詳細解釋將被除去 半導體元件丨0之電極M經由金屬塊丨6(其係由具有 於共鎔焊料者之'職之㈣物料形幻電連接至印刷電 板12上之如,雖然金属塊⑽形成具有料例子之如 1圖所不之球形輪廓,塊狀物可為柱狀。 液據本發明之韦於半導禮元件之安裝結構之第一特 在於金屬塊邮由具有高於共㈣料者之㈣之金屬物
4 5 59 ο 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明(7 ) , 製得,即使如其後所述之用於使金屬塊16焊接至半導體元 件10之電極14及印刷電路板12之墊18之共鎔焊料被熔融, 金屬塊16未被熔融且保持其原始形狀及高度η。例如,此 金屬物料可為具有比共鎔焊料(由61.9質量%之Sn組份、 38.1質量%之pb組份組成’且具有1 83 °C熔點)更高熔點之 高溶點焊料(Cu或Ni) »於此方面’高炫融焊料可由具有90 至97質量%iPb組份之pb-Sn合金組成。其熔點係約3〇〇°C 。因為金屬塊16可保持預定之所欲高度η,藉此,其可於 連接可靠性評估測試達成有利結果,其中具有之被安裝至 印刷電路板12後之金屬塊16之高度愈大,測試結果愈佳之 趨勢。 雖然共鎔焊料20,22被用以使金屬塊16焊接至半導體 元件10之電極14及印刷電路板12之墊18,本發明之第二特 徵在於用以使金屬塊16連接至半導體元件之電極14之共 銘焊料20及用以使金屬塊16連接至印刷電路板12之整之共 録焊料之一者具有比另一共鎔焊料更高之抗疲勞性。具有 較高抗疲勞性之共鎔焊料之例子係基本上£>1>_511合金组成 者’其被添加特定元素以使結構内之金屬間化合物結晶, 如此Pb之移動及生長被抑制以實現較長之生命期或較佳 之抗疲勞性。其典型之組成物係63質量%之Sn組份、14.3 質量%之Pb組份、1質量。/。之]^組份、〇 7質量。/。之Sb組份 及1質量%之Ag組份,以形成丨83。(:之熔點。 以具有高抗疲勞性之共鎔焊料焊接之部份係藉由連接 可靠性評估測試之結果決定,其中事先安裝至印刷電路板 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公g ) 10 ----------- ' --------訂---------吹 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合泎社 A7 ______ . B7 _ 五、發明說明(8 ) 12之丰導體元件丨〇接受熱沖擊。 一般而s,因其需使電極14之表面積小於印刷電路板 12上提供之墊者,金屬塊[6與半導體元件1〇之電極14間之 焊接部份(即,使金屬塊16之端部焊接至半導體元件1〇之 共銥焊料20)之載面積係小於金屬塊16及印刷電路板丨2之 墊1 8間之另一焊接部份者(即,使金屬塊丨6之端部焊接至 印刷電路板12側之共鎔焊料22) 3其被認為諸如破裂之疲 勞更易於產生於連接可靠性評估測試中之使金屬塊16之端 部焊接於丰導體元件1〇上之共鎔焊料2〇。因此,具有較高 抗疲勞性之共鎔焊料被作為共鎔焊料2〇。 相反地,若於半導體元件10上提供之電極之表面積係 大於印刷電路板丨2上提供之墊者且用於使金屬塊16之端部 焊接於印刷電路板12上之共鎵焊料系更易於在連接可靠性 评估測試中產生諸如破裂之疲勞,則具有較高之抗疲勞性 之共您焊料被使用之。 依據此一结構,因為用於使金屬塊16端部之一者連接 至半導體元件】0及印刷電路板1 6側(其被認為接受熱沖擊 時更易於產生諸如破裂之疲勞)上之共鎔焊料於耐久性上 被改良,其可促進半導體元件10整體對抗熱沖擊之安裝結 構,形成高可靠性之達成= 雖然藉由事先添加特定元素至傳統共鎔焊料而獲得之 具有較高抗疲勞性之共鎔焊料被用於上述實施例.一般當 金屬塊丨6使用共鎔焊料焊接至半導體元件1〇之電極14或其 上帶有金屬塊之半導體元件1 0被安裝至印刷電路板丨,時, f帝〈實適甲七:g萏孓嘌盈..CVS.:A4規蜱.:,:j9:_ γ«广~ --—_ ^--------t---------線 (請先閱讀背面之江意事項再填寫本頁) 4 5 5 9 1 A7 __B7_ 五、發明說明(9 ) , 其係採用其中事先以助熔劑塗覆後電極14或墊16以共鎔焊 料糊塗覆之方法,或其中焊料層被置於電極14表面上或墊 18及助熔劑被塗覆於其上之方法。 於此一情況中’上述特殊元素非於起始時被添加至共 鎔焊料,而係添加至助熔劑。當共鎔焊料被加熱及熔融時 ,包含於助熔劑内之特殊元素係與共鎔焊料混口。結果, 可何使事先與特殊元素混合之助溶劑使傳統之共鎵焊料轉 化成具有1¾的抗疲勞性者。 其次,適於上述安裝結構之半導體元件之結構將參考 第2及3圖解釋之。 其後描述之半導體元件係具有已參考第5及6圖之習知 技藝解釋之所謂晶片尺寸輪廓之半導體元件。 首先,第2圖所示之半導體元件ι〇被描述。因為此半 導體元件10基本上係相同於第5圖所示之半導體元件1〇 , 相同之參考編號被用於表示相似之零件。 於此結構中,絕緣保護膜3〇係於半導體晶片24之形成 電極端子之表面上之鈍性膜28上形成,藉此,由例如鋁製 得之電極端子26被曝露出。注意其可為不具有鈍性膜28等 之結構。 電連接至電極端子26之電路圖案32係於保護獏30上形 成’且電極14(或第2圖之柱狀)係於電路圖案32上形成, 且被包覆於模樹脂36内,如此,僅電極14之尖端部被曝露 出°金屬塊16經由共鎔焊料2〇接合至電極14之曝露出之尖 端部。 本紙張尺度適用中_家標準(CNS)A4規格(& χ 297公餐··) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------今 經濟部智慧財產局員工消費合作社印製 12 Λ7 B7 五、發明說明(10 ) 此配置之特效在於金屬塊1 6彳糸由具有高於共慰焊料者 之熔點之金屬物料形成,諸如,高熔點焊料,Cu或Ni , 且共錯焊料20係上述之具有高抗疲勞性者。 如前所述,此係因為當半導體元件1〇被安裝至印刷電 路板12時’金屬塊16未被熔融以保證足夠高度,且用於使 金屬塊16之端部連接至半導體元件丨〇上之共鎔焊料2〇之抗 疲勞性破改良’其部份係憑經驗認為於連接可靠性評估測 試中易產生諸如破裂之疲勞。 當半導體元件10被安裝至印刷電路板丨2時,用以使金 屬塊16被安裝至印刷電路板之墊18(未示於第1圖,但相 似於第1圖中所示者)之另一共鎔焊料22係傳統之組成物。 其次’如第3圖所示之半導體元件1〇將被描述。相同 之參考編號被用以表示第2圖所示半導體元件1 〇之相似零 件。 絕緣保護膜30(例如,聚醯亞胺)係於鈍度膜28上形成 ,半導體晶片26之電極端子經其曝露出,且電路圖案32於 保護膜30上形成,用以與電極端子26連接。 第二絕緣保護膜(例如,聚醯亞胺膜8係於其上提供 電路圖案之整個表面上形成3相對應至電路圖案32之部份 <金屬塊16被附接者)之第二保護膜3 8之部份被移除以形成 電極U。 金屬塊16以共鎔焊料20接合至電極14。 以如第2圖所示半導體元件[〇之相同方式.金屬塊16 係由具有高於共銘焊枓者之熔點之金屬物料製成’諸如' ------ -------I ----- — I ! .丨 -----I* (請先閱讀背面之注意事項再填寫本頁) ----1----- - - - - -----_ . 經濟部智慧財產局員工消費合作社印製 45 e7 (…. A7 _______B7__ 五、發明說明(11 ) , 向溶點焊料,Cu或Ni’且共鎔焊料20係具有如上所述之 抗疲勞性者》 當半導體元件10被安裝至印刷電路板12時,傳統組成 物之共錄焊料被作為用以使金屬域丨6連接至印刷電路板i 2 之墊18者。 於半導體元件10中,已參考第6圖描述之習知技藝, 其中金屬塊16係直接附接至於,例如,半導體晶片24活性 元件表面上形成之電極14 ’金屬塊16可由具有高於共錄焊 料者之炫點之金屬物料製得’諸如,高溶點焊料,Cu或州 ,且用以使電極14連接至金屬塊16之共鎔焊料2〇可為具有 如上所述之高抗疲勞性者。 於第7圖中’本發明之功效及比較例功效之比較實驗 資料被顯示’且第8圖顯示用於第7圖實驗之高溫焊料球, 其中參考編號40表示半導體元素;41係聚醯亞胺;42係金 屬柱(Cu) ; 43係共鎔焊料;44係高溫焊料球;45係接線圖 案;46係包覆物。 依據連接可靠性評估測試,其中如第8圖所示之半導 艘元件係接受熱沖擊。溫度循環係_4〇t至+125。(:。第7圊 之比較資料顯示1%之不可允許之產生於第8圖所示之本發 明半導體元件(第2或3圖)及第5或6圖所示之習知技藝之半 導體元件之循環。如第7圖所示,依據比較例(其中習知技 藝之共鎔焊料被使用)’發生CDF係約600周期。相反地, 依據本發明(其中高溫焊料塊被使用),發生Cdf係約900 周期。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 14 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------"' 五、發明說明(η ) .為主思,於第7圖所示之比較資料中,本發明係指使 用第1表中之',添加三種金屬之彈料·,且tt較例係指使用 傳統共鎔焊料。 因此’依據本發明,對熱沖擊具有高耐久性之半導體 元件可因而被獲得。 因為依據本發明之用以安裝半導體元件之結構金屬塊 係由具有南於共錄焊料者之溶點之金屬物料製得,其可於 女裝半導體7L件期間加熱時避免金層塊溶融及保持其原始 *度。因此’有利結果可於連接可靠性評估測試中獲得, 其中半導體疋件於安衆至印刷電路板之狀態中接受熱沖擊 。因為用於使金屬塊端部之任_者連接至半導體元件側或 印刷電路板侧上之共料料(其中t接受熱沖擊時諸如破 裂之f勞易產生)具有比其它用於另一端之連接之共錄焊 料更尚之抗疲勞性,其可改良整體之抗熱沖擊之耐久性及 達成高可靠性。 #者,依據本發料導體元件,因為金屬塊係由具有 2共紅焊料更高溶點之金屬物料製成,其於半導體元件被 安裝時不會藉由施加熱而炼融,以保持原始高度。因為用 於使金屬塊之端部連接於半導體元件之共鎔焊料(其中其 係依經驗認為諸如破裂之疲勞係易於接受熱沖擊時產生) 具有A用於使其它端部連接至印刷電路板惻上之其它共鎔 焊料更高之抗疲勞性.其可於半導體元件被安裝後增加對 抗所施熱沖擊之耐久性,造成高可靠性, …k項技藝者需瞭驊前述描述僅係有關所揭露發明 木 0 ” _ 如 J. f --~-~____ 一 -15 - 4 5 5 9 6(, A7 B7 五、發明說明(13 ) ' 之某些較佳實施例,各種變化及改良可在不偏離本發明精 神及範圍對本發明為之》 元件符號對照 10…半導體元件 32…電路圖案 12…印刷電路板 36…模樹脂 Η…電極 38···第二保護臈 16…金屬塊 40…半導體元素 18…墊 4卜··聚酿亞胺 20, 22, 43…共鎔烊料 42…金屬柱_ 24…半導體晶片 44…高溫焊料球 26…電極端子 45…接線圖案 28…鈍性膜 46…包覆物 30…絕緣保護膜 (請先閱讀背面之注意事項再填寫本頁) 策--------訂---------線' 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公复) 16
Claims (1)
- A8 B8 C8 D8 5 596 0 ^乜年I 六、申請專利範圍 第89105276號專利申請案申請專利範園修正本 修正曰期:90年4月 1. 一種用以使具有電極之半導體元件安裝於具有導體墊之安 裝基材上之安裝結構,該結構包含: 金屬塊,其使該半導體元件之該電極電連接至該導體 墊; 第一共錄焊料,其用於該金屬塊與該半導體元件之該 電極間之焊接: 第二共鎔焊料,其用於該金屬塊與該基材之該導體塾 間之焊接: 該金屬塊之熔點係高於該第_及第二共総焊料之溶 點’且該第一共錄焊料之疲勞抗性係高於該第二共錄焊料 之疲勞抗性。 2. 如申請專利範圍第丨項之安裝結構,其中該第一共嫁焊 料主要係由Sn組份及Pb組份組成,且亦由In組份' 处 組份、Ag組份及Cu組份之至少二者組成。 3. 如申請專利範圍第1項之安裝結構,其中該金屬塊係高 熔點焊料,Cu或Ni,其具有高於該第一及第二共鎔焊 料者之熔點。 4. 一種用於使具有電極之半導體元件安裝於具有導體墊 之安裝基材上之安裝結構,該結構包含: 金屬塊,其使該半導體元件之該電極電連接至該導 體墊; 第一共鎔焊料,其用於該金屬塊與該半導體元件之 該電極間之焊接; — 1 I ί - I I I I I I I ^--1!!! & (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製175. 6. 經濟部智慧財產局員工消費合作社印也取 4 5 5 9 B :;' &8 g 六、申請專利範圍 " ~ 第二共鎔焊料’其用於該金屬塊與該基材之該導體 墊間之焊接; 該金屬塊之熔點係高於該第一及第二共鎔焊料之 炫點’且3玄第二共録焊料之疲勞抗性係高於該第一共錄 焊料之疲勞抗性。 如申請專利範圍第4項之安裝結構,其中該第二共錄焊 料主要係由Sn組份及抑組份組成,且亦由^組份、外 組份、Ag組份及€:11組份之至少二者組成。 如申請專利範圍第4項之安裝結構,其中該金屬塊係高 溶點焊料,Cu或Ni,其具有高於該第一及第二共_ 料者之熔點。 7· —種半導趙元件,包含: 半導體構件,其具有形成電極之表面,於其上第一 電極端子及絕緣保護膜被形成; 線路圓案,其係於該保護膜上形成,如此’被電連 接至該第一電極端子; 金屬塊,其被藉由第二電極端子電連接至該線路圖 案; 共鎔焊料,其用於該金屬塊與該第二電極端子間之 焊接,該共鎔焊料具有高的抗疲勞性且係主要由如組 份與pb組份所組成,且亦可為由In組份、訃組份、Ag 組份以及Cu组份中之至少兩者所組成;及 該金屬塊之熔點係高於該共鎔焊料之熔點。 8. —種半導體元件,其包含: 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)184 5 59 A8 B8 § 六、申請專利範圍 半導體構件,其具有電極; 金屬塊’其係電連接至該電極; 共鎔焊料,其用於該金屬塊與該電極間之焊接,該 共鎔焊料具有高的抗疲勞性且係主要由S η組份及P b組 份組成’且其由卜組份、Sb組份、Ag組份及Cu組成組 成;及 着\ .\該金屬塊之熔點係高於該共鎔焊料之熔點。 9. 申請專利範圍第7或8項所述之半導體元件,其中 該焊料係由63質量%之Sn組份、34.3質量%之Pb組 份、1質量%之111組份、〇.7質量%之Sb組份及1質量%之 Ag組份所組成。 — — — — — — ^---- -----^---— II---I {請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印?衣 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 19
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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TW089105276A TW455960B (en) | 1999-03-24 | 2000-03-22 | Semiconductor device and mounting structure of a semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US6285083B1 (zh) |
EP (1) | EP1039527A3 (zh) |
KR (1) | KR100642229B1 (zh) |
TW (1) | TW455960B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4526651B2 (ja) * | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP3548082B2 (ja) * | 2000-03-30 | 2004-07-28 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
DE10114897A1 (de) * | 2001-03-26 | 2002-10-24 | Infineon Technologies Ag | Elektronisches Bauteil |
US6622380B1 (en) * | 2002-02-12 | 2003-09-23 | Micron Technology, Inc. | Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards |
US7276801B2 (en) | 2003-09-22 | 2007-10-02 | Intel Corporation | Designs and methods for conductive bumps |
KR100690245B1 (ko) * | 2005-04-06 | 2007-03-12 | 삼성전자주식회사 | 저융점 솔더를 이용한 솔더 접합 방법 및 이를 이용한 볼그리드 어레이 패키지의 수리 방법 |
US9706662B2 (en) * | 2015-06-30 | 2017-07-11 | Raytheon Company | Adaptive interposer and electronic apparatus |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6187396A (ja) * | 1984-10-05 | 1986-05-02 | 株式会社日立製作所 | 電子回路装置とその製造方法 |
JPS63211639A (ja) * | 1987-02-27 | 1988-09-02 | Hitachi Ltd | 電子回路装置の製造方法 |
US4938924A (en) * | 1990-02-16 | 1990-07-03 | Ag Communication Systems Corporation | Copper doping of eutectic solder |
CA2078538C (en) * | 1991-10-28 | 1998-10-06 | Boon Wong | Fatigue resistant eutectic solder |
US5616520A (en) * | 1992-03-30 | 1997-04-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and fabrication method thereof |
US5591941A (en) * | 1993-10-28 | 1997-01-07 | International Business Machines Corporation | Solder ball interconnected assembly |
US5907187A (en) * | 1994-07-18 | 1999-05-25 | Kabushiki Kaisha Toshiba | Electronic component and electronic component connecting structure |
JPH09270477A (ja) * | 1996-03-29 | 1997-10-14 | Sumitomo Kinzoku Electro Device:Kk | セラミック基板 |
US5761048A (en) * | 1996-04-16 | 1998-06-02 | Lsi Logic Corp. | Conductive polymer ball attachment for grid array semiconductor packages |
JP3201957B2 (ja) * | 1996-06-27 | 2001-08-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 金属バンプ、金属バンプの製造方法、接続構造体 |
JP3038644B2 (ja) * | 1996-07-17 | 2000-05-08 | 日本特殊陶業株式会社 | 中継基板、その製造方法、中継基板付き基板、基板と中継基板と取付基板とからなる構造体、その製造方法およびその構造体の分解方法 |
JP3719806B2 (ja) * | 1997-01-20 | 2005-11-24 | 日本特殊陶業株式会社 | 配線基板 |
US6002172A (en) * | 1997-03-12 | 1999-12-14 | International Business Machines Corporation | Substrate structure and method for improving attachment reliability of semiconductor chips and modules |
-
2000
- 2000-03-21 US US09/531,376 patent/US6285083B1/en not_active Expired - Fee Related
- 2000-03-21 EP EP00302289A patent/EP1039527A3/en not_active Withdrawn
- 2000-03-22 TW TW089105276A patent/TW455960B/zh not_active IP Right Cessation
- 2000-03-22 KR KR1020000014623A patent/KR100642229B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1039527A2 (en) | 2000-09-27 |
KR20000076932A (ko) | 2000-12-26 |
EP1039527A3 (en) | 2002-03-06 |
US6285083B1 (en) | 2001-09-04 |
KR100642229B1 (ko) | 2006-11-02 |
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