TW454281B - Method and apparatus for enabling conventional wire bonding to copper-based bond pad features - Google Patents

Method and apparatus for enabling conventional wire bonding to copper-based bond pad features Download PDF

Info

Publication number
TW454281B
TW454281B TW89106196A TW89106196A TW454281B TW 454281 B TW454281 B TW 454281B TW 89106196 A TW89106196 A TW 89106196A TW 89106196 A TW89106196 A TW 89106196A TW 454281 B TW454281 B TW 454281B
Authority
TW
Taiwan
Prior art keywords
layer
brush
patent application
applying
scope
Prior art date
Application number
TW89106196A
Other languages
English (en)
Inventor
Hugh Li
Diane J Hymes
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Application granted granted Critical
Publication of TW454281B publication Critical patent/TW454281B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B08CLEANING
    • B08BCLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B1/00Cleaning by methods involving the use of tools
    • B08B1/30Cleaning by methods involving the use of tools by movement of cleaning members over a surface
    • B08B1/32Cleaning by methods involving the use of tools by movement of cleaning members over a surface using rotary cleaning members
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B08CLEANING
    • B08BCLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B1/00Cleaning by methods involving the use of tools
    • B08B1/30Cleaning by methods involving the use of tools by movement of cleaning members over a surface
    • B08B1/32Cleaning by methods involving the use of tools by movement of cleaning members over a surface using rotary cleaning members
    • B08B1/34Cleaning by methods involving the use of tools by movement of cleaning members over a surface using rotary cleaning members rotating about an axis parallel to the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/038Post-treatment of the bonding area
    • H01L2224/0381Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48747Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7801Means for cleaning, e.g. brushes, for hydro blasting, for ultrasonic cleaning, for dry ice blasting, using gas-flow, by etching, by applying flux or plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8501Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/8501Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/85011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85203Thermocompression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • H01L2224/85207Thermosonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85375Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01072Hafnium [Hf]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

登明之領逾 屬化ίΓ明之領域係關於薄膜處理’尤其關於採用銅基金 匕技術之半導體積體電路的處理技術之領域。 知技術之描诚 以竹Ϊ ΐ造高級的半導體裝置時,銅(CU)開始取代紹(Α1) 、:為金屬化之材料。Cu已經變成受歡迎的材料,此乃由 H =比較時’ CU具有較低的電阻率與大幅改善的電致 遷移哥命之緣故。 -之标之一個問題包含原始氧化層形成於 氧化自由的空氣環境中,已經報導銅 鋼氧:内成長了2°埃;而在水中環境之内, H匕層在第-分鐘之内成長了50k。通常,這些原始氧 ς 7不被期望的。亦即,當銅區域在 地減少電導…,銅基冶被期望 控制與/或處理方法,係业型地用=特有的…先、環境 氧化層成長之影響力,控制緩和或至少限制 一個特定的問題領域,将Mm 入/輸出U/ο)連接至與其相關之封裝晶片作輸 銅基金屬化技術具有鋼焊墊蛵驗 aJ:T•墊。具體言之, 係由於銅焊墊上之相當厚的 此問題 -般而言’-條配線會如圖丨所示=成合長^ 4 5 4^81 五、發明說明(2) 1A,穿過係具有形成於毛細管尖端1〇5&之球體1〇2a之一條 (典型上是採用金(An)或A1)配線1〇 4a之一毛細管l〇la,係 位於一晶片焊墊103a之中心,且(現在參考圖1B)對著焊墊 1 0 3 b的面被押入。然後,一般而言,熱超音 (thermosonic)或熱壓縮(thermocompressive)能量係被施 加於毛細管尖端1 〇 5 b,以將球體1 〇 2 b予以黏著至焊墊 103b °如圖1C與1D所示,在球體丨〇2c被黏接至焊墊1〇3c之 後,毛細管101c移動至一封裝引線1〇6,於該處使得配線 104d隨後楔形接合至封裝引線丨〇6。 不幸的是’在標準的製程中,在球體1〇2&與焊墊1〇3a ( 接觸之前,一層原始氧化層(未顯示於圖1A)係形成於銅焊 墊1 0 3a之上。原始氧化層避免一種接合形成於配線與基本 銅焊墊之間。良好的接合典型地顯現出球體丨〇 2與焊墊1 〇 3 間之一種金屬間化合層。 如上述所探討的研究,原始氧化層係在施加球體丨〇 2 至焊墊103之前形成。典型上,標準的製程在半導體晶圓 之内連線構造之最後(或最高)之金屬化層後,立即形成焊 墊構造。在形成最後之金屬化層之後,金屬層係被拋光 (例如藉由化學機械拋光(CMp))至特定之厚度範圍。 f拋光之後’清洗半導體晶圓以從晶圓表面移除不必 要的微粒,大部分的微粒乃形成於先前的拋光步驟。形 於拋光後與清洗前之天然接合墊氧化層可能藉由清洗處理 而被移除’其乃取決於使用之清洗化學劑。在清洗之後, 半導體晶圓係被乾燥、測試、與切割。然後,每個的晶粒
第6頁 4 5 4¾ 8 1 五、發明說明(3) ___ 係被置放於一晶片搬運機,並在y線 在高溫下被環氧化成一晶粒封裝。接σ耘序開始之前, 上述之整個"後段清洗"製程導 一氧基環境中,並超過實質上的塾於室溫暴露於 此,在不將昂貴的複雜度引入至對二。因 :而",-種方法乃執行電漿蝕刻,然後、、心fi程〔舉 一種金屬膜配線層(例如Ni );緊拉—二况積相虽厚的另 二沉積層〕的情況下,難以备f者沈積鈀與/或金之第 墊上。 免原始氧化層成長於露出焊 因此,需要一種右 控制原始氧化層成長。P嚙成本的方法,以在銅焊墊上 【發明概要】 一種用以從—表$ # 5秒之内,開始塗敷一除一氧化層,然後在氧化層移除 明於下。此表面可处a蠖層至此表面之方法與設備係說 面。移除氧化層可人鋼表面,其可更包含一焊墊表 液。塗敷保護斧可採用包含擰檬酸酸或鹽酸之溶 之溶液,:中:二包含採用包含-氮二烯伍園族之成員 方法亦可更包含在園族成員可更包含BTA。上述 3 5秒。 °塗敷之後’完全地塗敷保護層持續 【較佳實施例之說明】 以下說明用以處理曰 处理Ba圓之方法與設備。於以下之說明
五、發明說明(4) 中,提出許多細節,例如:門 等。然而’對於熟習本項技4 J離、模型之型式 可能不在這些具體的詳細 ^理解到’本發明 !知之構造與裝置係以方塊圖顯示:非口:, 造,以避免將本發明模糊化。非顯不其坪s構 於一實施例中,製造能士兩/ + & 有權成本,係以說明於下之=技\鋼基金屬化技術之所 乃連續地氧化層形成,故說改良。因為銅 氧化層成長所導致之有害效^ 方法與設備可控制由 於一實施例中,晶圓之邀句 化層,然後開始塗敷一伴, μ 一表面移除一氧 執矣而梦、f層至此表面(例如銅表面、焊 4)。軋化層可能藉由採用擰檬酸 至此表面而移除。保護層可能藉由採用―種^液= 而被塗敷,其巾,溶液係為η文至此表面 H 例中,保護層係在氧化層移除之5秒内 被塗敷,並在在開始採用之後幾乎35秒完成。、 ^實㈣巾’塗㈣護層係藉^帛1子與被提 供 刷子之液體(例如一濕式化學劑)而執行。這種技術 係同等適合於线其他H實㈣巾,液 ==此層。於一實施例中,刷子可能為地設 计供刷子擦洗用之一晶圓處理系统之一邱 八% / :至刷子之核心部,以供經由刷子之化學;送 思到並非需要經由刷子之化學運二 乂 如刷子之上,藉以執行塗數動作。液體可施滴落至例 五、發明說明(5) 本發明之這些與其他實施例可能依據下述的教導而實 現’很明顯地,在不背離本發明之較寬的 =實 下,各種不同的修改與改變可能在以下的教 : ,,說明書與圖:係J視為例示性,而非 : 發明之範圍僅能參照申請專利範圍而論。 设巧 ^ 舉例而言’雖然探討以下係大部:針焊 到,本教導之較寬的範,可能被地理解 性的與/或不必要的氧化層形成所影響之1枯’”易文腐蝕 而言,磁性紀錄或磁光基處理同樣過屬^例:例 層沈積膜的成長。再者,於此昶道遭^到不必要的氧化 材料(除了銅以外)之半導體基處用於使用其他 或不必要的氧化層成長。又,於此之教以 封裝技術(除了弓丨線接合以外^教^可應用至其他 球形柵極陣列與引線柵極陣列技翁。1裝曰曰片技術、 焊墊係典型地於形成内連線金屬化 j。因此,最小量的破裂係在後CMp晶之主最後一層之後形 ^採用-種刷子洗㈣„ =驟之後, 除氧化層並沉積保護層。如果氧化製程中,以移 f ’係在測試晶圓之後或正好在引線接:與保護層塗敷方 會對整體製程導致最小數量的:JJ線接合之前被執行,亦 方法==7^^^,裝4清潔—晶圓之典型的 圖2顯不-例示的刷子洗條洗條裝置(亦 454^81 : \_ _丨丨 麵 ^_ _ 五、發明說明(6)^ ' " " 以系統表示)。洗滌洗滌裝置包含複數之站。每各該站典 型地表不在晶圓清洗處理中之一個或更多步驟。受污染的 晶圓(或基板)係於系統之一端被裝載,且乾淨與乾燥的基 板係從系統之另一端被卸載。亦即,受污染的基板係被裝 載進入一晶舟盒280,然後晶舟盒28〇被置於濕式傳遞索引 站210中。在晶舟盒280被置於濕式傳鸡索引站21〇之後, 基板係自動地從晶舟盒2 8 0被移除且一次一個地被置於外 部刷洗站2 2 0中。 於外部刷洗站2 2 0中,一基板係處理經由一第一洗 滌]一般而言,在第一洗滌期間’基板係被一種溶液(例 如氫氧化錢(N & Ο Η),H F或S C1)處理。此溶液係經由複數 之刷子221而被塗敷至基板。基板本身在複數之刷子221之 下可旋轉’以協助執行塗敷溶液。晶圓通常經由從刷洗站 之一端運送晶圓至另一端之硬體,並横越刷洗站2 2 〇, 2 30 〇 然後,洗滌的基板自動地從外部刷洗站22〇移除,且 被置於内部刷洗站2 3 0。大部分的洗滌洗滌裝置能於5秒内 或更短時間’從第一站運送晶圓至第二站。於内部刷洗站 2 3 0中’基板係經由一第二洗滌而被處理。又,在第二洗 梅期間,晶圓係受到另一種溶液(舉例而言,稀釋的i敗 酸(HF))之處理。如在第一洗滌步驟中,溶液係經由複數 之刷子2 31而被塗敷至基板上。在第二洗滌之後,基板接 著從内部刷洗站230自動地被移除且被置於沖洗、旋轉與 乾燥站2 4 0。基板係然後被運送至輸出站2 5 〇,接著被置於
第10頁 4 5 8 1 五、發明說明(7) 晶舟盒281中。 用來洗滌晶圓與塗敷各種不同的溶液之例示的刷洗設 備3 0 0係顯示於圖3。一種溶液係典型地為一種液體(例如 去離子(DI )水與酸)以上之混合物,圖3之實施例可經由供 應線3 1 0與3 2 0提供液體。各種不同的液體可能相繼地被塗 敷,亦即,一次塗敷一種;或者是同時塗敷。供應線3 i 〇 與320進入到運送管37〇。運送管37〇以預定的流動速率傳 送溶液進入刷子340之中空的核心部33〇。供應線31〇與 320係因此以流體之方式連通刷子核心部33〇。通常,當刷 子340上之溶液飽和時,其係藉由旋轉裝置36〇而旋轉。 旋轉裝置360驅動刷子34〇以順時針(反時針)方式旋轉, 經由插槽或開孔350塗敷溶液至基板。因為刷子34〇 係與晶圓接觸之溶液係被塗敷至基板。關 於刷子擦洗技術之更詳細之細節可從美國專利第 半導體基板之方法V設備』 吏用氫氟酸(HF)清洗 備,Lt加ϊ ΐ ί::二::之核心部之其他刷子擦洗設 咖子,其因此’這種設備亦採用 之設備型式為何(田奸=士二、、敷,谷液至晶圓。不管所採用 鋒液體至一刷子疋或〜由一刷子流動液體之系統,抑或是 子塗敷液體之設備表曰_曰圓 糸統),兩者都可能以一刷 潤濕之故。 不,此乃因為刷子係被兩系統之液體 以下之探討說明 可採用各種不同的方法與設備,以處
4 5 4^ 8 1 五、發明說明(8) 理一個或更多問題’例如產生於半導體丨C之銅焊墊上之氧 化層形成問題。一般而言,參見圖4,原始氧化層4〇 j係首 先從焊墊40 2被移除(如圖4A與4B所示),然後,一保護層 403立即(亦即,在5秒或更短時間之内開始)形成於焊墊 402上(如圖4C所示)。因為保護層覆蓋焊墊,故其避免原 始氧化層形成在運送與下游處理期間(例如測試、切宝、 熱回火等)。再者,保護層係設計成使配線接合部4〇4°在 其接合時,可能經由保護層而接合至銅焊墊(如圖4D與鈍 所示)。如此,保護層亦並不大幅地阻礙形成於配線接合 =銅焊墊之間的接合之完整性。保護層係因此為原 化層形成之阻絕,此可允許引線接合。 厘译ίΐΐ免原始氧化層形成於焊塾上,保護層具有足夠 旱又/、枪度以適當地避免氧環境與銅作 化声成:勒:之程度)。因11匕’厚度與密度具有由氧 定之第二界限。 帛界限與由弓1線接合動態所決 層之層ΐ與黏著劑與/或阻障層不同。黏著劑 屬膜配〖μ例如接合部之前沉積於鋼焊墊上之前述金 配線接合部本身之間之過渡2。::劑:係為在銅焊墊與 S’其最終促進配線接合部之整體機 運接至曰曰拉。然而,因為黏著劑層係慎重地被使用以
第12頁 4 5 8 1 -_Zk.___^____ 五、發明說明(9) 避免在銅焊墊與配線接合部間之直接接觸,故其必須能導 電。在不橫越黏著劑層之情況下,黏著劑層使電流並不直 接從焊墊流動至配線接合部,或從配線接合部流動至焊 塾。 比較而言,於此所探討之保護層係設計成藉由引線接 合處理而被打孔貫通。因此,在配線接合部與傳導焊墊之 間存在有某些直接接觸。因此,關於保護層,電流可能或 無法流經保護層’此乃因為至少某些電流直接從焊墊流動 至配線接合部,或從配線接合部流動至焊塾。 ,如所探討的内容,在最後的金屬化及與其相關的拋光 之後,晶圓係典型地更受到清洗、乾燥、測試、切判與熱 回火。在切割個別的晶片之後,每一個係典型地被7/置二 ^晶片搬運機,然後,在引線接合之前被環氧化至1封、 ,、。原始氧化層可能被移除,且保護層可在前述^ —被塗敷至任何地方。舉例而言’在測試之後,曰二 受到-氧化層#除步,驟’接著是一保護層塗敷可肊 备如上所探討的,原始氧化層急速地形成於山 氧(例如空氣或水)之環境之銅上。因此,^出於包含 —旦原始氧化層被移除,應儘可能快速塗=雜環境下, 少原始氧化層再成長。X,原始氧化層可处於護層,以減 /或低壓環境下被移除。若缺乏環境中之氧%; 一種無氧與 =法成I,允許在移除原始氧化層與’ ^原始氧化 韦的延遲時間(設置於維持無氧一段延遲保噢層之間較 如前所探討的,移除氧化層步驟與/之環境)。 笙敷保護層可能
五、發明說明(10) 以任Ί習知技術之方法(例如 成 3之說明:作為移除氧化層與塗敷保護層參考圖2與 包含經由洗條刷子塗敷溶液之至少義可能 之旋轉速度(亦即,刷子速度) ^數· 1 )刷子 子力量),其乃與刷子超過曰;)圓之2)/;子二剪力(亦即,刷 型/形狀典型地相關;3 )用以在“ G ^刷毛之類 之速度(亦即,滾轉速度);4) 一曰疋轉日日圓之滾轉 =,處理時間);5)被塗敷;曰複數= = :速率(亦即,流動速率);6)溶液組成物與 液之各種不同的濃度;最後是7)溫度。、塗敷之特有洛 時間=二!:::=而!,滾轉速度與晶圓處理 轉速度與晶圓處理時間,係於=數目。說明於此之滾 塗敷將移除鋼原始氧化層與 :以=積一薄膜層(例如保護層)至:=子擦Τ 之形成”4 :::: 超薄層(例如2°埃或更薄) 然而,如剧所論’可能改變製程以獲得厚度在 ^54^81 五、發明說明(11) 2 0k上下之層。又,超薄層係以—種濕式化學處理(亦即, 採用液體至一晶圓處理)建立。一般而言,濕式化學處理 (例如喷灑或洗滌)產生微米級之薄膜厚度。因此,在一刷 子擦洗系統之内使用一刷子作為塗敷材料層之裝置具有複 數之獨特貢獻。與此相符的是,圖2之設備亦可被視為只 是一種對於一刷子擦洗系統之刷洗系統。 於大部分的狀態下,晶圓在CMp之後需要清洗(使用上 述之刷子洗滌洗滌裝置)。氧化層移除與保護層塗敷步驟 可能在此晶圓清洗步驟之後立即採用。於此實例中,晶 可能在它們從輸出晶舟盒281被移除之後立即重新置入至 晶圓輪入晶舟盒280 (簡要地參見圖2)(此系統已經正 行後CMP晶圓清洗)。X ’目前之工業趨勢係整合⑽拋 =與刷洗*統。整合之*統可或無法禁止日日日圓刷洗先 再使用(取決於刷洗站輸入晶舟盒之存取能力)/旲一 ^ 的刷子擦洗之使用,分離式獨立刷子洗 “洗滌裝置可此被採用以實現前述之方法。於 此杏, 二中’如前所述’氧化層移除與保護層塗敷可;二^ 其他製造階段中,例如正巧在晶圓測試之後於 接合之前或在包含這些處理步驟之重做週期線 他可能的實施例中,可能需要在最高的金屬液面’其 一或第二金屬層)之下鈍化銅之金屬化。 ^第 以作這種塗敷方式。 發明亦可被用 原始氧化層必須在塗敷保護層之前被移。 層可能藉由不同的化學溶液而移除。通常_化 纖或其他溶液 第15頁 4 5 4^8 1 玉、發明說明(12) 係於DI水中稀釋。舉例而言,於DI水中具有濃度〇. 2%與 .0之ph值之擰檬酸酸,於DI水中具有濃度〇· 1%之鹽酸、 (HC1),於DI水中具有濃度0.2%之蘋果酸,或於DI水中具 濃度之丙二酸皆可使用,其中,濃度種類係為重量 ^度等級。再者,每一個濃度等級可能隨著例如待移除之 佑ϊ ΐ ί厚度或期望之處理時間而改變。因此’其範圍分 少廣如0. 0 0 5%至〇. 5%的檸檬酸、蘋果酸與丙二酸, ::可使用o.01m2%iHcl。再者,上述之任一種溶液可 1 ^ = 一步地缓衝(亦即,亦增加)100 ppm以成0.2%的氫 其他用以移除氧化層之習知溶液亦可採用。 清洗=與溶液流動速率,可能為目前在標準的晶圓 50Π處1例如處理時間為35秒且溶液流動速率為 a ^ η所採用之典型數值。一般的觀念係為晶圓膺遭 液一段足夠時間,以實質上移除氧it = 之Ϊ =化層之ΐ之材料導致損壞過度蚀刻效應與晶圓 ^此種指導方針亦延伸至上述的酸性濃产箄
:應::至言,較㈡L 能代表那些用來作氧數'轉速度與力量可 rpm、40 rPm與2.5 lbs。x f參數,例如分別是12〇 係適♦的接彳址、 ’這些參數之各種不同的範圍 化層)或太過腐蝕性(導致a n ^動(導致蝕刻不足的氧 從室溫至5 0度之?=;:【f特徵損壞)。溫度可能是 又氧化層移除與溫度之關係一般 第16頁 1 4 5 4^8 > 五、發明說明(13) 而言是:溫度越高移除迷率越大。 在移除氧化層之後,塗敷保護層。然而,在探討使用 於刷洗站之内以塗敷此層之特有的製程參數之前,關於運 送晶圓之動態之簡短探討將是有益的。如所探討的,於銅 上之原始氧化層具有很積極成長速率。本質上,在有氧之 環境下(例如在刷洗站内之自由空氣環境),氧化層開始在 它們被清潔之後立即成長。如此,理想上是可使在移除敦 化層與塗敷保護層間之時間最小化。如所探討的,大部分 的洗滌设備能於5秒以内,將晶圓從第一站運送至第二 站、。一般而言,可達成的最快運送時間應被採用。根據經 驗法則,運送時間應該消耗5秒以内。然而,如前所述, 此時間期可能取決於殘留於表面上之钱刻齊丨之數量而延 伸0 於一洗滌系統中,在晶圓下之硬體上,晶圓從第一 (亦▲即’氧化層移除)刷洗站2 2 〇水平地移動至第二(亦即, 保護層塗敷)刷洗站2 3 0 (簡要參照圖2)。亦即,告曰圓 第-站220移動至第二站23。時,晶圓表面係垂直:曰曰重圓:之 =向。又,因為晶圓係典型地"正面朝上"(意味著此置 i Ϊ f Ϊ係面對洗務洗務裝置之上部的刷子),且因為刷 曰糸在日日圓被運送至第二站之前,從晶圓表面被移除.告 日曰圓從第-刷洗站移動至第二刷洗站日夺,氧化層移除溶: 上、。St用一於第一刷洗站之溶液)之塗佈殘留於晶圓表面 适具有一種有利的效果,此效果將說明於下。 如果當晶圓離開此站時’複數之刷子殘留於晶圓表面
第17頁 五、發明說明(14) 上,則氧化層移除溶液將從晶圓上被抹 溶液從複數之刷子終止流動的狀態下更是举’特別是如果 從表面被擦拭掉,則複數 2 =如果溶液 中,立即導致不受期望的氧化層成長會=於2大氣 圓開始離去之前,特定的洗務系統(例如來自為^在晶 之SynergyTM刷子洗滌洗滌裝置)在第一 rak糸統 數之刷子,使晶圓未被擦拭乾淨,在晶J圓先站中僅升高複 氧化層蝕刻溶液之保護''膠泥(puddie)f表c-層 滌站間運送之期間會阻礙氧化層形成。 /、在aa圓於洗 因此,需要於晶圓表面上殘留惫 因為其在氧化層移除與保護層塗敷 液,此乃 移除,則保護層應儘快或儘可 ^二時—旦氧化層被 層應在氧化層移除步驟的5秒之内被H —般而言,保護 設定應被設定成以在各站間運送 因此,設備之 應提供某種超過此時間之裕声。θ日圓'疋蝕刻劑之膠泥 另一種可選擇的方法θ 移除溶液與保護層溶液兩;都可站J内’氧化層 移除溶液係首先以一第一 、主敷。亦即,氧化層 一站刷子促使保護層溶二被塗敷,然後以相同的第 第二站,⑪此種方法簡。因為晶圓並不需要通過 敷與保護層溶液之塗敷間=2。再者,在移除溶液之塗 圓從第一洗條站運送至序’不再受限於對應於將晶 繼續以"兩個站"之站之硬體。 之方法作為例子說明,一旦晶圓進λ 45m81
五、發明說明(15) 以:站,-種溶液立即被塗敷(經由複數之刷 :至Π墊表面之後,轉換成-種固態的、穩定的保; 2 1亦可以一薄膜表示。一般而言,溶液化學係包含 唑(ΒτΤη伍:私之複數成員。一氮二烯伍圜(例如苯並三 f(BTA)),係被熟知以提供對抗於銅上之複數原始氧化層 成長之保濩。BTA係為目前最廣泛地被使用於銅的保護 $,且其係為用來避免銅氧化層之多數商業上可利用的溶 液之主成分(例如來自應用化學科技股份有限公司
Applied Chemical Technologies, inc )之St〇p〇xTM)。 其他被使用以作為避免銅氧化層之一氮二烯伍圜包含引 唑、苯並咪唑、引朵(Indole)與甲基苯並三唑。再者,因 為P C基板(P c B )技術採用複數之鋼内連線,故基於三氮二 烯伍圓與咪唑(使用於PCB製程之〇rganic it;
Pservatives (OSPs))之保護層化學劑亦可使用。 依據一種化學反應’BTA舆其他之一氮二烯伍圜會形 成一保護層。在化學反應之前,純BTA (或稀釋的BTA溶 液)係處於一種液體狀態。然而,在暴露至銅時,於銅上 導致一種固體保護薄膜之化學反應之生成物。微粒係為固 相(包含高分子)之任何物質。這些微粒形成保護層。關於 BTA,化學反應係通常表示為:
Cux0 + BTA/H — [Cu-BTA]n + H20 (方程式1) 其中’ [Cu-BTA]n係為固態的薄膜材料,而cUx〇係被認 為是起因於Cu與分解的〇2之反應。 如所探討的,保護層之厚度可具有需要實質上避免更
第19頁 q 1 — —-- 五、發明說明(16) 進一步的氧化層成 = 透明性之最高界限界限,與需要維持接合製程之 數(例如頻率咬日寺π / σ又的接合所需要之特有接合參 之保護層厚度二合工f製造心^ 層厚度(或厚度變化)& _ = ^發一般而言,可能隨著保護 各種不同的接合工而需要更多的接合能量。因為 其他參數),所以二Λ 更多或更少能量(與/或改變 之特有接人工具 層厚度之上部接合可取決於所採用 f最/界限’ ΒΤΑ保護層的成果係關於另一種重要
層專”了厚度以外):密度。高度多孔性的ΒΤΑ之J r :疋一種不可接受的保護層’此乃因為氧將ΒΤΑ膜中之 左由毛細孔而與銅焊墊接觸。因此,密集的(亦即,低多 ==)BTA之薄膜係為期望的。薄膜多孔性係與所採用 筮佈技術(例如所使用之刷子型式、刷子速度、流動速率 寺)相關。一般而言,在整體晶圓表面上促進BTA覆蓋範 圍’而非有斑點的或有污點的覆蓋範圍之技術係會減少 孔性。 . 夕 與此相當的是,BTA薄膜密度係與溶液中之BTA浪度相 關。一般而言’較高的BTA濃度傾向於在晶圓表面上提&供 較好的BTA覆蓋範圍,以產生較密集的薄膜。較高的βΤΑ渡( 度亦產生較厚的薄膜,此乃因為表示於方程式1中之反應 可得到更多BTA。因此,較高程度的BTA濃度產生較大厚度 (不被期望的)之密集的薄膜(期望的)。 a 為了利用較高的B T A濃度之益處(亦即,多密集的薄
81 ----- 五、發明說明(17) 能)損JV寺降低或甚至使較高BTA濃度(亦即,厚薄膜)之潛 應心f小化’ BTA塗佈均勾性應受到控制。因此,不僅 2 2 進ΒΤΑ覆蓋範圍(亦即,確保至少最小數量的ΒΤΑ 個晶圓表面上)之技術,所採用之技術亦應促 量之_ / (亦即,使整個晶圓表面上之ΒΤΑ覆蓋範圍之數 置之變化最小化)之均勻性。 伴持2個晶圓表面上之濃縮ΒΤΑ之均句塗佈,係有助於 下、持:度變薄,同時確保密集的薄膜,此現象將探討於 數薄腹Ζ ί持可接焚的密度程度,未顯現良好均勻性之複 的ΒΤΑ::於需要較高的ΒΤΑ濃度。高濃縮溶液之非均句 的薄膜覆區^範^吏某些晶圓區域露出至大量之ΒΤΑ(產生厚 ^ m ",並使其他晶圓區露出以調變ΒΤΑ之數量(產生 在。;,薄狀 與較薄二it ,因為bta濃度高,故較厚 =么薄膜區域傾向於阻礙以引線接合】;=長’ 因此,成功地塗敷一保護層薄膜,係取 目標BTA薄膜厚度(小於或等於2〇k) 、、〜曰; 性綱濃度等級與製程參數之組合。 主要經由確保包含BTA之溶液之均 /圍 ;高=圓與刷子旋轉速度,可達成均^的^達液成塗佈错由 又刷子之形狀會影響均句性。舉例而言,與具有小節塊 第21頁
(nodule)之刷子比較而言,平的刷子可導致更整體的與 部的溶液均勻性。 局 於實施例中’ 一保護層塗敷製程係以下述條件實 現:於DI水中5 0 0ppm之BTa濃度與7〇之汕值;5〇〇 c c / m i η之溶液流動速率;一個具有小節塊之刷子與1 2 〇 pm之刷子速度,4〇 rpm之滾轉速度;3$秒之晶圓處理時 ,,1/ 5 lbs之刷子力量,與25 t之溫度,導致可接受之 密集薄膜,此薄膜厚度係橫越過整個晶圓的總厚度而在 1 5-20埃間改變。保護層厚度之最小界限係可滿足,此乃 因為其係足夠厚以避免氧化層形成。再者,因為薄膜係足( 夠薄以促使引線接合,故可滿足最大界限。 在另一個實施例中,一保護層塗敷製程係以下述條件 實現:於DI水中i 〇0ppm之BTA濃度與7. 〇之汕值,5〇〇 cc/min之溶液流動速率;一個轉速為139 rpm之平刷子; 40 rp曰m之滚轉速度;35秒之晶圓處理時間;丨.5 ibs之刷 子力量與25 t之溫度,導致可接受、15埃之密集薄膜,此 薄膜厚度係橫越過整個晶圓的厚度作小幅改變。 於上述兩實施例中’在測試樣品之高溫硬化期間,非 實質的氧化層成長(10-40埃)係產生於]gTA層之下。 最後,如所探討的’氧化層之移除與保護層之塗敷並( 不需要需要刷子擦洗設備。此製程在最後的(:^?晶圓清潔 步驟之後亦不需要立即執行。舉例而言,氧化層可能藉由 浸泡(例如洗滌)製程或藉由喷灑製程而被移除。 a 洗務包含完全地將晶圓浸泡於一種氧化層蝕刻劑溶液
1 五、發明說明(19) 一 :之ΪΪ之=、濃度、溫度與授 ,常與洗條洗條裝置系心使= ί從決於溶液之濃度與採取的= 所熟知,所以具體的製程參數可輕易地決定、。技-者 而移二,二上:八氧化層可能藉由-種酸液噴灑動作 灑動作相ΪΪ作:3以一種蝕刻劑溶液噴灑晶圓。虚喷 ,麗動作相關的製程參數包含:溶液 /、赁 J線流動速率,喷灑角⑨,喷灑溶液中ΐ:产,、時門:液 灑之氧化層移除=為 保護層亦可藉由除數亦可輕易地決定。 製程包含:浸泡(例如洗條):2 :塗5。這些 轉塗佈包含時間、旋轉 貫質上相同的參數。旋 者,因為藉由這此方法之:數:動速率與溶液濃度。再 藝者所熟知之技;,因;;之塗敷係為熟習本項技 易決定。 b ”體的製程參數亦可同樣地被輕 非製=在統以外之處理技術(而且除 在氧化層被移除之後塗;in:呆儘可能的 好的經驗法則。再者,亩者,在5和之内係為一種良 飿刻劑殘留於晶圓表面h 許氧化層 應可同樣地擴充在氧化層移除 第23頁 464^81
第24頁 斗5續8 1 _____ 圖式簡單說明 本發明之說明係為舉例性說明,並未限制於附圖中, 類似的參考數字表示類似的元件,其中: 圖1 A至1 D顯示一種典型的引線接合製程。 圖2顯示刷子擦洗系統之一例。 圖3顯示使用於圖2之刷子擦洗系統内之刷子之一例。 圖4A至4E顯示一種用以形成接合至一銅表面之配線之 方法。 【符號之說明】 101a、101c〜毛細管 102、 102a、102b、102c~ 球體 103、 103a、103b、103c〜焊墊 1 0 4 a、1 0 4 b ~ 配線 105a、105b〜毛細管尖端 106〜封裝引線 210〜濕式傳遞索引站 2 2 0〜第一刷洗站 2 2 1 ~刷子 2 3 0〜第二刷洗站 231〜刷子 2 4 0〜沖洗、旋轉與乾燥站 2 5 0 ~輸出站 2 8 0〜晶舟盒 2 8 1〜晶舟盒
4 5 8 1 _2_ 圖式簡單說明 3 0 0〜刷洗設備 3 1 0、3 2 0 ~供應線 3 3 0〜核心部 3 4 0〜刷子 3 5 0〜開孔 360〜旋轉裝置 370〜運送管 401〜原始氧化層 4 0 2 ~焊塾 4 0 3〜保護層 4 0 4〜配線接合部
第26頁

Claims (1)

  1. 4 5 8 1 i 案號 89106196 修 Μ 月 修正 六、申請專利範圍 wTa 包含以 a) b) 表面。 2. 含一銅 3. 包含_ 一 4. 層之步 5. 層之步 6. 層之步 液。 7. 伍圜族 8. 在開始 9. 包含: 塗 以 1. 一種可使習用引線接合達成銅基焊墊特色之方法 下步驟: 從一表面移除一氧化層;以及 在移除該氧化層5秒之内,開始塗敷一保護層至該 如申請專利範圍第1項之方法,其中,該表面更包 表面。 如申請專利範圍第2項之方法,其中,該銅表面更 焊墊表面。 如申請專利範圍第1項之方法,其中,移除該氧化 驟更包含塗敷含有檸檬酸酸之一種溶液至該表面。 如申請專利範圍第1項之方法,其中,移除該氧化 驟更包含塗敷包含鹽酸之一種溶液至.該表面。 如申請專利範圍第1項之方法,其中,塗敷該保護 驟更包含塗敷包含一氮二烯伍圜族之成員之一種溶 如申請專利範圍第6項之方法,其中,該一氮二烯 成員更包含BTA。 如申請專利範圍第1項之方法,其中,該保護層係 之後35秒完全地塗敷。 一種可使習用引線接合達成銅基焊墊特色之方法, 敷一液體至一刷子; 該刷子塗敷該液體至一半導體晶圓表面;以及
    第27頁 1 1 案號89106196 年 月 日 修正 _ 六、申請專利範圍 藉由在該液體與該半導體晶圓表面之間之化學反應, 於該半導體晶圓表面上形成一層。 1 0.如申請專利範圍第9項之方法,其中,該層之厚度 係為2 0埃或更薄。 . 11.如申請專利範圍第9項之方法,其中,該半導體晶 圓更包含具有敷塗金屬之半導體晶圓。 1 2.如申請專利範圍第9項之方法,其中,該半導體晶 圓表面更包含一焊墊表面。 1 3.如申請專利範圍第9項之方法,其中,該刷子係為 [ 一晶圓刷子擦洗系統之一部份。. 1 4.如申請專利範圍第9項之方法,其中,該層更包含 一保護層。 1 5.如申請專利範圍第1 4項之方法,其中,該保護層 更包含一氮二烯伍圜族之成員。 1 6.如申請專利範圍第1 5項之方法,其中,該一氮二 烯伍圜族成員更包含BTA。 1 7. —種可使習用引線接合達成銅基焊墊特色之方 法,包含: < a ) 以位於一刷子系統中之一第一刷子塗敷一第一液 體,而從一晶圓表面移除一第一層;以及 b) 以位於該刷子系統中之一第二刷子塗敷一第二液 體,而塗敷一第二層至該晶圓表面,該第二液體係與該晶 圓表面作用以形成第二層。 · 1 8.如申請專利範圍第1 7項之方法,其中,該第二層
    第28頁 ^5ή^81 > 案號 89106196 年 月 日____ 六、申請專利範圍 之厚度係為2 0埃或更薄, 1 9.如申請專利範圍第1 7項之方法,其中,該第一層 更包含一氧化層。 2 0.如申請專利範圍第1 9項之方法,其中,該第一液 體係為一種溶液。 2 1.如申請專利範圍第2 0項之方法,其中,該溶液包 含檸檬酸酸。 2 2.如申請專利範圍第20項之方法,其中,該溶液包 含鹽酸。 2 3.如申請專利範圍第1 7項之方法,其中,該第二層 更包含一保護層。 2 4.如申請專利範圍第23項之方法,其中,該保護層 更包含一氮二烯伍圜族之成員。 2 5.如申請專利範圍第24項之方法,其中,該一氮二 烯伍圜族成員更包含BTA。 2 6.如申請專利範圍第1 7項之方法,其中,該半導體 晶圓更包含具有敷塗金屬之半導體晶圓。 2 7.如申請專利範圍第26項之方法,其中,該半導體 晶圓更包含一焊墊。 2 8.如申請專利範圍第27項之方法,更包含經由該第 二層塗敷一接合劑至該焊墊。 2 9.如申請專利範圍第1 7項之方法,其中,該第一刷 子與該第二刷子係為相同的刷子。 3 0. —種可使習用引線接合達成銅基焊墊特色之設
    4 5 βΊ 案號89106196 年 月 日 修正__ 六、申請專利範圍 備,包含: 一供應線,其乃被配置以塗敷一液體至一刷子,該刷 子係位於一晶圓之表面上方,該刷子係被使用以於晶圓表 面上,以液體形成一層。 31.如申請專利範圍第30項之設備,其中,該液體更 包含一氮二烯伍圜族之成員。 3 2.如申請專利範圍第3 1項之設備,其中,該液體更 包含Β Τ Α。 3 3.如申請專利範圍第3 0項之設備,其中,該刷子係 位於一刷子系統之一洗務站之内。/ 3 4. —種可使習用引線接合達成銅基烊墊特色之方 法’包含: a. 以位於一刷子系統之一第一刷子塗敷之一第一液 體,從一晶圓表面移除一氧化層層; b. 以位於該刷子系統之一第二刷子塗敷之一第二液 體,塗敷一保護層至該晶圓表面,該液體係與該晶圓表面 作用以形成第二層;以及 c. 藉由穿過該·保護層塗敷一接合劑至晶圓表面。 3 5.如申請專利範圍第34項之方法,其中,該晶圓表 面更包含一銅焊墊。 3 6.如申請專利範圍第34項之方法,其中,該第二溶 液包含一氮二婦伍圜族之成員。 3 7.如申請專利範圍第36項之方法,其中,該第二溶 液更包含Β Τ A。
    第30頁
TW89106196A 1999-03-31 2000-03-31 Method and apparatus for enabling conventional wire bonding to copper-based bond pad features TW454281B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/282,596 US6358847B1 (en) 1999-03-31 1999-03-31 Method for enabling conventional wire bonding to copper-based bond pad features

Publications (1)

Publication Number Publication Date
TW454281B true TW454281B (en) 2001-09-11

Family

ID=23082214

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89106196A TW454281B (en) 1999-03-31 2000-03-31 Method and apparatus for enabling conventional wire bonding to copper-based bond pad features

Country Status (7)

Country Link
US (2) US6358847B1 (zh)
EP (1) EP1186022A2 (zh)
JP (1) JP2002540631A (zh)
KR (2) KR100731850B1 (zh)
AU (1) AU3867700A (zh)
TW (1) TW454281B (zh)
WO (1) WO2000059029A2 (zh)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413576B1 (en) * 1998-10-05 2002-07-02 Kulicke & Soffa Investments, Inc. Semiconductor copper bond pad surface protection
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US6432826B1 (en) 1999-11-29 2002-08-13 Applied Materials, Inc. Planarized Cu cleaning for reduced defects
US6790757B1 (en) * 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
US7351353B1 (en) * 2000-01-07 2008-04-01 Electrochemicals, Inc. Method for roughening copper surfaces for bonding to substrates
US7220322B1 (en) 2000-08-24 2007-05-22 Applied Materials, Inc. Cu CMP polishing pad cleaning
DE10064691A1 (de) * 2000-12-22 2002-07-04 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiter-Chip und Kupferleiterbahnen auf dem Chip sowie ein Verfahren zu seiner Herstellung
US6693020B2 (en) * 2001-03-12 2004-02-17 Motorola, Inc. Method of preparing copper metallization die for wirebonding
US6783432B2 (en) 2001-06-04 2004-08-31 Applied Materials Inc. Additives for pressure sensitive polishing compositions
TW583348B (en) * 2001-06-19 2004-04-11 Phoenix Prec Technology Corp A method for electroplating Ni/Au layer substrate without using electroplating wire
JP3761461B2 (ja) 2001-12-13 2006-03-29 Necエレクトロニクス株式会社 半導体装置の製造方法
TWI221026B (en) * 2002-12-06 2004-09-11 Nat Univ Chung Cheng Method of thermosonic wire bonding process for copper connection in a chip
MY134318A (en) * 2003-04-02 2007-12-31 Freescale Semiconductor Inc Integrated circuit die having a copper contact and method therefor
US6881437B2 (en) * 2003-06-16 2005-04-19 Blue29 Llc Methods and system for processing a microelectronic topography
US6969638B2 (en) * 2003-06-27 2005-11-29 Texas Instruments Incorporated Low cost substrate for an integrated circuit device with bondpads free of plated gold
US7919864B2 (en) * 2003-10-13 2011-04-05 Stmicroelectronics S.A. Forming of the last metallization level of an integrated circuit
US7105379B2 (en) * 2004-04-28 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Implementation of protection layer for bond pad protection
US7210988B2 (en) 2004-08-24 2007-05-01 Applied Materials, Inc. Method and apparatus for reduced wear polishing pad conditioning
JP4035733B2 (ja) * 2005-01-19 2008-01-23 セイコーエプソン株式会社 半導体装置の製造方法及び電気的接続部の処理方法
DE102005033469B4 (de) 2005-07-18 2019-05-09 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleitermoduls
DE102005034485B4 (de) * 2005-07-20 2013-08-29 Infineon Technologies Ag Verbindungselement für ein Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterleistungsbauelements
TW200720493A (en) 2005-10-31 2007-06-01 Applied Materials Inc Electrochemical method for ecmp polishing pad conditioning
DE102006044691B4 (de) * 2006-09-22 2012-06-21 Infineon Technologies Ag Verfahren zum Herstellen einer Anschlussleitstruktur eines Bauelements
US20090008796A1 (en) * 2006-12-29 2009-01-08 United Test And Assembly Center Ltd. Copper on organic solderability preservative (osp) interconnect
SG177212A1 (en) * 2008-06-20 2012-01-30 United Test & Assembly Ct Lt Copper on organic solderability preservative (osp) interconnect and enhanced wire bonding process
TWI452640B (zh) * 2009-02-09 2014-09-11 Advanced Semiconductor Eng 半導體封裝構造及其封裝方法
DE102009029577B3 (de) * 2009-09-18 2011-04-28 Infineon Technologies Ag Verfahren zur Herstellung eines hochtemperaturfesten Leistungshalbleitermoduls
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
TWI467675B (zh) * 2011-04-25 2015-01-01 Air Prod & Chem 用於改善打線製程的引線架清潔方法
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
US9565770B2 (en) * 2012-08-08 2017-02-07 Marvell World Trade Ltd. Methods of making packages using thin Cu foil supported by carrier Cu foil
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
US9012263B1 (en) * 2013-10-31 2015-04-21 Freescale Semiconductor, Inc. Method for treating a bond pad of a package substrate
JP6937283B2 (ja) * 2018-09-19 2021-09-22 株式会社東芝 半導体装置の製造方法
US11682641B2 (en) 2020-08-13 2023-06-20 Microchip Technology Incorporated Integrated circuit bond pad with multi-material toothed structure

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS531654A (en) 1976-06-28 1978-01-09 Furukawa Electric Co Ltd Method of preventing oxidation of copper member
US4370173A (en) 1981-05-15 1983-01-25 Amchem Products, Inc. Composition and method for acid cleaning of aluminum surfaces
US4871422A (en) 1987-01-27 1989-10-03 Olin Corporation Etching solutions containing ammonium fluoride and anionic sulfate esters of alkylphenol polyglycidol ethers and method of etching
JPH02130922A (ja) 1988-11-11 1990-05-18 Toshiba Corp 半導体基板エッチング装置
DE3939661A1 (de) 1989-11-30 1991-06-13 Wacker Chemitronic Verfahren zur steuerung des einbaues von kupfer in siliciumscheiben beim chemomechanischen polieren
WO1993010277A1 (en) 1991-11-20 1993-05-27 Electrochemicals, Inc. Improved method for bonding copper to a polymeric material
WO1994027314A1 (en) 1993-05-13 1994-11-24 Interuniversitair Microelektronica Centrum Method for semiconductor processing using mixtures of hf and carboxylic acid
JPH07147300A (ja) 1993-11-24 1995-06-06 Hitachi Ltd インナーリードボンディング装置
JPH08250635A (ja) * 1995-03-14 1996-09-27 Dainippon Printing Co Ltd リードフレームの製造方法
DE19525521B4 (de) 1994-07-15 2007-04-26 Lam Research Corp.(N.D.Ges.D.Staates Delaware), Fremont Verfahren zum Reinigen von Substraten
DE4444388A1 (de) 1994-11-28 1996-05-30 Atotech Deutschland Gmbh Verfahren zum Bonden von Drähten auf oxidationsempfindlichen, lötbaren Metallsubstraten
JPH08195369A (ja) 1995-01-13 1996-07-30 Daikin Ind Ltd 基板の洗浄方法
US5662769A (en) 1995-02-21 1997-09-02 Advanced Micro Devices, Inc. Chemical solutions for removing metal-compound contaminants from wafers after CMP and the method of wafer cleaning
US5714203A (en) 1995-08-23 1998-02-03 Ictop Entwicklungs Gmbh Procedure for the drying of silicon
EP1046433B1 (en) 1995-10-13 2004-01-02 Lam Research Corporation Method for removing contaminants by brushing
CN1096703C (zh) 1995-11-15 2002-12-18 大金工业株式会社 晶片处理液及其制造方法
US5700383A (en) 1995-12-21 1997-12-23 Intel Corporation Slurries and methods for chemical mechanical polish of aluminum and titanium aluminide
US5810938A (en) 1996-05-24 1998-09-22 Henkel Corporation Metal brightening composition and process that do not damage glass
TW416987B (en) 1996-06-05 2001-01-01 Wako Pure Chem Ind Ltd A composition for cleaning the semiconductor substrate surface
JPH1041298A (ja) * 1996-07-23 1998-02-13 Toshiba Corp 半導体装置及びその製造方法
US5709755A (en) 1996-08-09 1998-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method for CMP cleaning improvement
US5794299A (en) 1996-08-29 1998-08-18 Ontrak Systems, Inc. Containment apparatus
US6296714B1 (en) 1997-01-16 2001-10-02 Mitsubishi Materials Silicon Corporation Washing solution of semiconductor substrate and washing method using the same
JPH10321572A (ja) 1997-05-15 1998-12-04 Toshiba Corp 半導体ウェーハの両面洗浄装置及び半導体ウェーハのポリッシング方法
JPH113892A (ja) * 1997-06-11 1999-01-06 Ricoh Co Ltd 半導体装置の製造方法
US5935871A (en) * 1997-08-22 1999-08-10 Motorola, Inc. Process for forming a semiconductor device
US6096652A (en) * 1997-11-03 2000-08-01 Motorola, Inc. Method of chemical mechanical planarization using copper coordinating ligands
US6051879A (en) * 1997-12-16 2000-04-18 Micron Technology, Inc. Electrical interconnection for attachment to a substrate

Also Published As

Publication number Publication date
US20020058417A1 (en) 2002-05-16
WO2000059029A3 (en) 2001-02-15
US6610601B2 (en) 2003-08-26
WO2000059029A2 (en) 2000-10-05
AU3867700A (en) 2000-10-16
US6358847B1 (en) 2002-03-19
KR100731850B1 (ko) 2007-06-25
KR20010108419A (ko) 2001-12-07
JP2002540631A (ja) 2002-11-26
EP1186022A2 (en) 2002-03-13
KR20070010211A (ko) 2007-01-22
KR100731851B1 (ko) 2007-06-25

Similar Documents

Publication Publication Date Title
TW454281B (en) Method and apparatus for enabling conventional wire bonding to copper-based bond pad features
US6645550B1 (en) Method of treating a substrate
JP2000212754A (ja) めっき方法及びその装置、並びにめっき構造
US6423200B1 (en) Copper interconnect seed layer treatment methods and apparatuses for treating the same
JP4261931B2 (ja) 無電解めっき装置および無電解めっき後の洗浄方法
US20080017220A1 (en) Apparatus for cleaning a substrate having metal interconnects
CN106783538B (zh) 一种应用于单片清洗工艺的水痕及颗粒消除方法
JP2003115474A (ja) 基板処理装置及び方法
KR20000053597A (ko) 구리도금방법 및 그 장치
JP2001323381A (ja) めっき方法及びめっき構造
US8431443B2 (en) Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
JP2001073157A (ja) 無電解めっき方法及びその装置
US20070085162A1 (en) Capping of copper structures in hydrophobic ild using aqueous electro-less bath
CN100517610C (zh) 半导体元件的处理方法以及半导体元件的形成方法
US6897150B1 (en) Semiconductor wafer surface and method of treating a semiconductor wafer surface
JP2001181851A (ja) めっき方法及びめっき構造
JP5789614B2 (ja) めっき処理中の基板表面をウェットに維持するプロセス
WO2006095881A1 (ja) 基板処理方法及び基板処理装置
JP2003253488A (ja) 電解処理装置
JP2006077275A (ja) 金属膜の成膜方法及び装置
JP2005206905A (ja) 基板処理方法及び装置、並びに処理液
JP2005116630A (ja) 配線形成方法及び装置
JP2005002443A (ja) めっき方法及びめっき装置
JP2004052108A (ja) 基板処理装置
JP2004346399A (ja) 基板処理方法及び基板処理装置

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees