TW445632B - Integrated CMOS circuit arrangement and method for its production - Google Patents

Integrated CMOS circuit arrangement and method for its production Download PDF

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Publication number
TW445632B
TW445632B TW087104881A TW87104881A TW445632B TW 445632 B TW445632 B TW 445632B TW 087104881 A TW087104881 A TW 087104881A TW 87104881 A TW87104881 A TW 87104881A TW 445632 B TW445632 B TW 445632B
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layer
mos transistor
channel mos
silicon layer
channel
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TW087104881A
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Hermann Fischer
Franz Hofmann
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Siemens Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8256—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252 and H01L21/8254
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

45 63 2 A7 _____B7 五、發明説明（1 ) I - H - .^1 —1 - (I I n - In - - H τ {請先閏讀背面之注項再填寫本頁) 當Μ 0 S技術藉由類似的降低尺寸之原理將結構縮減到 最小時，MO S電晶體和C Η 0 S電路之特性基本上仍維持在 微米的範圍之中，但是，例如，在通埴長度約小於2〇〇η 之M0S電晶體的情形中，會發生短通道和穿透效應。 雖然這呰效應部分可Κ藉由增加基板摻雜補償，但是 如此高的基板摻雜特別會導致在通道内之電荷載子移動 率的減少，在通道內之電荷載子移動率的減少尤其在ρ 通道Μ 0 S電晶體中會變的特別明顯。 在CMOS電路配置中，尤其是在反相器，HAND和NOR (¾ ,位移暫存器，記憶體，璉輯和類比電路中，使用製造 之η通道M0S電晶體和ρ通道M0S電晶體不僅具有大小 相同的單位電壓，也有相同的互導和栢同的飽和電流， 其他相同的方法已提出，藉由給定Ρ通道M0S電晶體之 通道寬··長比大於η通道M0S電晶體2倍，建構η通道 M0S電晶體和ρ通道M0S電晶體，Κ完成相同的互導和 相同的飽和電滾（例如，請參見K. Hoffnan在1996年所 著之第三版 VLSI-Entwurf Modelle und Schaltungen [VLSI Design Models and Circuits]第 333到 339頁） 經濟部中央標率局負工消费合作社印裝 ,此係打算補償P通道MOS電晶體中之電洞移動率低於 n通道H0S電晶體中之電子移動率2倍，但是，ρ通道 Μ 0 S電晶體之面積和雜散電容會增加此量測的結果。 A , S a d e k 等人在 1 9 9 5 年 S ο 1 i d ~ S t a t e Eh e c t r 〇 n i c s 第 38期9卷1731-1734頁和K. Ismael在義大利Erice的 1995年 International School of materials science "3 " 本紙張尺度適用中國國家標準（CNS ) Λ4规格（2ΙΟΧ 297公;® ) 445632 經濟部中央標準局員工消費合作社印聚 Α7 Β7 五、發明説明（2 ) and technology的演講論文集第19到20頁提出g由在通 道區提供一受應力的S、vGe層增加p通道M0S電晶體
丄一X X 之通道中的電洞移動率，此層所受之應力係來自其具有 單晶矽晶格常數的實際作用，此層之晶格與^平面匹配 ，為此，會有壓縮應力存在在 SiGe 的X和y方向， 而張開應力則會出現在z方向，其對應於成長方向。此論文中之異 質結構中之假晶層（pseudomorphic layer)以此種方式彈性地受到應 力。為了要製造CH0S電路配置，要形成通道含有Si, Ge 1-x 層之p通道M0S電晶體和形成通道由單晶矽製成之η通 道M0S電晶體，此處需要兩個個別的製程方塊，以製 造Ρ通道M0S電晶體和η通道M0S電晶體。 本發明係根據可Μ降低空間需求和降低製程佈局製造 CMOS積體電路配置之詳加說明的問題，此外，本發明也 詳加說明製造此CMOS電路配置的方法。 此問題係根據本發明藉由申請專利範圍第1項之CMOS 積體電路配置和其產生之申請專利範圍第3項的方來解 決’本發明還包括申請專利範圍附屬項。 根據本發明之CMOS積電路實現在至少具有第一矽層， 受到應力的Si， Ge層和第二矽層之半導體基板中.至
丄一X X 少一 P通道M0S電晶體和至少一 η通道M0S電晶體兩者 皆製作在半導體基板中，本發明中知悉，適當地對Ρ通 道MOS電晶體進行植入’會形成埋入式導電通道（所謂 的埋入式通道），然而在η通道MOS電晶體中，導電通 道係沿著基板表面形成，也就是形成在閘極介電質的 -4 - 本紙張尺度送用中國囤家標準（CNS ) Λ4規格（210ΧΜ7公;f ) -----^—--^— (請先閱讀背面之注意事項再填寫本頁) 訂 445 63 2 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（3) 介面（所謂的表面通道），之後，在CMOS電路配置之 中，在 P通道MOS電晶體區之層中形成通 道，而在η通道MOS電晶體區之第二矽層區中形成導 電通道，結果，電荷載子移動率則由ρ通道MOS電晶 體區中之層和由π通道MOS電晶體區中之 第二矽層決定。 對於P通道MOS電晶體，可以採用Si^Gh層中之 較筒電洞移動率，在Sij.jjGe、層成長時，會在SibyGe^ 層的z方向產生張應力，此z方向之張應力會使重（heavy) 電洞之帶（band)能量增加且會使垂直於應力方向（即，在 電荷載子的傳輸方向）之平面中的T點改變能帶分散，在 此情形下，帶曲線變成像輕電洞者而使電洞質量減輕，在 此情形下，P通道MOS電晶體和π通道MOS電晶體 所需之空間相同，同時，可確定有相同的互導和相同的飽 和電流，因此，ρ通道MOS電晶體和η通道MOS電 晶體可以在一個製程順序中製成，層延伸於n 通道 MOS 電晶體的通道區之下，且不會干擾 n通道 MOS電晶體之工作》
Sii_xGex層之鍺含量最好在25% 和50% 之間，即 X = 0.25〜0_50，受應力的吕^/^層的厚度最好在5ηηι 和ΙΟηιη之間，經常在文獻中稱爲緩衝層且排列在Si^ Gex層之下的第一矽層之厚度最好在3 0nm和70nm之間， 在文獻中經常稱爲帽（cap)層之第二矽層的厚度最好在 5nm 和12nm之間。 第一矽層，受應力的SinGe^層和第二矽層係藉由磊 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） ϊ ------I I^---I L----訂 - -------線 (請先閱讀背面之注急事項再填寫本頁) 445632 A7 B7 經濟部中夹標隼局員工消費合作社印製 五、發明説明（ 4 ) 1 1 晶 成 長 形 成 茌 至少 在 主 區 域 之 範 圍 中 由 矽 構 成 之 半 導 .ft Mr 體 1 1 基 板 的 主 區 域 上， 適 當 的 半 導 體 基 板 為 早 晶 矽 晶 圓 ) 要 1 1 不 然 就 是 SC I 基板 或 在 主 區 域 之 範 圍 中 由 S i C 構 成 之 基 請 1 先 1 板 0 閱 讀 1 1 定 義 η 通 道 MOS電晶體和Ρ 通道Ν 0 E 電Ϊ %體之工作區的 η 面 1 i 之 1 絶 線 結 構 曰 取 好 先形 成 在 主 區 域 之 上 ， 然 後 再 藉 由 選 擇 性 t 1 I 事 喬 晶 成 長 第 一 矽層 受 m 力 的 S i l-xG :層 和 第 二 矽 層 9 項 再 1 此可確保受應力的Si 1- X G ex 層 成 長 » 在 工 作 區 没 有 任 何 缺 填 寫 1 本 陷 〇 頁 ί 1 本 發 明 將 採 用圓 示 之 實 施 範 例 更 詳 細 說 明 於 後 〇 圖 式 1 簡 DD 早 説 明 如 下 ： 1 1 第 1 ΓΗ 圆 爲 在 裔晶 成 長 第 一 矽 層 9 受 應 力 之 Si 1 - -X 層. 1 訂 1 和 第 二 砂 層 之 後具 有 絕 緣 結 稱 的 半 導 體 基 板 j 其 界 定 了 P 通 道 MOS 電 晶體 的 工 作 品、 和 P 通 道 M0S 電 P曰體白 β工作區。 1 1 第 2 圖 為 在 形成 閘 極 介 電 質 ’ 閘 極 電 掻 和 源 極 / 汲 極 1 | 區 之 後 的 半 導 體基 板 截 面 圖 0 1 i X I η 型 摻 雜 井 2係用1 80 k e V能量和4 X 10 13 C 1 -2 劑 量 的 砷 藉 由 有 遮 罩 的佈 植 形 成 在 由 具 有 > 例 如 ， 對 應 Ω -C m 1 電 阻 率 之 基 本 摻雜 準 位 的 P 型 接 雜 卑 晶 矽 製 成 之 基 板 1 1 中 ( 參 見 第 1 圖） 0 1 | 然 後 藉 由 有 遮罩 的 硼 佈 檀 形 成 P 型 摻 雜 井 3， 硼偽以5 0 1 I 到 7 0 k e V的能量和1 到2 X 10 13 era -2 的 劑 量 佈 植 〇 1 1 之 後 1 在 LO COS 製 程 形 成 绝 線 結 構 4 j 例 如 9 該 結 構 1 I 在 η 型 摻 雜 井 2區域定義p 通道Μ 0 S 電晶體之工作區ί【 1在 J ! P 型 摻 雜 井 3區域定義η 通道M0S -6 - 電晶體之工作區， 二擇 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公犮） 經濟部中央標隼局員工消費合作社印製 445632 A7 __B7___五、發明説明（5 ) 其一地，絶緣結構4也可以在淺溝渠絶緣製程中藉由用絶 緣材料填谋溝渠而形成，此絶緣結構4降到低於ti型摻 雜井2和p型摻雜井3之基板1 ^ 接著藉由使用含有SiH2 Cl2之製程氣體的選擇性磊 晶成長第一矽層5 ,在文獻中常稱為緩衝層之第一矽層 5成長30到7〇nH!厚，此第一矽層5為p型接雜，Μ設定 在稍後製作之η通道H0S電晶體和ρ通道H0S電晶體的 臨限電壓，為此，加入氫化硼（β2Η6)到製程氣體中， 直到層厚達到1 5到2 5 η π為止，然後在沒有氫化硼的情肜 ,再成長沒有摻雜的第一矽層5 ,厚度為10到50πβ,在 成長第一層5期間的製程溫度在7 5 0和8 5 0 t：之間。 之後藉由使用含有GeH4之製程氣體，在550和700Ό 之間的製程溫度，選擇性磊晶成長S卜 G e層6 ,例如 1-x X ,形成之Si 〇0 1層6 ,其緒含量X為0.25,而層厚10 na,二擇其一地，珂K與结含量X為0.5 —起形成層厚 5ηκ 之 Sii_xGe;x^ 6 。 然後藉由使用含有SiH2 Cl2之製程氣體的選擇性磊 晶成長層厚5到12πβ的無摻雜且在文獻上常稱為帽層之 第二矽層7 ,在此情形下，溫度係在550和700TC之間。 接著藉由在下120分鐘的熱氧化法形成由Si02 製成之閘極介電質S ,例如，此形成之閘極介電質8的 層厚為4. 5η® (參見第2匾），在此氧化&期間，大約要 消耗第二矽層7的Si2nm,因此.第二矽層7的使用， 有可能會藉由矽的氧化而形成閘極介電質8 ,以此方式 -7- -------^---d-- (#先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家橾準（CNS ) Λ4Α格（210 X 297公嫠） 445 63 2 A7 B7 經濟部中央標準局員工消費合作社印^ 五、發明説明（ ) 1 1 産 生 之 氣 化 矽 因 其 有 較 佳 的 m 久 性 » 所 以 優 於 S ] l G e的 I I 氧 化 物 〇 1 1 對 於 各 種 情 形 下 之 Ρ 通 道 Μ C S 電 晶 體 和 Π 通 道 HOS 電 請 1 先 1 晶 體 的 閘 極 電 極 9 藉 由 沈 積 和 建 構 η —型摻雜β 句多晶 閱 讀 1 | 矽 層 而 形 成 S 之 後 再 m 由 使 用 具 有 2 0到 3 0 k£ V能量和 背 面 I I 之 4到8 X 1 0 15 C Η -2 劑 量 之 硼 及 / 或 BF 2 作 遮 罩 佈 植 S 而 形 t 1 ] 成 用 於 P 通 道 MOS 電 晶 體 之 Ρ 型 摻 雜 源 搔 / 汲 極 區 1 0 項 1 t 再 次 使 用 具 有 1 0 0 - 1 3 0 k eV能 和 4 - 8 X 1 0 15 € nr2劑量之砷 填 寫 本 衣 作 遮 罩 佈 置 1 而 形 成 用 於 η 通 道 M0 S 電 晶 體 之 η 型 摻 雜 頁 1 I 源 極 / 汲 極 區 11 〇 1 1 在 製 程 週 期 中 之 溫 度 負 載 的 結 果 J 硼 摻 雜 <^3 日 在 第 —* 矽 I ί 層 (5 ) 之 中 擴 散 且 分 佈 此 摻 雜 在 表 面 區 域 之 中 ) 在 此 方 1 訂 式 下 對 於 η 通 道 M0 S 電 晶 醱 而 内· 在 表 面 區 域 之 中 可 1 以 得 到 足 夠 高 的 摻 雜 〇 1 1 為 了 最 佳 化 電 晶 體 特 性 $ 可 以 已 知 之 兩 段 式 佈 植 法 分 1 I 別 提 供 L D D 縱 深 和 HD D 縱 深 給 P 型 摻 雜 源 極 / 汲 掻 區 10 1 1 和 η m 摻 雜 源 極 / 汲 棰 區 11 0 | CHOS 電 路 配 置 可 以 已 知 之 沈 積 披 覆 層 開 接 觸 孔 和 形 I 成 金 屬 化 層 等 方 式 完 成 ( 並 未 詳 細 圖 予 說 明 ) ό 1 1 在 各 種 倩 形 下 » η 型 摻 雜 井 2和P 型摻雜井3 都 是 用 1 [ 1 . 5 X 1 0 3 C ]最大雜質濃度形成， 此高雜質濃度偽 1 I 要 防 止 穿 透 效 應 此 高 雜 質 濃 度 在 電 路 配 置 中 是 可 允 許 1 1 的 ， 因 為 η 型 摻 雜 井 2和ρ 型摻雜井3都 是 在 晶 晶 之 前 産生 1 I 9 因 此 就 閛 極 介 電 質 8 的 -8 介 面 而 言 1 大 量 的 摻 雜 並 不 1 1 ί 1 1 1 本紙張尺度適用中國國家標準{ CNS ) A4規格（210X 297公楚） 445 63 2 A7 B7 五、發明説明（7 ) ; 能達成。 在上述之CMOS電路配置中，給定應用適當的控制訊號 , 在p通道M0S電晶體配置中，埋入的導電通道係形 成在η型搀雜2的Si Ge層6之中.在另一方面，在
1-X X π通道M0S電晶體配置中，若驅動適當，則導電通道形 成在P型接雜#3中之第二矽層7的表面上。 i I - HI. - -- - I --ΐ - I : - ! - i— I— iv ,1 (請先閱讀背面之注意事項再填寫本頁) 經滴部中央標準局員工消費合作社印聚 _ 9 _ 本纸張尺度適用中國S家標率（CNS ) Λ4規格（210X 297公釐} 4 4 5 6 3 2 A7 B7
頌請-^ .-;否變更原貧質内容 經滴部中央標準局負工消費合作社印裝 五、發明説明（8 ) 符號對照表 1 基板 2 η型摻雜井 3 P型摻雜井 4 絕緣结構 5 第一矽層 6 S ί Ί Ge 層 1-X X 7 第二矽麿 8 閛極介電質 9 閘極電掻 10 p型摻雜之源搔/汲極區 1 1 ti型接雜之源極/汲搔區 -10- 本紙張尺度遙用中國®家標準（CNS >以说格（2丨OXM7公犮） (請先閱讀背面之注意事項再填寫本頁)

Claims (1)

  1. A8 BS C8 D8 六、申請專利範圍 第87i(M881號「CMOS積體電路配置及其製造方法」專利 案 （90年4月修正） A申請專利範圍： 1·—種CMOS積體電路配置，其特徵爲： -提供之半導體基板（1)至少具有一第一矽層（5)， 一受應力的SinGh層（6>和一第二矽層（7), -受應力的8丨1_^61[層（6)基本上具有與第一矽層 (5)和第一砂層（7)相同的晶格常數， -受應力的Sine%層⑹在Z方向中具有張應力，此 SihG^層⑹是在Z方向中生長， -p通道MOS電晶體和η通道MOS電晶體係製作 在該半導體基板中= 2·如申請專利範圍第1項之電路配置，其中 -第一矽層（5>具有3〇nm和7〇nm之間的厚度， -受應力的SiuGe,層（6)具有5nm至lOiim之間的厚 度，且鍺含量在5 0原子％和2 5原子％之間， -第二矽層（7)具有Snm和12nm之間的厚度。 經濟部智慧財產局員工消費合作社印製
    145 6 (請先閲讀背面之注意事項再填寫本頁) 3.—種CMOS積體電路配置之製造方法，其特徵爲： -至少在主區域之範圍中由矽組成之半導體基板（1)的 主區域上嘉晶成長第一砂層（5)，受應力的Si^Gex 層（6)和第二矽層（7), -受應力的層⑹在Z方向中具有張應力，此 Si^Ge,層⑹是在Z方向中生長， 本紙張尺度適用中國國家標準（CNS ) A4規格（210乂297公釐） 445 63 2 as B8 C8 D8 六、申請專利範圍 -在該半導體基板（1)中形成p通道MOS電晶體和η 通道MOS 電晶體= 4. 如申請專利範圍第3項之方法，其中 -形成絕緣結構以定義一種用於η通道MOS電晶體 之工作區和用於Ρ通道MOS電晶體之工作區， -在成長第一矽層（5>，受應力的層（6)和第 二矽層（7)之後，藉由選擇性磊晶方法分別形成η通 道MOS電晶體和ρ通道MOS電晶體所用之閘極 介電質（8)，閘極電極（9)和源極/汲極區（1〇 ,11)。 5. 如申請專利範圍第3或第4項之方法，其中 -形成之第一矽層（5)的厚度在30nm和70nm之間， 形成之第二矽層（7)的厚度在5nm和Unm之間， -形成之8丨1_:^6!(層（6)的厚度在5nm和ι〇ηηι之間， 且鍺含量在50原子％和25原子％之間。 6. 如申請專利範圍第3或第4項之方法， 其中在第一砂層（5)的慕晶成長期間，藉由加質· 以設定π通道MOS電晶體及/或P通道MOS電晶 體之臨限電壓。 7. 如申請專利範圍第3或第4項之方法， 其中嘉晶方法係使用含有SiH^Cl2及/或之製 程氣體，在5S〇°C和850 °C之間的溫度範_中進行。 •2- 本紙張尺度速用中國國家標準（CNS ) A4規格（210x297公釐） (請先閱讀背面之注意事項再填寫本頁) ，1T 經濟部智慧財產局員工消費合作社印製
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