TW432304B - Integrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus - Google Patents

Integrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus Download PDF

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Publication number
TW432304B
TW432304B TW086118367A TW86118367A TW432304B TW 432304 B TW432304 B TW 432304B TW 086118367 A TW086118367 A TW 086118367A TW 86118367 A TW86118367 A TW 86118367A TW 432304 B TW432304 B TW 432304B
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Taiwan
Prior art keywords
design
layer
module
information
behavior
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TW086118367A
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English (en)
Chinese (zh)
Inventor
Masaharu Imai
Akichika Siomi
Yoshinori Takeuchi
Jun Sato
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Semiconductor Tech Acad Res Ct
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW086118367A 1996-12-13 1997-12-05 Integrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus TW432304B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8333539A JP2954894B2 (ja) 1996-12-13 1996-12-13 集積回路設計方法、集積回路設計のためのデータベース装置および集積回路設計支援装置

Publications (1)

Publication Number Publication Date
TW432304B true TW432304B (en) 2001-05-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW086118367A TW432304B (en) 1996-12-13 1997-12-05 Integrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus

Country Status (5)

Country Link
US (1) US6026228A (fr)
EP (1) EP0848342A3 (fr)
JP (1) JP2954894B2 (fr)
KR (1) KR100281977B1 (fr)
TW (1) TW432304B (fr)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6169968B1 (en) * 1997-07-09 2001-01-02 Matsushita Electric Industrial Co., Ltd. Apparatus and method for estimating performance integrated circuit
US6430732B1 (en) 1998-03-27 2002-08-06 Xilinx, Inc. Method for structured layout in a hardware description language
US6243851B1 (en) 1998-03-27 2001-06-05 Xilinx, Inc. Heterogeneous method for determining module placement in FPGAs
US6237129B1 (en) 1998-03-27 2001-05-22 Xilinx, Inc. Method for constraining circuit element positions in structured layouts
US6292925B1 (en) 1998-03-27 2001-09-18 Xilinx, Inc. Context-sensitive self implementing modules
US6260182B1 (en) * 1998-03-27 2001-07-10 Xilinx, Inc. Method for specifying routing in a logic module by direct module communication
US6216258B1 (en) 1998-03-27 2001-04-10 Xilinx, Inc. FPGA modules parameterized by expressions
US6199031B1 (en) * 1998-08-31 2001-03-06 Vlsi Technology, Inc. HDL simulation interface for testing and verifying an ASIC model
JP3562975B2 (ja) * 1998-09-29 2004-09-08 株式会社東芝 集積回路設計方法及び集積回路設計装置
JP2000123061A (ja) 1998-10-16 2000-04-28 Matsushita Electric Ind Co Ltd 集積回路装置の設計用データベース及び集積回路装置の設計方法
US6233724B1 (en) 1998-10-30 2001-05-15 Micron Technology, Inc. Circuit synthesis time budgeting based upon wireload information
US6226777B1 (en) * 1998-11-25 2001-05-01 Agilent Technologies, Inc. Method and system for improving the performance of a circuit design verification tool
AU3754100A (en) * 1999-03-19 2000-10-09 Moscape, Inc. System and method for performing assertion-based analysis of circuit designs
JP3250542B2 (ja) 1999-03-23 2002-01-28 日本電気株式会社 Ｌｓｉ設計方法
US6505328B1 (en) * 1999-04-27 2003-01-07 Magma Design Automation, Inc. Method for storing multiple levels of design data in a common database
US6298472B1 (en) * 1999-05-07 2001-10-02 Chameleon Systems, Inc. Behavioral silicon construct architecture and mapping
US6581029B1 (en) * 1999-05-11 2003-06-17 International Business Machines Corporation Method and system for optimizing execution of a collection of related module sequences by eliminating redundant modules
US6671857B1 (en) * 1999-08-18 2003-12-30 Matsushita Electric Industrial Co., Ltd. Method of designing integrated circuit device using common parameter at different design levels, and database thereof
JP2001067384A (ja) * 1999-08-26 2001-03-16 Matsushita Electric Ind Co Ltd 集積回路装置の設計用データベース及び集積回路装置の設計方法
US6397341B1 (en) * 1999-08-27 2002-05-28 Synopsys, Inc. Method for improving the speed of behavioral synthesis links to logic synthesis
US7062425B1 (en) * 1999-09-30 2006-06-13 Cypress Semiconductor Corp. Method and apparatus for automated enumeration, simulation, identification and/or irradiation of device attributes
US6804810B1 (en) * 2000-02-21 2004-10-12 Hewlett-Packard Development Company, L.P. Resistance and capacitance estimation
US6467074B1 (en) 2000-03-21 2002-10-15 Ammocore Technology, Inc. Integrated circuit architecture with standard blocks
JP2002163324A (ja) * 2000-11-28 2002-06-07 Hitachi Ltd 遅延時間計算方法及びそれを用いた半導体集積回路の設計方法
US7302670B2 (en) 2000-12-21 2007-11-27 Bryan Darrell Bowyer Interactive interface resource allocation in a behavioral synthesis tool
JP2002318825A (ja) * 2001-04-20 2002-10-31 Hitachi Ltd 論理回路の設計方法
WO2002103585A1 (fr) 2001-06-15 2002-12-27 Cadence Design Systems, Inc. Renforcement de la fusionnabilite des chemins de donnees et reduction des largeurs de chemins de donnees en reponse a une limite superieure d'un contenu d'information
KR100429573B1 (ko) * 2001-12-24 2004-05-03 주식회사 하이닉스반도체 레지스터 전송레벨 코드의 생성방법
US20030120475A1 (en) 2001-12-26 2003-06-26 Toshiba Tec Kabushiki Kaisha Method of generating asic design database
JP3825328B2 (ja) * 2002-01-23 2006-09-27 Ｎｅｃエレクトロニクス株式会社 プロセッサ合成装置、システムｌｓｉ合成装置、プロセッサ合成方法、システムｌｓｉ合成方法、及び記録媒体
JP2003316838A (ja) * 2002-04-19 2003-11-07 Nec Electronics Corp システムｌｓｉの設計方法及びこれを記憶した記録媒体
JP4541783B2 (ja) * 2004-06-30 2010-09-08 富士通セミコンダクター株式会社 半導体集積回路の設計方法、設計装置及び論理設計プログラム
US20060156268A1 (en) * 2005-01-13 2006-07-13 Wen Kuei-Ann Circuit design platform
US7483823B2 (en) 2005-06-21 2009-01-27 Nvidia Corporation Building integrated circuits using logical units
US7363610B2 (en) 2005-06-21 2008-04-22 Nvidia Corporation Building integrated circuits using a common database
EP1736905A3 (fr) * 2005-06-21 2007-09-05 Nvidia Corporation Conception de circuits intégrés en utilisant des unités logiques
KR100809684B1 (ko) 2005-08-22 2008-03-06 삼성전자주식회사 디바이스의 전원차단효과를 ｒｔｌ에서 검증할 수 있는 검증 장치 및 전원차단효과를 모델링 하는 방법
US7735050B2 (en) 2006-02-09 2010-06-08 Henry Yu Managing and controlling the use of hardware resources on integrated circuits
JP5114877B2 (ja) * 2006-06-27 2013-01-09 富士通株式会社 設計データ作成方法、設計データ作成装置および設計データ作成プログラム
US8516418B2 (en) * 2006-06-30 2013-08-20 Oracle America, Inc. Application of a relational database in integrated circuit design
US8819608B2 (en) 2007-07-23 2014-08-26 Synopsys, Inc. Architectural physical synthesis
US8595674B2 (en) 2007-07-23 2013-11-26 Synopsys, Inc. Architectural physical synthesis
US8307315B2 (en) 2009-01-30 2012-11-06 Synopsys, Inc. Methods and apparatuses for circuit design and optimization
US8082530B1 (en) * 2009-02-20 2011-12-20 Xilinx, Inc. Power estimation in high-level modeling systems
CN102708265B (zh) * 2012-06-12 2014-01-22 电子科技大学 一种带通滤波器直接综合设计方法
KR102218200B1 (ko) 2014-03-06 2021-02-23 삼성전자주식회사 스프레드 시트를 이용한 rtl 자동 합성 시스템, 방법 및 기록매체
JP5839379B1 (ja) * 2015-02-12 2016-01-06 アダプトＩｐ株式会社 Ｉｐ自動生成システム
JP7081331B2 (ja) * 2018-06-22 2022-06-07 日本電気株式会社 回路合成装置、回路合成方法、及び、回路合成プログラム
CN114066238B (zh) * 2021-11-16 2022-11-29 四川省林业和草原调查规划院(四川省林业和草原生态环境监测中心) 一种林地保护利用规划指标确定系统、云平台系统及方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572436A (en) * 1990-04-06 1996-11-05 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design
US5870308A (en) * 1990-04-06 1999-02-09 Lsi Logic Corporation Method and system for creating and validating low-level description of electronic design
US5557531A (en) * 1990-04-06 1996-09-17 Lsi Logic Corporation Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation
US5544066A (en) * 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints
US5499192A (en) * 1991-10-30 1996-03-12 Xilinx, Inc. Method for generating logic modules from a high level block diagram
EP0597087B1 (fr) * 1992-06-02 1999-07-28 Hewlett-Packard Company Procedes de conception assistee par ordinateur destines a des technologies d'interconnexions a multiniveaux
US5557532A (en) * 1992-11-12 1996-09-17 Vlsi Technology, Inc. Parameterized generic compiler
US5566079A (en) * 1992-11-12 1996-10-15 Vlsi Technology, Inc. Parameterized generic multiplier complier
US5487018A (en) * 1993-08-13 1996-01-23 Vlsi Technology, Inc. Electronic design automation apparatus and method utilizing a physical information database
US5533148A (en) * 1993-09-30 1996-07-02 International Business Machines Corporation Method for restructuring physical design images into hierarchical data models
US5953519A (en) * 1995-06-12 1999-09-14 Fura; David A. Method and system for generating electronic hardware simulation models
US5764532A (en) * 1995-07-05 1998-06-09 International Business Machines Corporation Automated method and system for designing an optimized integrated circuit
US5841663A (en) * 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
US5802349A (en) * 1996-01-22 1998-09-01 Motorola, Inc. Method for generating an optimized integrated circuit cell library

Also Published As

Publication number Publication date
US6026228A (en) 2000-02-15
EP0848342A3 (fr) 2001-01-10
JPH10171857A (ja) 1998-06-26
KR100281977B1 (ko) 2001-02-15
EP0848342A2 (fr) 1998-06-17
JP2954894B2 (ja) 1999-09-27
KR19980063998A (ko) 1998-10-07

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