TW429581B - A method of fabricating a multi-layered wiring system of a semiconductor device - Google Patents

A method of fabricating a multi-layered wiring system of a semiconductor device

Info

Publication number
TW429581B
TW429581B TW088115205A TW88115205A TW429581B TW 429581 B TW429581 B TW 429581B TW 088115205 A TW088115205 A TW 088115205A TW 88115205 A TW88115205 A TW 88115205A TW 429581 B TW429581 B TW 429581B
Authority
TW
Taiwan
Prior art keywords
layer
forming
reflective layer
predetermined portions
conductive
Prior art date
Application number
TW088115205A
Other languages
English (en)
Inventor
Joo-Sung Park
Chan-Hyoung Cho
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW429581B publication Critical patent/TW429581B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW088115205A 1998-09-03 1999-09-03 A method of fabricating a multi-layered wiring system of a semiconductor device TW429581B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980036319A KR100267106B1 (ko) 1998-09-03 1998-09-03 반도체 소자의 다층 배선 형성방법

Publications (1)

Publication Number Publication Date
TW429581B true TW429581B (en) 2001-04-11

Family

ID=19549496

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088115205A TW429581B (en) 1998-09-03 1999-09-03 A method of fabricating a multi-layered wiring system of a semiconductor device

Country Status (3)

Country Link
US (1) US6218283B1 (zh)
KR (1) KR100267106B1 (zh)
TW (1) TW429581B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465350B1 (en) * 1999-11-29 2002-10-15 Texas Instruments Incorporated Aluminum nitride thin film formation on integrated circuits
JP4190118B2 (ja) * 1999-12-17 2008-12-03 三菱電機株式会社 半導体装置、液晶表示装置および半導体装置の製造方法
KR100373708B1 (ko) * 2000-07-24 2003-02-25 아남반도체 주식회사 반도체 소자의 금속 배선층 형성 방법
WO2002017693A1 (fr) * 2000-08-18 2002-02-28 Mitsubishi Denki Kabushiki Kaisha Substrat d'installation, procede de montage d'un tel substrat et douille d'ampoule mettant en oeuvre ledit substrat
US6613664B2 (en) * 2000-12-28 2003-09-02 Infineon Technologies Ag Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
JP2003115535A (ja) * 2001-10-04 2003-04-18 Hitachi Ltd 半導体集積回路装置
KR100432785B1 (ko) * 2001-12-20 2004-05-24 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US20030219459A1 (en) * 2002-01-18 2003-11-27 Cytos Biotechnology Ag Prion protein carrier-conjugates
US6806579B2 (en) * 2003-02-11 2004-10-19 Infineon Technologies Ag Robust via structure and method
KR20040081240A (ko) * 2003-03-14 2004-09-21 주식회사 하이닉스반도체 반도체소자의 금속배선 형성방법
KR100506943B1 (ko) * 2003-09-09 2005-08-05 삼성전자주식회사 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들
US7045455B2 (en) * 2003-10-23 2006-05-16 Chartered Semiconductor Manufacturing Ltd. Via electromigration improvement by changing the via bottom geometric profile
US7263762B2 (en) * 2004-09-30 2007-09-04 Hitachi Global Storage Technologies Method for reducing pole height loss in the formation of a write pole for a magnetic write head
KR100668833B1 (ko) * 2004-12-17 2007-01-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 제조방법
US7332428B2 (en) * 2005-02-28 2008-02-19 Infineon Technologies Ag Metal interconnect structure and method
KR100665852B1 (ko) * 2005-08-03 2007-01-09 삼성전자주식회사 반도체 소자의 제조방법
DE102006035645B4 (de) * 2006-07-31 2012-03-08 Advanced Micro Devices, Inc. Verfahren zum Ausbilden einer elektrisch leitfähigen Leitung in einem integrierten Schaltkreis
KR100790452B1 (ko) * 2006-12-28 2008-01-03 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
KR100857999B1 (ko) * 2006-12-28 2008-09-10 동부일렉트로닉스 주식회사 씨모스 이미지센서 및 그 제조방법
US10163644B2 (en) 2014-02-07 2018-12-25 Taiwan Semiconductor Manufacturing Company Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same
JP6552547B2 (ja) * 2017-05-24 2019-07-31 三菱電機株式会社 赤外線センサおよび赤外線固体撮像装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106461A (en) * 1989-04-04 1992-04-21 Massachusetts Institute Of Technology High-density, multi-level interconnects, flex circuits, and tape for tab
JP2660359B2 (ja) * 1991-01-30 1997-10-08 三菱電機株式会社 半導体装置
US5470790A (en) * 1994-10-17 1995-11-28 Intel Corporation Via hole profile and method of fabrication
US5565707A (en) * 1994-10-31 1996-10-15 International Business Machines Corporation Interconnect structure using a Al2 Cu for an integrated circuit chip
JPH0917785A (ja) * 1995-06-30 1997-01-17 Sony Corp 半導体装置のアルミニウム系金属配線
JPH0955425A (ja) * 1995-08-10 1997-02-25 Mitsubishi Electric Corp 多層Ａｌ配線構造を有する半導体装置およびその製造方法
JPH11186382A (ja) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR20000018646A (ko) 2000-04-06
KR100267106B1 (ko) 2000-10-02
US6218283B1 (en) 2001-04-17

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees