CA2064922A1 - Tapering sidewalls of via holes - Google Patents
Tapering sidewalls of via holesInfo
- Publication number
- CA2064922A1 CA2064922A1 CA 2064922 CA2064922A CA2064922A1 CA 2064922 A1 CA2064922 A1 CA 2064922A1 CA 2064922 CA2064922 CA 2064922 CA 2064922 A CA2064922 A CA 2064922A CA 2064922 A1 CA2064922 A1 CA 2064922A1
- Authority
- CA
- Canada
- Prior art keywords
- via hole
- via holes
- conductive layer
- tapered
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
A method of tapering side walls of via holes and a tapered via hole structure for an integrated circuit is provided. Via holes having steep sidewalls are provided in an insulating layer overlying a conductive layer on a substrate, with an underlying conductive layer exposed at a bottom of each via hole. A protective layer is provided over the conductive layer in each via hole, and over the sidewalls. The via holes are then tapered by argon sputter etching to remove the protective layer and part of the insulating layer from the sidewall and around the peripheral edge of each via hole, thereby smoothly tapering the sidewall and providing a via hole increasing continuously in diameter from the bottom to the upper peripheral edge of the via hole. Via holes of multiple depths are simultaneously and smoothly tapered to the bottom of the via holes Any sputtered debris remaining in the via holes after the sputter etch step is removed by reactive ion etching to clean the conductive layer exposed in each via hole and allow for formation of reliable electrical contacts.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA 2064922 CA2064922C (en) | 1992-04-02 | 1992-04-02 | Tapering sidewalls of via holes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA 2064922 CA2064922C (en) | 1992-04-02 | 1992-04-02 | Tapering sidewalls of via holes |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2064922A1 true CA2064922A1 (en) | 1993-10-03 |
CA2064922C CA2064922C (en) | 1998-11-24 |
Family
ID=4149560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA 2064922 Expired - Fee Related CA2064922C (en) | 1992-04-02 | 1992-04-02 | Tapering sidewalls of via holes |
Country Status (1)
Country | Link |
---|---|
CA (1) | CA2064922C (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5933756A (en) * | 1995-10-18 | 1999-08-03 | Ricoh Company, Ltd. | Fabrication process of a semiconductor device having a multilayered interconnection structure |
-
1992
- 1992-04-02 CA CA 2064922 patent/CA2064922C/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5933756A (en) * | 1995-10-18 | 1999-08-03 | Ricoh Company, Ltd. | Fabrication process of a semiconductor device having a multilayered interconnection structure |
Also Published As
Publication number | Publication date |
---|---|
CA2064922C (en) | 1998-11-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |