TW419799B - Leadless array package - Google Patents
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- TW419799B TW419799B TW088104633A TW88104633A TW419799B TW 419799 B TW419799 B TW 419799B TW 088104633 A TW088104633 A TW 088104633A TW 88104633 A TW88104633 A TW 88104633A TW 419799 B TW419799 B TW 419799B
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- 239000000463 material Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 3
- 239000010703 silicon Substances 0.000 claims abstract description 3
- 239000013078 crystal Substances 0.000 claims description 50
- 238000012360 testing method Methods 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 239000004593 Epoxy Substances 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 4
- 230000007547 defect Effects 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 8
- 238000005253 cladding Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- 238000003339 best practice Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
41979 D
發明領域 本發明係關於積體電路封裝件之領域。 背景技術 在積體電路的裝配中’製造具有較大密度及較小封事 寸之電子組件是一項持續的挑戰。將印刷電路板上的^尺 空間作盡可此最有效率的運用是極為重要的β積體電路封 裝的趨勢’是擺脫傳統的雙排(dual-in-1 ine )及穿孔式 封裝’而朝向表面式安裝(surface-mount)封裝件,諸 列Gba丄L gj ii aj:X4J )及晶方承載器封裝件(cj3u ’ )。表面式安裝是一種將一封裝1(:物理 地裝設至印刷電路板(PCB)表面的過程,而不是將引線 插入穿過PCB鍍上金屬的孔。封裝件的設計細節,諸如外 形、插腳排列方式及尺寸,通常由同業公會,例如JEDEC 來訂定。 大部分表面式安裝的元件都使用引線以將晶f封裝件安 裝至PCB表面。小型1C封裝件(S〇ic, small outline 1C )及四邊形扁平封裝件(QFP,QUad flat pack)經常使 用從該元件伸展開的「鷗翼型(gu丨丨w i ng )」引線。鷗 翼型的主要優點是,焊接頭可易於檢查。其缺點則是,暴 露出來的引線常會在系統板上回焊(ref l〇w )之前的處裡 中彎曲及斷裂。其另一缺點是,因為引線展開,所以在 PCB上引線會佔用額外的空間。 另一種使用的引線形式為「】引線」,其引線被捲摺在
)41979 9 五、發明說明(2) 裝置下,形狀如同英文字母「J」。「J引線」通常被使用 於塑膠引線式晶方承載器(PLCC,plastic-leaded chip carrier ) 。 「J引線」的優點是,其佔用電路板較少的空 間’且引線被保護於裝置的下方。然而,這也使此種裝置 較不易於測試、檢查或維修,且不允許薄斷面安裝(1 〇w profile mounting) ° 無引線式積體電路封裝件為先前技術中習知者。MUes 等人之美國專利第5,5 3 5,1 0 1號揭示—種^ ?厂線一恐 ,其使用球形格狀陣列供安裝至印席/電路 形格狀陣列係利用位於,產鈹之焊球而安裝至印 路板。此種安排具有一些優點,例如,因為沒有 裝件邊緣突出’所以封裝件尺寸較小。然格: 歹“似)存在著某些缺點。首先,焊接頭係隱藏於封/ 件底侧’而使得視查及原地探針測試f τ π ^ • 、— ^ ^ in-situ probe teS』ing)貫際上不可能達成。再者,因為BGA具有可保捭 晶,且扇出引線的電路板’故BGA系統的 二^ 從面積的觀點來看,BGA佔用較少的* 金〜^然 使。這將使整體系統:;用二巍篇會 發明概述 ' a 但具有可供@及^ 件利用封裝件邊緣上 可延伸至 。無引線式封裴件 本發明係為一種積體電路封裝件 刷電路板(PCB ),其不具有插腳, 笔>蹢畚。本發明之無引線式封裝 觸點以安裝至印刷電路板,該觸點 (solder reflow pad)
Λ19799 五 發明說明(3) ___ 有類似於禅運_矣& 因為安裝安裝封裝件的印跡—A"。 可周/ 有引線,原本引線結構所使用的空間二 Γ周於容納矽元件晶方。 二間,現在 =:式陣列封裳件具有一 r5|,該基 印刷電路板之製作材料相同,所以在表面= :.、、、不相配(thermal mismatch )問題便可顯^ 、 二;=因為電觸點係位於無引線式封裝件減封 更ί易I;及測試可較球形格狀陣列型安裝系統之封裝件 要說明 圖1為一無引線式封裝件之斜視圖。 =2為無引線式封裝件在製造階段配置之 本發明之第1體例。 ㈤例不 圖3為另一無引線式封裝件在製造階段配置之俯 例示本發明之第二具體例。 圖4為無引線式陣列封裝件之斜視圖,例示 在最終使用者的印刷電路板上。 装封裝件 最佳實施楛式 參照圖1,無引線式陣列封裝件1 〇係以一種「三明治」 方式組裝。一底層21,由基底材料所製成,包含無引線式 陣列封裝件之底部。一積體電路晶方丨5接合於底層2丨之上 方’而一包覆材料11覆蓋於積體電路晶方15及底層21之上 方。然後’完整之無引線式陣列封裝件1 〇便可準備安裝至
D:\2D-CODE\88-05\88104633. ptd
第7頁 419799 五 '發明說明(4) 最終使用者的印刷電路板上。 參照圖2,.底層2丨)係由、言板材崎所兔畫、例如環氧玻璃 或其他一般用於印刷電路板製造的合適料。使用此種基 板材料製作底層21的理由是,藉由使用相同或相似於最終 使用者之印刷電路板製造材料的基板材料,可顯著地減小 熱不相配(therma 1 mi smat ch )的可能性。藉由減小熱不 相配的可能性,可減小因熱膨脹係數差異所引起的機械應 力,因而減小晶方封裝件中焊接及接線失敗的可能性。在 氯龙後,'底_層.0將被分I成激瓜分,亂秦4遠暴篇 16,每一底層區域為一個晶方。每一個別底層區域16的長 度14及寬度1 2係等於小型積體電路(SOIC )晶方封裝件印 跡(footprint)的標準尺寸。底層21的基板材料通常很 薄,名目厚度約0.38〜0.64毫米。在本發明之一具體例 中’底層係由一 35毫米環氧玻璃(epoxy-glass )捲帶所 製成’其係被捆在滾輪上ϋ膦椿。此種使 用環氧玻璃捲帶的形式,使得製造過程可相容於許多自動 處裡、測試及佈局系統,且亦便利於平行測試。 本發明也可使用其他種類的IC印跡,例如TS0P,但其 必須使用於具有小引線數目(3 2插腳或更少)的積體電路 晶方。這是因曰^^弓L屢位-於1C是友一的.一,以 可入。引線數目被IC晶方周邊的尺寸 所限制。甚至i FV的k度,引線間必須存在有間隔以防 止短路發生。為獲得額外的空間,晶方的四邊均可供引線 使用,引線的設置係可使使用者能進行引線的PCB佈線。
419799 五、發明說明(5) 如果IC晶方太大’晶方的石夕晶粒與底層基板間的熱不相配 太大,而晶方封裝件非常可能會破裂。因此每一底層區域 必須選定適當尺寸的晶方。 繼續參照圖2,在底層21的上方配置了一連串的金屬合 接塾(Ϊ 9 ’積體電路晶方15可安裝於其上。金屬合接墊IQ係 對應於積體電路晶方15的尺寸而設的。金屬墊19可設計成 適用於兩邊或四邊上具有觸點的1C晶方。在圖2中,顯示 觸點位於I C晶方的兩邊。積體電路晶方1 5通常小於個別底 層區域16 ’但其尺寸亦可與底層區域16相同(因此,尺寸 與一標準SOIC封裝件相同)。在圖2中,積體電路晶方15 係小於底層區域16。每一底層區域16中將會安裝一積體電 路晶方15。在整個底層21上可佈局一大型積體電路晶方陣 列(例如1 Ο Ο X 1 5 0晶方)。同時生產大數量的晶方封裝件 是有利的,因為可節省時間及成本,且能夠同時製造及測 試一大數量的晶方封裝件。當IC晶方15被佈局在底層2 1 上,晶粒被附接至板的上側’且考線4 位於金屬晶方% 與每一個別底層區域16邊緣上的我1觸雜义間。當使用工 業標準尺寸之晶方時’如圖2所示,晶方1 5的邊緣與底層 21的邊緣之間通常有約1 . 4 mm的空間,以允許標準接線及 晶粒附接。 圖3係例示當I C晶方1 5的尺寸與底層區域的尺寸相同的 情況(如圖2所界定該區域具有標準SOIC封裝件的長14及 寬12 )。在此種情況’金屬晶方9與板觸點23之間的距 離為最小,且不是使用接線技術,而是使用倒裝法(f 1 i p
D:\2D-CODE\88-05\88104633. ptd 第9頁
I 419799 五、發明說明(6) ch i ρ ) /凸塊(bump )技術以· I έ昂方附接至瘡、違域 16 〇 ' 再參照圖2,在接線及晶粒附接之後,一包覆材料丨i , 較佳為環氣樹脂覆蓋(epoxy overcoat)或塑穆模製 (Plastic molding) ’被塗敷到整個積體電路晶方15陣 列及底層21。通常,該包覆材料厚度應超過2 mffl。然後, 方附接且被包覆材料n覆蓋的整轉瓣 一 氮β此部分分割將使每一個別晶方封 裝件與其他的晶方封裝件成電性隔離,因 個上所述,個別晶方陣列封裝件的=二皮 S0IC Β曰方封裝件的標準尺寸相同。以 將會符合標準尺寸S0IC印跡。 '早夕i封裝件 在如上述部分分割成個別晶方 測試。典型地,這些測試 :封裝件被 圖確認是否有任何會導致二業生產測試’其意 守软積體電路故障的居都遛彳土庇t 這些測試可藉由習知的測…"::㈣局八k瑕疵。 , 、』式儀器來進行,例如掇测+ 者。大部分的習知測試="如及類似 (其連接至合接墊)心ί都具有小到能夠接觸板觸點2 3 也存在著可能性。在〶 。、平行地測試數個晶方封裝件 後,^害jAiJ f :且認為其符合測試要求之 的最終分割通常為么*牛。此種在測試之後 有介於晶方封裝件之間的带以70全念牛(所 了)。 、電性連接都已在測試之前被分開
第10頁 五、發明說明(7) " ' ---- 參照圖4 ’完成的I c陣列封裝件丨0,可被安裝於最終 用者的印刷電路板59。I C陣列封裝件1 〇被置於印刷電、路 59上焊接鮮的庄方.。焊接鐵5龙對應於板觸滅、_,其係暴 。藉1¾ :然後 印刷電路板5 9及i C陣列封裝件在一熱對流爐中加熱。焊膏 流動’ 塾5 7身板觸點2 3之間有媒^ ( s0 1 r f 1 )€。在從爐中取出之後,當焊流冷1時,無引線式陣列 封裝件10與最終使用者的印刷電路板之間便存在一電性 及機械連接。
Claims (1)
- 419799 六、申請專利範圍 !.一種無引線式〇^1^封裝每,包含:— 一積體電路晶方’其周圍上具有複數個n·^; 一底層,其具有一長度及一寬度’及具有包含一上側的 兩相對主側,上侧具有數個^^签配置在底層的周圍、且 對應於積體電路晶方上的運-接i ’該積體電路晶方被接合 至底層的上侧; —包覆材料,其覆蓋於積體電路晶方、且本質上覆蓋整 個底層的上側;及 一連串的板觸點,連接至合接墊’且未被包覆材料所覆 蓋,因此板觸點係暴露以供焊流(S ο 1 d e r f 1 〇 W )連接至 使用者的電路板° 2. 如申請專利範圍第1項之無引線式羞件;, 其中底層係由環氧玻璃(epoxy-glass)所組成》 3, 如申請專利範圍第1項之無引線式, 其中積體電路晶方具有一長度及寬度,其小於或等於底層 之長度及寬度。 4 ·如申請專利範圍第1項之無引線式積艘電路封裝件, 其中底層之長度及寬度對應於標準小型積體電路(S〇ic, small outline 1C)印跡(footprint)之標準長度及寬 度。 5. —種無引線式積體電路封裝件,包含: 一底層,其由絕緣基板製成,且具有包含一上側的兩相 對主側,上側具有複數個合接墊配置在底層的周圍,該底 層之尺寸對應於標準積體電路印跡;4^799六、申請專利範圍 一積體電路晶方,其具有複數個連接墊在其周圍上,哕 積體電路晶方具有一矽晶粒,其尺寸等於或小於底層之= 寸’該積體電路晶方係被附接至底層的上側;一 〇覆材料,覆蓋該積體電路晶方、且本質上覆蓋整個 底層的上側;及 一連串的板觸點,連接至底層之周圍上的合接墊,且未 被包覆材料所覆蓋,因此板觸點係暴露以供 n〇tf)連接至使用者之電路板。 6. 如申請專利範圍第5項之無引線式積體電路封裝件, 其中底層係由環氧玻璃組成。 7. 如申凊專利範圍第5項之無引線式積體電路封裝件’ 其中該積體電路晶方具有小於33晶方觸點的?丨線數目。 S. —種構造無引線式積體電路封裝件之方法,該方法包 含步驟: 該底層係由絕 在底層之上側配置一連串的金屬合接墊 緣基板製成; 將一積體電路晶方陣列附接至金屬合接墊; 以包覆材料覆蓋積體電路晶方及底層; 將底層部份分割且電性隔離成個別晶方封裝件; 測試底層上之個別晶方封裝件以確定是否有任何製造瑕 疲;及 元全分開底層以使晶方封裝件分割成個別晶方封裝件。 9 ·如申請專利範圍第8項之構造無引線式積體電路封裝 件之方法,其中該積體電路晶方及底層個別具有一長度及D:\2D-CODE\88-05\88104633. ptd 第13頁 41979 9 六、申請專利範圍 一寬度,該積體電路晶方之長度及寬度小於該底層之長度 及寬度。 1 0.如申請專利範圍第8項之構造無引線式積體電路封裝 件之方法,其中該積體電路晶方及底層個別具有一長度及 一寬度,該積體電路晶方之長度及寬度等於該底層之長度 及寬度。D:\2D-CODE\88-05\88104633.ptd 第14頁
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US09/063,817 US6177722B1 (en) | 1998-04-21 | 1998-04-21 | Leadless array package |
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TW419799B true TW419799B (en) | 2001-01-21 |
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TW088104633A TW419799B (en) | 1998-04-21 | 1999-03-24 | Leadless array package |
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US (2) | US6177722B1 (zh) |
TW (1) | TW419799B (zh) |
WO (1) | WO1999054932A1 (zh) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012745A (ja) * | 1998-06-24 | 2000-01-14 | Nec Corp | 半導体パッケージおよびその製造方法 |
JP3556503B2 (ja) * | 1999-01-20 | 2004-08-18 | 沖電気工業株式会社 | 樹脂封止型半導体装置の製造方法 |
IT1320025B1 (it) * | 2000-04-10 | 2003-11-12 | Viasystems S R L | Supporto del tipo a circuito stampato per circuiti elettroniciintegrati, procedimento per la sua fabbricazione, e componente |
US6603191B2 (en) * | 2000-05-18 | 2003-08-05 | Casio Computer Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP3485525B2 (ja) * | 2000-07-06 | 2004-01-13 | 沖電気工業株式会社 | 半導体装置の製造方法 |
US20020117753A1 (en) * | 2001-02-23 | 2002-08-29 | Lee Michael G. | Three dimensional packaging |
SG120858A1 (en) * | 2001-08-06 | 2006-04-26 | Micron Technology Inc | Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same |
US6470594B1 (en) * | 2001-09-21 | 2002-10-29 | Eastman Kodak Company | Highly moisture-sensitive electronic device element and method for fabrication utilizing vent holes or gaps |
US7566587B2 (en) * | 2001-12-03 | 2009-07-28 | Azimuth Industrial Co., Inc. | Method and apparatus for packaging electronic components |
US6660562B2 (en) * | 2001-12-03 | 2003-12-09 | Azimuth Industrial Co., Inc. | Method and apparatus for a lead-frame air-cavity package |
US6882044B2 (en) * | 2002-05-17 | 2005-04-19 | Agilent Technologies, Inc. | High speed electronic interconnection using a detachable substrate |
US6818838B1 (en) * | 2003-03-17 | 2004-11-16 | Unisys Corporation | PCB component placement and trace routing therebetween |
US7358119B2 (en) * | 2005-01-12 | 2008-04-15 | Asat Ltd. | Thin array plastic package without die attach pad and process for fabricating the same |
US7220626B2 (en) * | 2005-01-28 | 2007-05-22 | International Business Machines Corporation | Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels |
TWI569381B (zh) * | 2011-05-27 | 2017-02-01 | 住友電木股份有限公司 | 半導體裝置 |
US9995638B2 (en) * | 2015-04-30 | 2018-06-12 | National Instruments Corporation | Cold-junction-compensated input terminal of a thermocouple instrument |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4423468A (en) * | 1980-10-01 | 1983-12-27 | Motorola, Inc. | Dual electronic component assembly |
US4668032A (en) * | 1982-04-08 | 1987-05-26 | Harris Corporation | Flexible solder socket for connecting leadless integrated circuit packages to a printed circuit board |
US5059557A (en) | 1989-08-08 | 1991-10-22 | Texas Instruments Incorporated | Method of electrically connecting integrated circuits by edge-insertion in grooved support members |
US5047711A (en) | 1989-08-23 | 1991-09-10 | Silicon Connections Corporation | Wafer-level burn-in testing of integrated circuits |
US5200362A (en) * | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5239191A (en) | 1990-01-19 | 1993-08-24 | Kabushiki Kaisha Toshiba | Semiconductor wafer |
JP2848682B2 (ja) * | 1990-06-01 | 1999-01-20 | 株式会社東芝 | 高速動作用半導体装置及びこの半導体装置に用いるフィルムキャリア |
US5126286A (en) | 1990-10-05 | 1992-06-30 | Micron Technology, Inc. | Method of manufacturing edge connected semiconductor die |
US5241133A (en) * | 1990-12-21 | 1993-08-31 | Motorola, Inc. | Leadless pad array chip carrier |
FR2675632B1 (fr) * | 1991-04-18 | 1997-04-30 | Texas Instruments France | Dispositif de conditionnement de circuits integres |
JPH05206314A (ja) * | 1991-11-12 | 1993-08-13 | Nec Corp | 半導体装置 |
US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5804870A (en) | 1992-06-26 | 1998-09-08 | Staktek Corporation | Hermetically sealed integrated circuit lead-on package configuration |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
KR100245257B1 (ko) | 1993-01-13 | 2000-02-15 | 윤종용 | 웨이퍼 수준의 반도체 패키지의 제조방법 |
US5573172A (en) * | 1993-11-08 | 1996-11-12 | Sawtek, Inc. | Surface mount stress relief hidden lead package device and method |
JP2647001B2 (ja) * | 1994-05-31 | 1997-08-27 | 日本電気株式会社 | テープキャリアならびに半導体デバイスの実装構造およびその製造方法 |
US5832600A (en) | 1995-06-06 | 1998-11-10 | Seiko Epson Corporation | Method of mounting electronic parts |
US5731222A (en) | 1995-08-01 | 1998-03-24 | Hughes Aircraft Company | Externally connected thin electronic circuit having recessed bonding pads |
US5880011A (en) | 1996-06-19 | 1999-03-09 | Pacific Trinetics Corporation | Method and apparatus for manufacturing pre-terminated chips |
US5904496A (en) | 1997-01-24 | 1999-05-18 | Chipscale, Inc. | Wafer fabrication of inside-wrapped contacts for electronic devices |
US5888884A (en) | 1998-01-02 | 1999-03-30 | General Electric Company | Electronic device pad relocation, precision placement, and packaging in arrays |
-
1998
- 1998-04-21 US US09/063,817 patent/US6177722B1/en not_active Expired - Lifetime
- 1998-12-16 US US09/216,019 patent/US6004833A/en not_active Expired - Lifetime
-
1999
- 1999-02-24 WO PCT/US1999/003952 patent/WO1999054932A1/en active Search and Examination
- 1999-03-24 TW TW088104633A patent/TW419799B/zh not_active IP Right Cessation
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US6177722B1 (en) | 2001-01-23 |
WO1999054932A1 (en) | 1999-10-28 |
US6004833A (en) | 1999-12-21 |
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