CN102356461B - 半导体装置及其制造方法、电子装置以及电子零件 - Google Patents
半导体装置及其制造方法、电子装置以及电子零件 Download PDFInfo
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Abstract
本发明提供半导体装置和该半导体装置的制造方法、电子装置以及电子零件,提高布线衬底和半导体零件的连接可靠性。本发明的半导体装置具有:布线衬底(11),其表面具有第一电极焊盘(14);电路板(30),其竖立设置在布线衬底(11)之上,且具有用于与第一电极焊盘(14)相连接的布线(31);半导体封装件(20),其设为通过电路板(30)与布线衬底(11)相对置,且其表面具有用于与布线(31)相连接的第二电极焊盘(19)。
Description
技术领域
本发明涉及半导体装置和该半导体装置的制造方法、电子装置以及电子零件。
背景技术
近年来,服务器或个人计算机这样的电子装置在高速化及高性能化等方面实现了显著了发展,伴随于此,用于电子装置的CPU(CentralProcessing Unit:中央处理单元)等半导体元件的大型化进一步发展。
作为半导体元件的安装技术,已知将半导体元件以裸芯片(bare chip)的状态通过焊料凸块(bump)直接安装布线衬底上的倒装片安装法。
另外,还有如下方式的安装方法,为了将半导体元件的微小的电极排列按比例增加到(scale up)布线衬底的电极排列,制造在内插板(interposer)上搭载半导体元件而成的半导体封装件,将该半导体封装件通过焊料凸块安装到布线衬底上的BGA(Ball Grid Array:球阵列封装)。用于BGA方式的半导体封装件还称为BGA型的半导体封装件。
图1的(a)、(b)部分是将BGA型的半导体封装件5安装到布线衬底1上的过程的剖视图。
如图1的(a)部分所示,布线衬底1的一个主面上具有第一电极焊盘2。在该第一电极焊盘2上预先利用丝网印刷印刷有锡膏4。
另一方面,半导体封装件5的主面上的与第一电极焊盘2相对的位置上具有第二电极焊盘6,并且,在该第二电极焊盘6的上表面接合焊料凸块7。
然后,在锡膏4与接触焊料凸块7的状态下,通过对它们进行加热来进行回流,如图1的(b)部分所示,在布线衬底1上安装半导体封装件5。回流之后的焊料凸块7的形状由焊锡的表面张力和半导体封装件5的自重决定,一般成为图示那样的中央膨胀的如鼓那样的形状。
但是,半导体封装件5和布线衬底1因材料的不同而分别具有不同的热膨胀率,若半导体封装件5发热,则因热膨胀率之差而会向焊料凸块7施加应力。该应力集中到焊料凸块7的直径最小部位即各电极焊盘2、6和焊料凸块7的接合部A附近。
反复开通/断开半导体封装件5的电源,反复对接合部A的焊料凸块7施加应力,由此逐渐加深焊料凸块7的金属疲劳。然后,有最终在焊料凸块7生成裂纹而导致接合部A断裂的可能性。
现有技术文献
专利文献
专利文献1:日本特开平5-114627号公报
专利文献2:国际公开第08/114434号小册子
专利文献3:日本特开2001-118876号公报
专利文献4:日本特开平8-236898号公报
专利文献5:日本特表2005-510618号公报
非专利文献
非专利文献1:森田、林、中西、米田,“无铅焊料凸块的高加速试验”,第23次电子器件安装学会春季演讲大会。
发明内容
发明要解决的问题
本发明的目的在于,对于半导体装置和该半导体装置的制造方法、电子装置以及电子零件,提高布线衬底和半导体零件的连接可靠性。
用于解决问题的手段
若采用以下公开的一个观点,则能够提供一种半导体装置,该半导体装置具有:布线衬底,其表面具有第一电极焊盘;电路板,其竖立设置在所述布线衬底之上,且具有与所述第一电极焊盘相连接的布线;半导体零件,其设为隔着所述电路板而与所述布线衬底相对置,且表面具有与所述布线相连接的第二电极焊盘。
另外,若采用以下公开的另一个观点,则能够提供一种电子装置,该电子装置搭载有半导体装置,该半导体装置具有:布线衬底,其表面具有第一电极焊盘,电路板,其竖立设置在所述布线衬底之上,且具有与所述第一电极焊盘相连接的布线,半导体零件,其设为隔着所述电路板而与所述布线衬底相对置,且其表面具有与所述布线相连接的第二电极焊盘。
进而,若采用以下公开的又一个观点,则能够提供一种电子零件,该电子零件具有:布线衬底,其表面具有第一电极焊盘;电路板,其竖立设置在所述布线衬底之上,且该电路板具有连接所述第一电极焊盘和第二电极焊盘的布线,所述第二电极焊盘是指,预定要安装到所述布线衬底上的半导体元件所具有的电极焊盘。
其中,若采用以下公开的再一个观点,则能够提供半导体装置的制造方法,该半导体装置的制造方法具:将电路板竖立设置在布线衬底上的工序,该布线衬底的表面上设有第一电极焊盘;连接所述电路板所具有的布线和所述第一电极焊盘的工序;以使半导体零件隔着所述电路板而与所述布线衬底相对置的方式,在该电路板上装载该半导体零件的工序;连接设在所述半导体零件的表面的第二电极焊盘和所述电路板的所述布线的工序。
附图说明
图1的(a)、(b)部分是利用倒装片安装法将半导体元件安装到布线衬底上的过程的剖视图。
图2是在各实施方式中使用的挠性电路板的俯视图。
图3是沿图2的I-I线的剖视图。
图4的(a)、(b)部分是示出了关于第一实施方式的挠性电路板的使用方法的立体图。
图5是第一实施方式的半导体装置的剖视图。
图6是在各实施方式中使用的布线衬底的俯视图。
图7是在各实施方式中使用的半导体封装件的内插板的俯视图。
图8的(a)、(b)部分是第一实施方式的半导体装置的挠性电路板和其周围的放大剖视图。
图9是第一实施方式的半导体装置的放大俯视图。
图10的(a)~(d)部分是各实施方式的挠性电路板的制造过程的剖视图。
图11的(a)、(b)部分是各实施方式的挠性电路板的制造过程的俯视图。
图12的(a)~(c)部分是使用了第一实施方式的挠性电路板的半导体装置的制造过程的剖视图。
图13是第一实施方式的在内插板和半导体元件之间配置了挠性电路板的情况的剖视图。
图14是示出了关于第二实施方式的挠性电路板的使用方法的立体图。
图15是将第二实施方式的挠性电路板粘合到布线衬底之上而成的电子零件的放大俯视图。
图16是在第三实施方式中使用的三张挠性电路板的放大俯视图。
图17是示出了关于第三实施方式的挠性电路板30的使用方法的立体图。
图18是将第三实施方式的挠性电路板粘合到布线衬底之上而成的电子零件的放大俯视图。
图19的(a)、(b)部分是示出了关于第四实施方式的样品的制造方法的剖视图(其一)。
图20的(a)、(b)部分是示出了关于第四实施方式的样品的制造方法的剖视图(其二)。
图21是第四实施方式的样品的俯视图。
图22的(a)、(b)部分是用于说明关于第四实施方式的样品的连接可靠性的调查方法的剖视图。
图23是示出了第四实施方式的对第二电极焊盘和第三电极焊盘之间的电阻值的测定方法的示意俯视图。
具体实施方式
以下,一边参照附图,一边对本实施方式进行详细的说明。
(1)第一实施方式
图2是在本实施方式中使用的吸收应力用的挠性电路板30的俯视图。
该挠性电路板30包括具有挠性的带状的树脂基材32和嵌入到该树脂基材32中的布线31。树脂基材32的尺寸不特别限定,但在本实施方式中将长度L设定为约40mm,将宽度W设定为约2mm。
布线31形成为在带状的树脂基材32的短边方向上延伸,作为其材料例如使用铜。
在树脂基材32上相隔约1.27mm的间隔形成有多个那样的布线31,且在各布线31之间的树脂基材32上形成有狭缝32b。
图3是沿图2的I-I线的剖视图。
如图3所示,树脂基材32由均由聚酰亚胺构成的第一树脂薄膜38和第二树脂薄膜39层叠而成,且这些树脂薄膜38、39之间嵌入有布线31。
将这些树脂薄膜38、39结合而成的树脂基材32的厚度T不特别限定,但在本实施方式中设定为约0.1mm。
其中,从布线31的两端到约0.5mm的部分的树脂基材32上形成有开口32a,从该开口32a露出布线31的端部。此外,为了防止氧化或提高接合性,也可以对从开口32a露出的部分的布线31实施镀金等表面处理。
图4的(a)、(b)部分是示出了关于该缓和(抵消)应力用的挠性电路板30的使用方法的立体图。
如图4的(a)部分所示,在本实施方式中,准备多个上述的挠性电路板30,并嵌合其各自的各狭缝30a。
由此,如图4的(b)部分所示,各挠性电路板30组合成格子状,成为即使没有支撑各挠性电路板30也可以自己竖立的状态。
此时,为了防止各挠性电路板30的高度产生偏差,优选将狭缝32b的深度设定为各挠性电路板30的宽度W(参照图2)的一半左右。
图5是使用了这样组合的挠性电路板30的半导体装置的剖视图。
该半导体装置10具有布线衬底11和半导体封装件20,该半导体封装件20是作为隔着挠性电路板30而与布线衬底11相对置的半导体零件。
其中,布线衬底11是将由铜构成的布线12和由环氧玻璃树脂构成的绝缘层13交替层叠而成的多层布线衬底,在其最上层的表面上设有由铜构成的第一电极焊盘14。
另外,半导体封装件20,是在内插板16之上搭载CPU等半导体元件21并由封固树脂22封固该半导体元件21和内插板16而成的。
其中,内插板16是由多个由铜构成的布线17和由环氧玻璃树脂构成的绝缘层18交替层叠而成的多层布线衬底,在其最下层和最上层的表面上具有由铜构成的第二以及第三电极焊盘19、24。
另外,半导体元件21具有由铜构成的第四电极焊盘25,并由焊料凸块19电连接且机械连接该第四电极焊盘25和内插板16的第三电极焊盘24。
进一步,在封固树脂22的表面上粘合用于对半导体元件21所产生的热进行高效散热的散热器23。散热器23由导热率良好金属构成,例如由铝构成。
图6是布线衬底11的俯视图。
如图6所示,布线衬底11的平面形状是一边的长度为约110mm的正方形,且除去中央的16个×16个的区域之外的26个×26个的第一电极焊盘14配置为格子状。另外,第一电极焊盘14的大小不特别限定,但在本实施方式中将直径设定为约0.76mm的圆形。
另一方面,图7是半导体封装件20所具有的内插板16的俯视图。
如图7所示,内插板16的平面形状是一边的长度为约40mm的正方形。其中,设在该内插板16上的第二电极焊盘19是直径为约0.76mm的圆形,且排列方式与在图6中示出的第一电极焊盘14相同。
图8的(a)、(b)部分是上述的半导体装置10的挠性电路板30和其周围的放大剖视图。其中,图8的(a)部分是沿挠性电路板30的延伸方向的放大剖视图,图8的(b)部分是沿与挠性电路板30的延伸方向垂直的方向的放大剖视图。
如图8的(a)、(b)部分所示,带状的挠性电路板30竖立设置在布线衬底11之上,且在基板11的横向延伸,使得该挠性电路板30在第一电极焊盘14之上通过。
其中,在挠性电路板30的布线31中,在从树脂基材32的开口32a露出的部分,通过Sn-3Ag-0.5Cu焊料等的第一、第二连接介质41、42,分别与第一、第二电极焊盘14、19机械连接且电连接。
通过这样在开口32a上连接布线31和各连接介质41、42,与没有设置开口32a的情况相比,能够使得布线31和各连接介质41的接触面积增加,从而提高通过电路板30来连接布线衬底11和半导体封装件20的连接可靠性。
此外,各连接介质41、42并不限定于焊料凸块,也可以是导电性粘接剂。该导电性粘接剂例如由环氧树脂、氨酯树脂、硅酮树脂、丙烯酸树脂以及聚酰亚胺树脂等粘合剂和银或铜等导电性填充料混匀而成。
如图8的(b)部分所示,通过这样将挠性电路板30竖立在布线衬底11之上,在布线衬底11或半导体封装件20热膨胀时,能够促使挠性电路板30沿布线衬底11的面内方向D发生变形。
图9是该半导体装置的放大俯视图。此外,在图9中,为了易于观察挠性电路板30的平面布局,而省略了半导体封装件20。
如图9所示,对组合成格子状的多个挠性电路板30与布线衬底11进行对位,使得其布线31位于第一电极焊盘14之上。
若采用以上说明的半导体装置10,则如图8的(a)、(b)部分所示,在布线衬底11和半导体封装件20之间设有挠性电路板30。
若采用该结构,则由挠性电路板30自身变形来吸收因半导体封装件20发热而产生的布线衬底11和半导体封装件20之间的热膨胀差,因而能够防止应力集中到挠性电路板30和各电极焊盘14、19的接合部上。因此,能够降低因应力集中导致的电路板30的布线31与各电极焊盘14、19接合断裂的危险性,从而能够提高电路板30和半导体封装件20的连接可靠性。
特别地,在本实施方式中,将挠性电路板30竖立在布线衬底11之上,因此,如图8的(b)部分所示,能够使挠性电路板30沿布线衬底11的面内方向D变形。由此,能够利用挠性电路板30有效吸收沿方向D的布线衬底11和半导体封装件20之间的热膨胀差,从而能够实现基于挠性电路板30的提高连接可靠性的实效。
接着,对该挠性电路板30的制造方法进行说明。
图10的(a)~(d)部分是挠性电路板30的制造过程的剖视图,图11的(a)、(b)部分则是其俯视图。
为了制造挠性电路板30,首先,如图10的(a)部分所示,在由厚度为约0.25mm的聚酰亚胺构成的第一树脂薄膜38的主面上,利用未图示的粘接剂(厚度为约0.25mm)粘接铜箔33。铜箔33的厚度不特别限定,但在本实施方式中设定为约0.35mm。
此外,作为第一树脂薄膜38的材料也可以使用聚酰亚胺以外的材料,例如环氧、丙烯酸以及酚等。
接着,如图10的(b)部分所示,利用光刻法和湿式蚀刻对铜箔33刻画图形而形成布线31。通过该刻画图形处理得到的布线31的宽度例如为约0.5mm。
接着,如图10的(c)部分所示,预先准备形成有开口32a的第二树脂薄膜39。然后,利用未图示的粘接剂将该第二树脂薄膜39压到第一树脂薄膜38上而进行粘贴,由此得到由各树脂薄膜39、39构成的树脂基材32。
该第二树脂薄膜39的材料不特别限定,可使用由聚酰亚胺、环氧、丙烯酸以及酚中的任一中材料构成的薄膜作为第二树脂薄膜。
在低温下进行各树脂薄膜38、39之间的粘贴的情况下,优选使用丙烯酸以及酚中的任一种材料,来作为这些树脂薄膜的材料。
另外,第二树脂薄膜39的厚度不特别限定,但在本实施方式中是约0.25mm。
其中,如图10的(d)部分所示,利用激光加工在第一树脂薄膜38上形成开口32a,以使布线31的端部从该开口32a露出。
如参照图8的(a)、(b)部分说明的那样,通过以这种方法形成开口32a,能够在开口32a内增加布线31和各连接介质41、42的接触面积。
此外,在该例中,在各树脂薄膜38、39的双方上形成了开口32a,但即使仅在这些树脂薄膜38、39的任一方形成开口32a,也能够增加布线31和各连接介质41、42的接触面积。
图11的(a)部分是完成上述工序之后的树脂基材32的放大俯视图,之前的图10的(d)部分相当于图11的沿(a)部分的II-II线的剖视图。
此后,如图11的(b)部分所示,利用冲压,在多个布线31之间的树脂基材32上以机械方式形成狭缝32b。
根据以上的工序,完成了缓和应力用的挠性电路板30的基本结构。
在制造半导体装置时,制造多个这样的挠性电路板30,并如图3的(a)、(b)部分示出那样将各个该挠性电路板30组合成格子状。
图12的(a)~(c)部分是在使用这样组合的挠性电路板30来制造半导体装置的过程的剖视图。此外,在图12的(a)部分~图12的(c)部分中,对于在图8的(a)、(b)部分说明的相同的要素,标注与这些附图相同的附图标记,并在以下的说明中省略其说明。
为了制造半导体装置10,首先,如图12的(a)部分所示,在布线衬底11的第一电极焊盘14上预先印刷Sn-3Ag-0.5Cu焊料来作为第一连接介质41。
此外,也可以预先在第一电极焊盘14之上搭载焊焊料凸块作为第一连接介质41,以代替这样的印刷法。
接着,如图12的(b)部分所示,对第一电极焊盘14和上述挠性电路板30进行对位,在布线衬底11之上搭载组合成格子状的多个挠性电路板30。通过这样组合格子状,即使不支撑各电路板30,各电路板30也能够在布线衬底11之上维持自己竖立的状态。
此后,将第一连接介质41中的焊料加热到其熔点即220℃以上的温度来进行回流(reflow)。
此后,若第一连接介质41被冷却而固化,则挠性电路板30的布线31和第一电极焊盘14通过第一连接介质41连接,并且,挠性电路板30暂时被第一连接介质41固定在布线衬底11上。
由此,得到在布线衬底11之上竖立设置挠性电路板30的电子零件40。
接着,如图12的(c)部分所示,在电子零件40之上搭载半导体封装件20。此时,在半导体封装件20的第二电极焊盘19上预先印刷有Sn-3Ag-0.5Cu焊料作为第二连接介质42,且半导体封装件20通过该第二连接介质42搭载在挠性电路板30上。
此外,也可以在第二电极焊盘19之上搭载焊焊球来作为第二连接介质42,而不利用印刷法形成第二连接介质42。
并且,在该状态下将第二连接介质42中的焊料加热到其熔点即220℃以上的温度来进行回流。
此后,若第二连接介质42被冷却而固化,则挠性电路板30的布线31和第二电极焊盘19通过第二连接介质42连接,并且,半导体封装件20被第二连接介质42固定在挠性电路板30上。
通过以上处理,能够得到本实施方式的半导体装置的基本结构。
此外,在上述中使用焊料作为第一、第二连接介质41、42,但也可以使用导电性粘接剂,以代替该第一、第二连接介质41、42。
并且,在上述中,在半导体封装件20和布线衬底11之间配置了用于吸收应力的挠性电路板30,但设置电路板30的部位不限定于此。
例如,如图13的放大剖视图所示,为了连接内插板16和半导体元件21,也可以在它们之间配置挠性电路板30。此外,在图13中,对与图5相同的要素标注与图5相同的附图标记,并在以下的说明中省略其说明。
在该情况下,在各电极焊盘24、25之上预先设置焊料或导电性粘接剂,以作为第一、第二连接介质41、42,电路板30通过该连接介质41、42而与各电极焊盘24、25电连接且机械连接。
由此,能够由挠性电路板30吸收半导体元件21和内插板16之间的热膨胀差,从而能够提高半导体元件21和内插板16的连接可靠性。
这样,在本实施方式中,通过将挠性电路板30竖立设置在半导体基板11之上,能够提高半导体封装件20或半导体元件21等半导体零件和布线衬底11的连接可靠性。并且,通过将该半导体装置搭载到服务器或个人计算机等电子装置上,能够更加促进电子装置的高性能化。
(2)第二实施方式
本实施方式与第一实施方式的不同点仅是挠性电路板30的组合方式不同,这以外的方式与第一实施方式相同。
图14是示出了关于本实施方式的挠性电路板30的使用方法的立体图。
如图14所示,在本实施方式中,将一张挠性电路板30卷成螺旋状。
图15是将该挠性电路板30粘合到布线衬底11之上而成的电子零件50的放大俯视图。
如图15所示,将挠性电路板30竖立设置在布线衬底11之上,以使布线31在第一电极焊盘14之上通过,并且通过在适当的位置上弯曲该挠性电路板30来卷成螺旋状。
通过这样卷成螺旋状,仅用一张挠性电路板30也能够使其蜿蜒贴附在全部的第一电极焊盘14上。因此,易于加工挠性电路板30,而不需如第一实施方式那样准备多个挠性电路板30,或者为了组合各电路板30而在该各电路板30上形成狭缝32b。
并且,通过在适当的位置上弯曲挠性电路板30,能够与第一电极焊盘14的平面布局无关地使挠性电路板30蜿蜒贴附在该电极焊盘14上,从而能够提高挠性电路板30的通用性。
(3)第三实施方式
本实施方式与第一实施方式的不同点仅是挠性电路板30的组合方式不同,这以外的方式与第一实施方式相同。
图16是在本实施方式中使用的三张挠性电路板30的放大俯视图。
如图16所示,三张挠性电路板30中的两张挠性电路板30仅从其一侧长边切入狭缝32b,剩下的一张挠性电路板30则从两侧长边切入狭缝32b。
使用时,使这三张挠性电路板30向如图中箭头的方向组合。
图17是示出了关于本实施方式的挠性电路板30的使用方法的立体图。
如图17所示,在本实施方式中,通过嵌合在图15中示出的三张挠性电路板30的各狭缝32b,以狭缝32b为中心将各挠性电路板30组合成放射状。
图18是将这样组合成放射状的挠性电路板30粘合到布线衬底11之上而成的电子零件60的放大俯视图。
如图18所示,将各挠性电路板30竖立设置在布线衬底11之上,以使布线31在第一电极焊盘14上通过。
这样的放射状的方式,也与第一实施方式同样地,通过各挠性电路板30变形,能够由挠性电路板30吸收布线衬底11和半导体封装件20之间的热膨胀差,从而能够提高布线衬底11和半导体封装件20的连接可靠性。
(4)第四实施方式
在本实施方式中,对本申请的发明者所进行的调查进行说明。在该调查中,调查的内容是:通过如第一实施方式那样在布线衬底和半导体封装件之间设置挠性电路板30,该布线衬底和半导体封装件的连接可靠性能够提高到何种程度。
图19及图20是示出了关于用于该调查的样品的制造方法的剖视图。此外,在这些图中,对于在第一实施方式中说明的相同的要素,标注与第一实施方式相同的附图标记,并在以下的说明中省略其说明。
为了制造该样品,首先,如图19的(a)部分所示,准备挠性电路板30和封装基板70。
其中,封装基板70在调查时模拟发挥半导体封装件发挥功能,在树脂基材74的两面具有第一电极焊盘71和第二电极焊盘72。其中,这些电极焊盘71、72通过形成在树脂基材74上的通孔70a而相互连接。
另外,挠性电路板30和封装基板70通过焊料等的第一连接介质75而电连接且机械连接。
在这里,在本调查中,挠性电路板30所具有的多个布线31中,仅左右两端的布线31与第一电极焊盘71相连接,其余的布线31不与封装基板70连接。
接着,如图19的(b)部分所示,准备在树脂基材82之上形成有多个第三电极焊盘83的布线衬底80。其中,在多个第三电极焊盘83中,仅在左右两端的第三电极焊盘83之上,利用印刷法等印刷有焊料凸块膏来作为第二连接介质87。
接着,如图20的(a)部分所示,对挠性电路板30的两端的布线31和布线衬底80的两端的第三电极焊盘83进行对位之后,将挠性基板30竖立在第二连接介质87之上。
此后,如图20的(b)部分所示,通过对第二连接介质87进行回流来使其熔解,通过第二连接介质87将挠性电路板30的布线31和布线衬底80的第三电极焊盘83电连接且机械连接。
此外,作为各连接介质75、87,使用了Sn-37Pb焊料。
通过以上的处理,完成了样品S的基本结构。
图21是该样品S的俯视图,之前的图20的(b)部分相当于沿图21的III-III线的剖视图。
如图21所示,在该样品S中,组合四张挠性电路板30来将其竖立设置在封装基板70的边缘。
这些挠性电路板30中,对封装基板70和布线衬底80双方进行电连接且机械连接的挠性电路板30,仅是在图中上下相对的两张挠性电路板30。在连接部B上,该两张挠性基板30如上述那样通过第一、第二连接介质75、87而分别与封装基板70和布线衬底80相连接
利用这样的样品S,本申请的发明者如下进行了连接可靠性的调查。
图22的(a)、(b)部分是用于说明关于连接可靠性的调查方法的剖视图。
进行调查时,以封装基板70作为下侧,将样品S搭载在支撑体90上。在支撑体90上设有凹部90a,挠性电路板30和封装基板70容纳在该凹部90a内。
其中,以0.5Hz的频率进行了如下的循环处理,如图22的(a)部分那样利用按压件91将布线衬底80和封装基板70向铅直下方压下1.5mm,再如图22的(b)部分那样使其返回初始位置。与此同时,测定了第二电极焊盘72和第三电极焊盘83之间的电阻值R。在室温为约25度的室内进行了该测定。这样的调查还称为弯曲(bending)试验。
与温度循环试验相比,弯曲试验是可期待作为能在短时间测定出基于疲劳的接合部的寿命的方法。
图23是示出了上述的电阻值R的测定方法的示意俯视图。
如图23所示,在封装基板70的表面设有与第二电极焊盘72相连接的两个第一试验焊盘79。另外,在布线衬底80的表面设有与第三电极焊盘83电连接的两个第二试验焊盘89。
在测定电阻值R时,一边利用直流电流发生装置96在两个第一试验焊盘79中的一个第一试验焊盘79和两个第二试验焊盘89中的一个第二试验焊盘89之间施加恒定电流I,一边利用电压计96来测定在焊盘83和72之间产生的电压V,并根据R=V/I求出电阻值R。
在本调查中,在从开始试验起,电阻值R比初始值上升了1%的时间点上,视为封装基板70和布线衬底80之间的连接部B(参照图21)被破坏。其结果,与如图1的(b)部分那样通过焊料凸块7来连接各基板70、80的情况相比,确认了样品S的连接部B的寿命是前者的8倍以上。
由此,证实了如样品S那样利用挠性基板30连接封装基板70和布线衬底80,有效提高了各基板70,80的连接可靠性。
Claims (15)
1.一种半导体装置,其特征在于,具有:
布线衬底,其表面具有第一电极焊盘;
电路板,其竖立设置在所述布线衬底之上,且具有与所述第一电极焊盘相连接的布线;
半导体零件,其隔着所述电路板与所述布线衬底相对置,且该半导体零件的表面具有与所述布线相连接的第二电极焊盘;
所述电路板设有多个,并在各个所述电路板上分别形成有狭缝,
通过使各个所述电路板的各所述狭缝相嵌合来组合多个所述电路板,从而使所述电路板竖立设置在所述布线衬底之上。
2.根据权利要求1记载的半导体装置,其特征在于,
所述电路板是挠性电路板。
3.根据权利要求1记载的半导体装置,其特征在于,
多个所述电路板组合成格子状或放射状。
4.根据权利要求2记载的半导体装置,其特征在于,
所述布线通过焊料或导电性粘接剂与所述第一电极焊盘及所述第二电极焊盘相连接。
5.根据权利要求4记载的半导体装置,其特征在于,
所述挠性电路板具有第一树脂薄膜和第二树脂薄膜,在所述第一树脂薄膜的一个主面上形成有所述布线,所述第二树脂薄膜形成在所述布线和所述第一树脂薄膜之上;
在所述布线的端部上的所述第一树脂薄膜和所述第二树脂薄膜中的至少一个树脂薄膜上形成有用于使所述布线露出的开口,所述布线的所述端部与所述第一电极焊盘或者所述第二电极焊盘相连接。
6.根据权利要求2记载的半导体装置,其特征在于,
所述挠性电路板的平面形状是带状。
7.根据权利要求6记载的半导体装置,其特征在于,
所述布线在带状的所述挠性电路板的短边方向上延伸。
8.一种电子装置,其特征在于,该电子装置搭载半导体装置,
该半导体装置具有:
布线衬底,其表面具有第一电极焊盘,
电路板,其竖立设置在所述布线衬底之上,且具有与所述第一电极焊盘相连接的布线,
半导体零件,其隔着所述电路板与所述布线衬底相对置,且该半导体零件的表面具有与所述布线相连接的第二电极焊盘;
所述电路板设有多个,并在各个所述电路板上分别形成有狭缝,
通过使各个所述电路板的各所述狭缝相嵌合来组合多个所述电路板,从而使所述电路板竖立设置在所述布线衬底之上。
9.根据权利要求8记载的电子装置,其特征在于,
多个所述电路板组合成格子状或放射状。
10.一种电子零件,其特征在于,具有:
布线衬底,其表面具有第一电极焊盘,
电路板,其竖立设置在所述布线衬底之上,且该电路板具有连接所述第一电极焊盘和第二电极焊盘的布线,所述第二电极焊盘是指,预定要安装到所述布线衬底上的半导体元件所具有的电极焊盘;
所述电路板设有多个,并在各个所述电路板上分别形成有狭缝,
通过使各个所述电路板的各所述狭缝相嵌合来组合多个所述电路板,从而使所述电路板竖立设置在所述布线衬底之上。
11.根据权利要求10记载的电子零件,其特征在于,
多个所述电路板组合成格子状或放射状。
12.一种半导体装置的制造方法,其特征在于,具有:
具有准备多个电路板并在各个所述电路板上分别形成狭缝的工序,
将电路板竖立设置在布线衬底上的工序,该布线衬底的表面上设有第一电极焊盘,
连接所述电路板所具有的布线和所述第一电极焊盘的工序,
以使半导体零件隔着所述电路板与所述布线衬底相对置的方式,在该电路板上装载该半导体零件的工序,
连接所述电路板的所述布线和设在所述半导体零件的表面上的第二电极焊盘的工序;
将所述电路板竖立设置在所述布线衬底之上的工序,是在通过使各个所述电路板的各所述狭缝相嵌合来组合了多个所述电路板的状态下进行的。
13.根据权利要求12记载的半导体装置的制造方法,其特征在于,
在连接所述布线和所述第一电极焊盘的工序中,通过第一连接介质来连接所述布线和所述第一电极焊盘。
14.根据权利要求12或13记载的半导体装置的制造方法,其特征在于,
在连接所述布线和所述第二电极焊盘的工序中,通过第二连接介质来连接所述布线和所述第二电极焊盘。
15.根据权利要求12记载的半导体装置的制造方法,其特征在于,
将所述电路板竖立设置在所述布线衬底之上的工序,是在将多个所述电路板组合成格子状或放射状的状态下进行的。
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2009
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- 2009-10-15 JP JP2011504709A patent/JP5590027B2/ja not_active Expired - Fee Related
- 2009-10-15 EP EP09841905.4A patent/EP2410562B1/en not_active Not-in-force
- 2009-10-15 WO PCT/JP2009/067856 patent/WO2010106703A1/ja active Application Filing
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2011
- 2011-08-18 US US13/212,467 patent/US9318425B2/en not_active Expired - Fee Related
-
2016
- 2016-03-07 US US15/062,477 patent/US9565755B2/en not_active Expired - Fee Related
- 2016-03-07 US US15/062,480 patent/US9585246B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
US20110299255A1 (en) | 2011-12-08 |
JPWO2010106703A1 (ja) | 2012-09-20 |
EP2410562A1 (en) | 2012-01-25 |
US9565755B2 (en) | 2017-02-07 |
US9318425B2 (en) | 2016-04-19 |
US20160192498A1 (en) | 2016-06-30 |
US20160192479A1 (en) | 2016-06-30 |
CN102356461A (zh) | 2012-02-15 |
JP5590027B2 (ja) | 2014-09-17 |
EP2410562B1 (en) | 2016-04-13 |
US9585246B2 (en) | 2017-02-28 |
EP2410562A4 (en) | 2014-09-24 |
WO2010106703A1 (ja) | 2010-09-23 |
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