201003858 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件絕緣被覆結構及其製 程，尤指一種單一晶粒尺寸半導體元件絕緣被覆結構及其 製程。 【先前技術】 按，半導體封裝提供積體電路保護、散熱、及電路導 通等功能，習知技術除高階封裝技術，如球柵陣列封裝 (Bal 1 Grid Array，BGA )、覆晶封裝（FI ip-Chip，FC)、 及多晶片模組（Mu 11 i Ch i p Modu 1 e，MCM)，最常用的還是 導線架封裝方式，其主要為黏晶（Die Bond)、焊線（Wired Bond)、封裝（Molding)、及印字（Marking)等封裝過程。 如，中華民國專利證號I 2 4 9 2 ◦ 8「晶圓級封裝 製程與晶圓級晶粒尺寸封裝結構」，係提供一晶圓，該晶圓 具有一第一表面與相對於該第一表面之一第二表面及至少 一切割道；在該晶圓之該第一表面上形成多數個盲孔，其 中該晶圓具有多數個第一接墊，且每一該些盲孔的位置係 分別對應於該些第一接墊其中之一的位置；在該些盲孔内 形成多數個導電柱 '其中每一該些導電柱的一端係分別與 該些接墊其中之一電性連接；在該晶圓之該第一表面上配 置多數個膠框；將一基板配置於該些膠框上，其中該基板 與該晶圓之間係藉由該些膠框維持一間隙；以及研磨該晶 圓，以暴露出每一該些導電柱的另一端。其中，該些第二 接墊上形成多數個銲球；該晶圓之該第二表面上形成一重 配線路層；該重配線路層上形成多數個銲球，且該些銲球 係經由該重配線路層電性連接至該些第二接墊。 6 201003858 然而，上述習知採用導線架封裝，利用黏晶、焊線、 及封裝等，使得封裝製程繁瑣複雜且耗費時間，造成成本 提高。 緣是，本發明人有感上述缺失之可改善，且依據多年 來從事此方面之相關經驗，悉心觀察且研究之，並配合學 理以及被動元件製程之運用，而提出一種設計合理且有效 改善上述缺失之本發明。 【發明内容】 因此本發明之目的在於提供一種單一晶粒尺寸半導體 元件絕緣被覆結構及其製程，達到簡化製程及降低成本的 目的。 根據本發明之上述目的，本發明提出一種單一晶粒尺 寸半導體元件絕緣被覆結構，包括：一單一晶粒尺寸半導 體元件，該單一晶粒尺寸半導體元件具有一前側面、一後 側面、一左侧面、一右侧面、一底面、及一上表面，該單 一晶粒尺寸半導體元件之該上表面具有二金屬墊；以及一 絕緣被覆層，該絕緣被覆層覆蓋於該單一晶粒尺寸半導體 元件之該前侧面、該後侧面、該左侧面、該右侧面、及該 底面。 本發明另提出一種單一晶粒尺寸半導體元件絕緣被覆 製程，包括下列步驟：首先提供一單一晶粒尺寸半導體元 件及一治具；將該單一晶粒尺寸半導體元件之上表面貼附 於該治具；然後執行一絕緣被覆製程，一起將該治具、及 該單一晶粒尺寸半導體元件放置於一鍍膜設備，形成一絕 緣被覆層於該單一晶粒尺寸半導體元件上，藉由該治具遮 蔽該單一晶粒尺寸半導體元件之上表面，該單一晶粒尺寸 7 201003858 半導體元件之上表面定義一金屬引線區域（Metal Wire Area)，該金屬引線區域形成二金屬墊（Metal Pad);接著 一起將該治具、及該單一晶粒尺寸半導體元件從該鍍膜設 備取出，隨後分離該治具與該單一晶粒尺寸半導體元件； 隨後將該單一晶粒尺寸半導體元件之二端形成一導電層， 該導電層覆蓋於該絕緣被覆層、及該二金屬墊；以及最後 將該單一晶粒尺寸半導體元件之二端形成一電鍍層，該電 鍍層包覆於該導電層。 本發明係具有以下有益效果： (一） 利用被動元件之製程，可以得到相同的可靠度，但 是尺寸較小之半導體元件，舉例說明，單一晶粒的大小已 經可以輕易製作到1 . 〇 m m x 0 . 5 m m x 0 . 5 m m，甚 至 0· 5 m m x ◦ . 2 5 m m x 〇 . 2 5 m m，保護該單一晶 粒尺寸半導體元件不受環境影響，如水氣、或灰塵等其他 異物影響。 (二） 利用被動元件製程之治具、及設計，不僅簡單化半 導體元件封裝製程，且同時在該單一晶粒尺寸半導體元件 上形成被動元件採用之端電極與具備焊接介面之電鍍層， 用以與其他基板電性連接，節省了精密封裝設備之費用， 並降低製程之難度。 為了使本發明之敘述更加詳盡與完備，以下發明内容 中，提供許多不同的實施例或範例，可參照下列描述並配 合圖式，用來暸解在不同實施例中的不同特徵之應用。 【實施方式】 請參照第一圖所繪示，本發明提供一種單一晶粒尺寸半 導體元件封裝製程S 1 〇 〇，包括下列步驟：流程步驟S 1 8 201003858[Technical Field] The present invention relates to a semiconductor element insulating coating structure and a process thereof, and more particularly to a single grain size semiconductor element insulating coating structure and a process thereof. [Prior Art] According to the semiconductor package, the integrated circuit provides functions such as integrated circuit protection, heat dissipation, and circuit conduction. In addition to high-order packaging technologies, such as Ball Grid Array (BGA) and flip chip package (FI ip) -Chip, FC), and multi-chip module (Mu 11 i Ch ip Modu 1 e, MCM), the most commonly used is the lead frame package, which is mainly Die Bond, Wired Bond, Packaging processes such as packaging and marking. For example, the Republic of China Patent No. I 2 4 9 2 ◦ 8 "Wafer Level Packaging Process and Wafer Level Grain Size Package Structure" provides a wafer having a first surface and opposite to the first a second surface of the surface and at least one scribe line; forming a plurality of blind holes on the first surface of the wafer, wherein the wafer has a plurality of first pads, and the positions of each of the blind holes Corresponding to a position of one of the first pads; forming a plurality of conductive pillars in the blind holes, wherein one end of each of the conductive pillars is electrically connected to one of the pads a plurality of plastic frames are disposed on the first surface of the wafer; a substrate is disposed on the plastic frames, wherein a gap is maintained between the substrate and the wafer by the plastic frames; and grinding The wafer is exposed to expose the other end of each of the conductive pillars. Wherein the plurality of solder balls are formed on the second pads; a re-wiring circuit layer is formed on the second surface of the wafer; a plurality of solder balls are formed on the re-wiring circuit layer, and the solder balls are passed through the weight The circuit layer is electrically connected to the second pads. 6 201003858 However, the above-mentioned conventional use of the lead frame package, using the die bonding, the bonding wire, and the packaging, etc., makes the packaging process complicated and time consuming, resulting in an increase in cost. The reason is that the inventors have felt that the above-mentioned defects can be improved, and based on years of experience in this field, carefully observed and studied, and with the use of academic and passive component processes, a reasonable design and effective improvement of the above is proposed. The invention is missing. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a single-grain size semiconductor device insulating coating structure and a process thereof for the purpose of simplifying the process and reducing the cost. In accordance with the above objects of the present invention, the present invention provides a single grain size semiconductor device insulating coating structure comprising: a single grain size semiconductor device having a front side, a back side, and a left side a top surface, a bottom surface, a bottom surface, and an upper surface, the upper surface of the single grain size semiconductor device having a second metal pad; and an insulating coating layer covering the single grain size semiconductor device The front side, the rear side, the left side, the right side, and the bottom surface. The present invention further provides a single grain size semiconductor device insulating coating process, comprising the steps of: first providing a single grain size semiconductor component and a jig; attaching the upper surface of the single die size semiconductor component to the fixture And then performing an insulating coating process, placing the fixture and the single-grain size semiconductor component together in a coating device to form an insulating coating layer on the single-grain-size semiconductor component, and shielding the fixture by the fixture a single grain size semiconductor device upper surface, the single grain size 7 201003858 The upper surface of the semiconductor device defines a metal wire region (Metal Wire Area), the metal lead region forms a metal pad (Metal Pad); The fixture, and the single-grain size semiconductor component are removed from the coating apparatus, and then the fixture and the single-grain-size semiconductor component are separated; then the two ends of the single-grain-size semiconductor component are formed into a conductive layer, the conductive a layer covering the insulating coating layer and the two metal pads; and finally the single crystal ruler Two ends of a semiconductor element formed of a plating layer, the plating layer coated on the electrically conductive layer. The invention has the following beneficial effects: (1) The same reliability can be obtained by the process of the passive component, but the semiconductor component with a small size, for example, the size of a single die can be easily fabricated to 1. 〇mmx 0 5 mmx 0 . 5 mm, even 0·5 mmx ◦ . 2 5 mmx 〇. 2 5 mm, protects the single-grain size semiconductor component from environmental influences such as moisture, dust or other foreign matter. (2) using the fixture and design of the passive component process, not only simplifying the semiconductor component packaging process, but also forming a terminal electrode for the passive component and a plating layer having the soldering interface on the single-grain size semiconductor component for Electrical connection with other substrates saves the cost of precision packaging equipment and reduces the difficulty of the process. In order to make the description of the present invention more detailed and complete, various embodiments or examples are provided in the following description, and the following description and the accompanying drawings are used to understand the application of the different features in different embodiments. [Embodiment] Please refer to the first figure, the present invention provides a single-grain size semiconductor device packaging process S 1 〇 , comprising the following steps: process step S 1 8 201003858
0 2、流程步驟S 1 〇 4、流程步驟s 1 〇 6、流程步驟S 1 Ο 8、流程步驟S 1 1 〇、以及流程步驟1 1 2。 流程步驟S 1 〇 2 请參照第二圖，首先提供一單一晶粒尺寸半導體元件1 〇 0，該單一晶粒尺寸半導體元件1 〇 〇為一立方體，該立 方體具有六面係由前侧面1 0 1、後側面丄0 2、左側面工 0 3、右側面1〇 4、底面1 〇 5、及上表面1 〇 6所組成， 該立方體之長寬高尺寸約為〇.6mmx〇.3mmX〇.5m f m、UmmxO.SmmUmm、或 l.6mmx〇.8m m χ 〇 . 5 m m。 請參照第三圖，然後提供一治具2 〇 〇，該治具2 〇 〇 係由使用者自行設計。 流程步驟S 1 〇 4 將該單一晶粒尺寸半導體元件丄〇 〇置放該治具2 〇 〇 上，使該單一晶粒尺寸半導體元件丄◦◦之上表面丄〇 6貼 附於該治具200上表面。 ' ^ 流程步驟S1〇6 〇然後執行一絕緣被覆製程，一起將該治具2 0 〇、及該 單一晶粒尺=半導體元件工〇 〇放置於一鐘膜設備（未^ 不）’請芩照第四圖，形成一絕緣被覆層丄丄〇於該單—晶粒 =半導體it件1 Q ◦上，該絕緣被覆層丄2 ◦可以是有機 冋刀子塗料、氧化矽、或多晶矽，該絕緣被覆層1 1 〇覆罢 於該單一晶粒尺寸半導體元件i ◦ 〇之前側面丄〇 2、後ς 面1 0 2、左側面：L 0 3、右側面丄〇 4、及底面丄〇 5， 該絕緣被覆層1 1 0的厚度介於約1至5 0㈣，可足以保 201003858 護讀單一晶粒尺寸半導體元件1〇〇。 藉由該治具2 0 0遮蔽該單一晶粒尺寸半導體元件1 〇 0之忒上表面1 〇 6，該單一晶粒尺寸半導體元件丄〇 〇之 上表面1 0 6定義形成一金屬引線區域(Metai Wire Area) 1 0 6 a，請參照第五圖，該金屬引線區域丄〇 6 a在進行絕 緣被覆製程前，該金屬引線區域工〇 6 a已具有二金屬塾 (Metal Pad)l 2 〇，該二金屬墊1 2 〇用以與其他基板電性 連接，形成该些金屬墊1 2 0的方法為半導體製程常用的技 ί 術如半導體曝光顯影（Lithography)、及金屬蝕刻（Metal Etching)，不是本發明重點，故不在此詳述。 流程步驟S 1 〇 8 接著將该治具2 〇 〇、及該單一晶粒尺寸半導體元件工 0 ϋ起從該絕緣被覆設備取出，隨後分離該治具2 0 0與 該單一晶粒尺寸半導體元件丄〇 〇。 流程步驟S 1 1 0 =麥,知第六圖，隨後將該單一晶粒尺寸半導體元件1〇 〇 0之二端沾附銀膠後進行乾燥（drying)或固化(curmg)或燒附 (Firing)處理’用以形成一導電層，在本實施例中，該導電層 端電極1 3 0，該端電極1 3 0覆蓋該絕緣被覆層1 1 ◦及該些金屬墊1 2 0。 流程步驟S 1 1 2 知第七圖，最後將該單一晶粒尺寸半導體元件1 0 之一端電錄以形成—電鍍層1 4 Q，該電艘層1 4 0包含 錫’該電鍍層“ 0包覆於該端電極1 3 0，完成-早BS粒尺寸半導體元件絕緣被覆結構1 〇 〇 a。 10 201003858 請參照第-圖所緣示，本發明提供—種單一晶粒尺寸 半導體元件封裝製程S100,包括下列步驟：流程步驟 5 1 0 2、流程步驟s 1 〇 4、流程步驟s丄〇 6、流程 步驟S 1 〇 8、流程步驟s工工〇、以及流程步驟工丄2。 流程步驟S 1 〇 2 ，參照第。二圖’首先提供—單—晶粒尺寸半導體元件 )0 0，该早一晶粒尺寸半導體元件丄〇 〇為一立方體， 該立方體具有六面係由前側面1◦丄、後側面丄◦2、左 2 3、右側面1 0 4、底面1 0 5、及上表面1 0 6 ^且成，該立方體之長寬高尺寸約為0.6 mmxO ·3 m ^ '5mm' 1-〇mmx〇.5mmx〇.5min'^l 6mmx〇.8mmx〇 5mm。 . rv往照第三圖’然後提供—治具2 Q Q，該治具2 Ο 〇係由使用者自行設計。 流程步驟S 1 〇 4 η η將該單—晶粒尺寸半導體元件1 0 Q置放該治具2 。Α肚：使該單—晶粒尺寸半導體元件10◦之上表面1 06貼附於該治具2 GO上表面。 流程步驟S 1 〇 6 二，執仃一絕緣被覆製程，一起將該治具2 〇 〇、及 半導體元件1 0 ◦放置於一鍍膜設備（未 晶敍只弟四圖，形成—絕緣被覆層1 1 0於該單— :有機高4:二件30 ，該絕緣被覆層11 〇可以 1 〇覆蓋於該二：::夕：或姆，該絕緣被覆層1 早日日粒尺寸半導體元件1 〇 〇之前側面工 11 201003858 0 1、後侧面1 〇 2、左侧面1 ο 3、右側面1 〇 4、及 底面1 0 5，該絕緣被覆層1 1 〇的厚度介於約1至5 0 /z m，可足以保護該單一晶粒尺寸半導體元件1 ◦ 〇。 藉由該治具2 ◦ 0遮蔽該單一晶粒尺寸半導體元件 1 0 0之該上表面1 〇 6，該單一晶粒尺寸半導體元件1 0 0之上表面1 〇 6定義形成一金屬引線區域（Metal Wire Area) 1 〇 6 a ’請參照第五圖，該金屬引線區域1 0 6 a在進行絕緣被覆製程前，該金屬引線區域1 〇 6 a Γ 已具有二金屬墊(Metal Pad)l 2 〇，該二金屬墊1 2 0用 以與其他基板電性連接’形成該些金屬墊1 2 〇的方法為 半導體製程常用的技術，如半導體曝光顯影 (Lithography)、及金屬姓刻（Metal Etching)，不是本發明重 點’故不在此詳述。 流程步驟S 1 〇 8 接著將該治具2 〇 〇、及該單一晶粒尺寸半導體元件 1 0 0 —起從該絕緣被覆設備取出，隨後分離該治具2 〇 (,f 0與该單一晶粒尺寸半導體元件1 〇 ◦。 流程步驟s 1 1 〇 β芩,日、?、第六圖，隨後將該單一晶粒尺寸半導體元件1 ρ 0之二端沾附銀膠後進行乾燥（drying)或固化或 、二附(Fmng)處理，用以形成-導電層，在本實施例中，該 稱一端電極1 3 〇，該端電極1 3 ◦覆蓋該絕緣 破伋層1 1 〇及該些金屬墊1 2 0。 流程步驟s 1 1 2 ^第七圖，最後將該單一晶粒尺寸半導體元件1 12 201003858 〇 〇之一端電鑛以形成一電鍍屛1 4 π 包含鎳、及錫，該電鍍層14〇包覆於層140 元成-單-晶粒尺寸半導體元件絕緣被覆：：'13 〇， 本發明與習知比較之下可達到下列效〇〇a。 (一）由於不使用一般半導體元件之 。焊”後封裝)，而利用被動元=以利用黏 相同可靠度’但是尺寸較小之半導 ’可以得到 件的大小已經可以輕易製作到i ·〇 。例如—般被動元 mm^^.5mmxQ25mm $mmx〇.5 習知半導體封裝接腳所無法輕易 υ·! 5 一這是 層1 1 ◦、該端電極i 3 ◦及該電鍍 广該絕緣被覆 單-晶粒尺寸半導體元件封裝絕曰保護該 環境影響，如水氣'或灰⑽其他異不受 (二）利用該治具2 Q 〇及其設計 ^ 封裝保護製程，且同時在該 2化半導體元件 成被動元件當g夕# + 尺寸半導體元件上形 成被勁兀件吊見之端電極2 3 仟上形 層“Ο,用以與其他基板電性連接、。備二:：面之電鑛 業界習知之導線架封裝（利 =使用半導體 成與其他基板電性連結。以7 來達 降低製程之難度。 山玎忒叹備之費用，並 雖然本發明已以—較 用以限定本發明，任何露如上，然其並非 之精神和範圍内，可〆易在不股離本發明 在以下本案之變化或修飾，皆可涵蓋 設計，不僅簡單化半導體2，及其 一晶粒尺寸半導體元件上 ’、又衣壬，且同時在該單 件上形成被動元件常見之端電極i 3 〇 33 201003858 與具備焊接介面之電鍍層1 4 0，用以與其他基板電性連 接。而不必使用半導體業界習知之導線架封裝（利用黏晶、焊 線、然後封裝）來達成與其他基板電性連結。節省了精密封裝 設備之費用，並降低製程之難度。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，可輕易思及之變化或修飾，皆可涵蓋在以下本案之 申請專利範圍。0 2. Process step S 1 〇 4. Process step s 1 〇 6. Process step S 1 Ο 8, process step S 1 1 〇, and process step 1 1 2 . Process Step S 1 〇 2 Referring to the second figure, a single grain size semiconductor device 1 〇0 is first provided. The single grain size semiconductor device 1 is a cube having a six-sided system from the front side 10 1. The rear side 丄0, the left side work 0 3, the right side face 1〇4, the bottom side 1 〇5, and the upper surface 1 〇6, the length, width and height of the cube are about 6.6mmx〇.3mmX〇 .5m fm, UmmxO.SmmUmm, or l.6mmx〇.8m m χ 〇. 5 mm. Please refer to the third figure, and then provide a fixture 2 〇 〇, which is designed by the user. Step S 1 〇4, placing the single-grain-size semiconductor component on the fixture 2, and attaching the upper surface 6 of the single-grain-size semiconductor component to the fixture 200 upper surface. ' ^ Process step S1〇6 〇 Then perform an insulation coating process, together with the fixture 20 〇, and the single die size = semiconductor component process placed on a film device (not ^) According to the fourth figure, an insulating coating layer is formed on the single-grain=semiconductor member 1 Q ,, and the insulating coating layer 丄2 ◦ may be an organic enamel coating, yttrium oxide, or polycrystalline germanium. The coating layer 1 1 is covered by the single grain size semiconductor element i ◦ 〇 front side 丄〇 2, rear side surface 1 0 2 , left side surface: L 0 3 , right side surface 丄〇 4, and bottom surface 丄〇 5, The thickness of the insulating coating layer 110 is between about 1 and 50 (four), which is sufficient to protect the single-grain size semiconductor device 1 2010 201003858. The upper surface 1 〇6 of the single-grain-size semiconductor device 1 〇0 is shielded by the fixture 200, and the upper surface of the single-grain-size semiconductor device 11 defines a metal lead region ( Metai Wire Area) 1 0 6 a, please refer to the fifth figure, the metal lead region 丄〇6 a has a metal pad 1 2 前 before performing the insulation coating process. The two metal pads 1 2 〇 are electrically connected to other substrates, and the method for forming the metal pads 1 20 is a commonly used technique for semiconductor processes such as semiconductor exposure and development (Lithography) and metal etching (Metal Etching). It is not the focus of the present invention and therefore will not be described in detail herein. The process step S 1 〇8 then picks up the fixture 2 and the single-grain size semiconductor component from the insulating coating device, and then separates the fixture 200 from the single-grain size semiconductor component. Hey. The process step S 1 1 0 = wheat, the sixth figure, and then the two ends of the single grain size semiconductor device 1 〇〇 0 are adhered to the silver paste and then dried or cured (curmg) or burned (Firing) The process is used to form a conductive layer. In this embodiment, the conductive layer terminal electrode 1 30, the terminal electrode 1 30 covers the insulating cover layer 1 1 ◦ and the metal pads 1 220. The process step S 1 1 2 is known as the seventh figure, and finally one end of the single-grain size semiconductor device 10 is electrically recorded to form a plating layer 1 4 Q, and the electric boat layer 1 40 includes tin 'the plating layer' Covering the terminal electrode 130, the completed-early BS grain size semiconductor device insulating covering structure 1 〇〇a. 10 201003858 Please refer to the drawings, the present invention provides a single grain size semiconductor device packaging process S100, comprising the following steps: process step 5 1 0 2. process step s 1 〇4, process step s丄〇6, process step S1 〇8, process step s work 〇, and process step work 2. Process step S 1 〇 2 , refer to the second figure 'first provides a single-grain size semiconductor element) 0 0, the early grain size semiconductor element 丄〇〇 is a cube, the cube has a hexahedron from the front side 1 ◦丄, rear side 丄◦ 2, left 2 3, right side 1 0 4, bottom surface 1 0 5, and upper surface 1 0 6 ^, and the cube has a length, width and height of about 0.6 mm x O · 3 m ^ ' 5mm' 1-〇mmx〇.5mmx〇.5min'^l 6mmx〇.8mmx〇5mm. . rv towards the third picture 'then The fixture has 2 QQ, and the fixture 2 is designed by the user. The process step S 1 〇4 η η places the single-grain size semiconductor component 1 0 Q on the fixture 2. The upper surface of the single-grain size semiconductor device 10 is attached to the upper surface of the jig 2 GO. Flow step S 1 〇 6 Second, an insulating coating process is performed, and the jig is clamped together 2 And the semiconductor component 10 ◦ is placed in a coating device (not crystallized, only four drawings, forming - insulating coating layer 1 10 in the single -: organic high 4: two pieces 30, the insulating coating layer 11 〇 can 1 〇 covering the second::: 夕: or 姆, the insulating coating layer 1 early grain size semiconductor component 1 〇〇 front side work 11 201003858 0 1, rear side 1 〇 2, left side 1 ο 3, right side 1 〇 4, and a bottom surface 1 0 5 , the insulating coating layer 1 1 〇 has a thickness of about 1 to 50 / zm, which is sufficient to protect the single grain size semiconductor device 1 ◦ 〇. 0 masking the upper surface 1 〇6 of the single-grain size semiconductor device 100, the single-grain size semiconductor device 100 Surface 1 〇6 defines a metal wire area (Metal Wire Area) 1 〇6 a 'Please refer to the fifth figure, the metal lead area 1 0 6 a before the insulation coating process, the metal lead area 1 〇 6 a Γ There is a metal pad (2), which is used to electrically connect with other substrates. The method for forming the metal pads 1 2 is a commonly used technique in semiconductor manufacturing, such as semiconductor exposure and development. (Lithography), and Metal Etching, which is not the focus of the present invention, is not described in detail herein. The process step S 1 〇8 then removes the fixture 2 and the single-grain-size semiconductor component 100 from the insulating coating device, and then separates the fixture 2 〇 (, f 0 and the single crystal The grain size semiconductor element 1 〇◦. The flow step s 1 1 〇β芩, 、, 、, 6th, and then the two ends of the single grain size semiconductor element 1 ρ 0 are adhered to the silver paste and then dried. Or a curing or Fmng process for forming a conductive layer. In this embodiment, the one end electrode 1 3 〇, the end electrode 13 3 ◦ covers the insulating break layer 1 1 〇 and the Metal pad 1 2 0. Flow step s 1 1 2 ^ seventh figure, finally, the single-grain size semiconductor element 1 12 201003858 〇〇 one end of the electric ore to form a plating 屛 1 4 π containing nickel, and tin, the The plating layer 14 is coated on the layer 140-single-single-grain size semiconductor element insulating coating:: '13 〇, the present invention can achieve the following effects in comparison with the conventional ones. (1) Since it is not used Semiconductor components. Solder "post-package", while using passive elements = to utilize the same reliability of adhesion' However, the smaller size of the semi-conducting 'can get the size of the piece can be easily made to i · 〇. For example - passive element mm ^ ^. 5mmxQ25mm $ mmx 〇. 5 conventional semiconductor package pin can not easily υ · 5 One is a layer 1 1 ◦, the terminal electrode i 3 ◦ and the electroplated wide-area insulated single-grain size semiconductor device package to protect the environmental influence, such as moisture or gray (10), and other (2) utilization The fixture 2 Q 〇 and its design ^ package protection process, and at the same time in the 2 semiconductor components into a passive component when the g # # + size semiconductor component is formed on the terminal electrode 2 3 仟 upper layer “Ο, used to electrically connect to other substrates. Preparation 2:: The lead frame package of the electric ore industry in the face (Lear = use semiconductor to electrically connect with other substrates. It is difficult to reduce the process by 7). Although the invention has been - </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A die-size semiconductor component is formed on the semiconductor device, and at the same time, a common terminal electrode i 3 〇 33 201003858 of the passive component is formed on the single component, and a plating layer 1400 having a solder interface is used for electrically connecting the other substrate. It is not necessary to use the lead frame package (using die bonding, bonding wire, and then packaging) in the semiconductor industry to achieve electrical connection with other substrates. This saves the cost of precision packaging equipment and reduces the difficulty of the process. The above has been disclosed in a preferred embodiment, but it is not intended to limit the invention, and it is obvious to those skilled in the art without departing from the spirit and scope of the invention. And the variations or modifications, can be encompassed by the following case the patent application range.
【圖式簡單說明】 第一圖 為本發明實施例之方法流程圖。 第二圖 為本發明實施例之單一晶粒尺寸半導體元件 之立體示意圖。 第三圖 為本發明實施例之單一晶粒尺寸半導體元件 放置治具之立體示意圖。 第四圖 為本發明實施例之製程剖面示意圖（一）。 第五圖 為本發明實施例之製程剖面示意圖（二）。 第六圖 為本發明實施例之製程剖面示意圖（三）。 第七圖 為本發明實施例之製程剖面示意圖（四）。 【主要元件符號說明】 流程步驟 S100 — S112 單一晶粒尺寸半導體元件 100 早'一晶粒尺寸半導體元件絕緣被覆結構1 0 0 a 前侧面 101 後侧面 102 左侧面 103 14 201003858 右侧面 1 0 4 底面 1 0 5 上表面 1 0 6 金屬引線區域 絕緣被覆 層 1 金屬墊 1 2 0 端電極 1 3 0 電鍍層 1 4 0 治具 2 00BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a flow chart of a method according to an embodiment of the present invention. The second figure is a perspective view of a single grain size semiconductor device in accordance with an embodiment of the present invention. The third figure is a perspective view of a single die-size semiconductor component placement jig according to an embodiment of the present invention. The fourth figure is a schematic cross-sectional view of a process according to an embodiment of the present invention (1). Figure 5 is a schematic cross-sectional view of a process according to an embodiment of the present invention (2). Figure 6 is a schematic cross-sectional view of a process according to an embodiment of the present invention (3). Figure 7 is a schematic cross-sectional view of a process according to an embodiment of the present invention (4). [Main component symbol description] Flow step S100 - S112 Single grain size semiconductor device 100 Early 'one grain size semiconductor element insulating covering structure 1 0 0 a Front side 101 Rear side 102 Left side 103 14 201003858 Right side 1 0 4 Bottom 1 0 5 Upper surface 1 0 6 Metal lead area Insulation coating 1 Metal pad 1 2 0 Terminal electrode 1 3 0 Plating layer 1 4 0 Fixture 2 00