TWI455253B - Semiconductor Package with Adhesive Material Pre-Printed On The Lead Frame And Chip, And Its Manufacturing Method - Google Patents

Semiconductor Package with Adhesive Material Pre-Printed On The Lead Frame And Chip, And Its Manufacturing Method Download PDF

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TWI455253B
TWI455253B TW099121472A TW99121472A TWI455253B TW I455253 B TWI455253 B TW I455253B TW 099121472 A TW099121472 A TW 099121472A TW 99121472 A TW99121472 A TW 99121472A TW I455253 B TWI455253 B TW I455253B
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stage
printing
wafer
bonding material
printed
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TW099121472A
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TW201201326A (en
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Xiaotian Zhang
Jun Lu
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Alpha & Omega Semiconductor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

一種通過印刷粘接材料封裝的半導體裝置及其製造方法 Semiconductor device packaged by printing adhesive material and manufacturing method thereof

本發明涉及一種半導體裝置及其製造方法，特別涉及一種通過印刷粘接材料封裝的半導體裝置及其製造方法。 The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device packaged by a printed adhesive material and a method of fabricating the same.

在積體電路的封裝中，目前普遍使用引線框架來承載晶片和連接外部裝置。引線框架通常是由銅或者合金的平面板材經過衝壓或蝕刻的方法製成，具有高強度、抗腐蝕、抗氧化、高導電率、高導熱性、延展性好、容易成形的特點，還有極好的鍍層性能，能良好的粘接塑封體，並且具有與所述晶片和塑封體的熱膨脹係數極接近的熱膨脹係數。 In the package of integrated circuits, lead frames are currently commonly used to carry wafers and connect external devices. The lead frame is usually made of a flat plate of copper or alloy by stamping or etching. It has high strength, corrosion resistance, oxidation resistance, high electrical conductivity, high thermal conductivity, good ductility and easy forming. Good coating properties, good adhesion of the molded body, and thermal expansion coefficient close to the thermal expansion coefficient of the wafer and the molded body.

以下結合附第1圖至第5圖詳細說明現有的半導體封裝技術中，粘接晶片和引線框架的具體製造過程。 The specific manufacturing process of bonding a wafer and a lead frame in the conventional semiconductor packaging technology will be described in detail below with reference to FIGS. 1 to 5.

如第1圖所示，引線框架100通過設有的載片台110來承載晶片150，並設有2個引腳120、130將晶片150連接到外部元裝置。如第2圖所示，目前常用的粘接晶片的方法是在載片台110的表面利用點膠方式鋪設形成粘接材料140；其中，所述的粘接材料140可以是膠黏劑環氧樹脂，包含利用點膠形成的導電或非導電的環氧樹脂；該粘接材料140也可以是利用點膠形成的焊膏或者共晶材料。如第3圖所示，再將晶片150(例如積體電路IC)放置到粘接材料140上，與載片台110固定粘接。如第4圖所示，利用引線結合技術(Wire Bonding，俗稱打線)將晶片150分別與引腳120和引腳130通過若干金屬引線160連接。 如第5圖所示，對引線框架100進行塑封成型，將其封裝在塑封體170內，以完成封裝程式，使該半導體封裝內的晶片150通過所述引腳120和130實現與外部其他裝置的連接。 As shown in FIG. 1, the lead frame 100 carries the wafer 150 through the stage 110 provided, and is provided with two pins 120, 130 to connect the wafer 150 to the external component. As shown in FIG. 2, a conventional method for bonding wafers is to form a bonding material 140 by dispensing on the surface of the stage 110; wherein the bonding material 140 may be an adhesive epoxy. The resin comprises an electrically conductive or non-conductive epoxy resin formed by dispensing; the bonding material 140 may also be a solder paste or a eutectic material formed by dispensing. As shown in FIG. 3, the wafer 150 (for example, the integrated circuit IC) is placed on the bonding material 140 and fixedly bonded to the stage 110. As shown in FIG. 4, the wafer 150 is connected to the leads 120 and 130 by a plurality of metal leads 160 by wire bonding (Wire Bonding, commonly known as wire bonding). As shown in FIG. 5, the lead frame 100 is molded by molding, and is packaged in the molding body 170 to complete the packaging process, so that the wafer 150 in the semiconductor package is realized by the pins 120 and 130 and other external devices. Connection.

上述晶片與引腳的連接，也可如第6圖所示，使用若干金屬連接平板180將晶片150分別與引腳120和引腳130連接來實現。其中，所述的金屬連接平板180是利用點膠形成的粘接材料(例如焊膏或環氧樹脂)分別與晶片150以及引腳120、引腳130結合連接。隨後，如第7圖所示，對引線框架100進行塑封成型，將其封裝在塑封體170內，以完成封裝程式。 The connection of the above wafers to the leads can also be realized by connecting the wafers 150 to the pins 120 and 130, respectively, using a plurality of metal connection plates 180 as shown in FIG. The metal connection plate 180 is connected to the wafer 150 and the pins 120 and 130 by an adhesive material (for example, solder paste or epoxy resin) formed by dispensing. Subsequently, as shown in Fig. 7, the lead frame 100 is molded by molding, and is packaged in the molded body 170 to complete the packaging process.

上述晶片與引腳的連接，還可以如第8圖所示，使用金屬引線160將晶片150與引腳120連接，並同時使用金屬連接平板180將晶片150與引腳130連接。其中，所述的金屬引線160利用引線結合技術分別與晶片150以及引腳120結合連接；而所述的金屬連接平板180則利用點膠形成的粘接材料(例如焊膏或環氧樹脂)分別與晶片150以及引腳130結合連接。隨後，如第9圖所示，對引線框架100進行塑封成型，將其封裝在塑封體170內，以完成封裝程式。 The wafer and the lead are connected. As shown in FIG. 8, the wafer 150 can be connected to the lead 120 using the metal lead 160, and the wafer 150 can be connected to the lead 130 using the metal connection plate 180 at the same time. Wherein, the metal lead 160 is respectively connected to the wafer 150 and the lead 120 by wire bonding technology; and the metal connecting plate 180 is respectively formed by using a bonding material (such as solder paste or epoxy resin) formed by dispensing. It is coupled to the wafer 150 and the leads 130. Subsequently, as shown in Fig. 9, the lead frame 100 is molded by molding, and is packaged in the molded body 170 to complete the packaging process.

但是，上述所描述的利用點膠方式形成的粘接材料粘接晶片和引線框架，存在以下缺點： However, the bonding material formed by the dispensing method described above bonds the wafer and the lead frame, and has the following disadvantages:

1、在相同的封裝尺寸中，由於採用點膠方式在載片臺上先鋪設形成粘接材料(焊膏或環氧樹脂)，當其上貼附並粘接晶片後，該粘接材料會從晶片周圍溢出，基於該無法避免的溢出效應，將會限制被封裝的晶片尺寸大小。 1. In the same package size, because the adhesive material (solder paste or epoxy resin) is firstly laid on the stage by dispensing, the bonding material will be attached after bonding and bonding the wafer thereon. Overflow from the periphery of the wafer, based on this unavoidable spillover effect, will limit the size of the packaged wafer.

2、在載片臺上通過點膠鋪設來形成用於粘接晶片的粘接材料(焊膏或環氧樹脂)，這種方式會導致所形成的粘接材料的厚度並不均勻一致，由此會使得貼附粘接在其上的晶片產生傾斜的情況。 2. Adhesive material (solder paste or epoxy resin) for bonding the wafer is formed by dispensing on the stage, which results in uneven thickness of the formed bonding material. This causes the wafer attached to the wafer to be tilted.

3、採用焊膏或環氧樹脂作為粘接材料將晶片粘接到載片臺上後， 會產生很高的應力，極容易導致晶片產生裂紋，影響晶片的可靠性。 3. After bonding the wafer to the carrier using solder paste or epoxy resin as bonding material, It will generate high stress, which will easily lead to cracks in the wafer and affect the reliability of the wafer.

4、採用焊膏作為粘接材料將晶片粘接到載片臺上後，還需要在氮氣或者在氮氣及氫氣的混合氣體的環境下進行回流焊。 4. After bonding the wafer to the stage using solder paste as a bonding material, it is also necessary to perform reflow under nitrogen or a mixed gas of nitrogen and hydrogen.

5、在粘接晶片的過程中，若採用焊膏或者共晶材料作為粘接材料，需要較高的工藝操作溫度，這會導致引線框架快速氧化。 5. In the process of bonding wafers, if solder paste or eutectic material is used as the bonding material, a higher process operating temperature is required, which causes rapid oxidation of the lead frame.

鑒於上述，非常有必要提出一種新的半導體封裝及方法，通過改善現有的晶片粘接技術，以克服所述的缺點，從而提高產品的品質和生產效率。 In view of the above, it is highly desirable to propose a new semiconductor package and method that overcomes the shortcomings by improving existing wafer bonding techniques, thereby improving product quality and production efficiency.

本發明的目的是提供一種通過印刷粘接材料封裝的半導體裝置及其製造方法，其通過改善現有的晶片粘接技術，克服現有技術所存在的缺陷，使得產品的品質和生產效率得以提高。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device packaged by a printing adhesive material and a method of manufacturing the same that overcomes the deficiencies of the prior art by improving the existing wafer bonding technology, thereby improving the quality and production efficiency of the product.

為了達到上述目的，本發明的技術方案是提供一種通過印刷粘接材料封裝的半導體裝置，其特徵在於，包含：第一引線框架，其設有電性隔離的第一載片台、第二載片台；半導體晶片，通過在其頂面的若干頂部電極上印刷形成的、導電的第一印刷粘接材料固定貼附於第一載片台和第二載片臺上；設置在第二引線框架上的第三載片台，通過在其頂面印刷形成的、導電的第二印刷粘接材料固定貼附於上述半導體晶片底面的若干底部電極上。 In order to achieve the above object, the technical solution of the present invention provides a semiconductor device packaged by a printed adhesive material, comprising: a first lead frame provided with an electrically isolated first stage, and a second load a semiconductor wafer fixedly attached to the first stage and the second stage by a conductive first printing adhesive formed by printing on a plurality of top electrodes of the top surface thereof; The third stage on the frame is fixedly attached to a plurality of bottom electrodes of the bottom surface of the semiconductor wafer by a second conductive bonding material formed by printing on the top surface thereof.

上述第一載片台、第二載片臺上分別設有若干引腳，將粘接固定在上述第一載片台、第二載片臺上的上述半導體晶片的若干頂部電極與外部元裝置連通。 The first stage and the second stage are respectively provided with a plurality of pins, and a plurality of top electrodes and external element devices of the semiconductor wafer bonded and fixed on the first stage and the second stage Connected.

上述粘接固定在上述半導體晶片底面的第三載片臺上設有若干引腳，將上述半導體晶片的若干底部電極與外部元裝置連通。 The third stage mounted on the bottom surface of the semiconductor wafer is provided with a plurality of pins, and a plurality of bottom electrodes of the semiconductor wafer are connected to an external element device.

上述半導體晶片的若干頂部電極上分別包含若干區域的、通過印刷形成的上述第一印刷粘接材料。 The plurality of top electrodes of the semiconductor wafer respectively comprise a plurality of regions of the first printed bonding material formed by printing.

上述在半導體晶片頂面印刷形成的上述第一印刷粘接材料具有與上述頂部電極相同或不同的形狀。 The first printing adhesive material formed by printing on the top surface of the semiconductor wafer has the same or different shape as the top electrode.

上述在半導體晶片頂面印刷形成的上述第一印刷粘接材料的尺寸等於或小於上述頂部電極的面積。 The size of the first printing adhesive material formed on the top surface of the semiconductor wafer is equal to or smaller than the area of the top electrode.

上述第三載片台頂面印刷形成的上述第二印刷粘接材料尺寸與上述半導體晶片面積相等。 The size of the second printing adhesive formed by printing on the top surface of the third stage is equal to the area of the semiconductor wafer.

上述第三載片台頂面印刷形成的上述第二印刷粘接材料尺寸與上述半導體晶片面積不相等。 The size of the second printing adhesive formed by printing on the top surface of the third stage is not equal to the area of the semiconductor wafer.

上述通過印刷粘接材料封裝的半導體裝置，還包含塑封體，其將上述第一載片台、第二載片台、半導體晶片、第三載片台封裝在其內部，使上述第一載片台、第二載片台、第三載片臺上分別設有的若干引腳暴露在上述塑封體外。 The semiconductor device packaged by the printing adhesive material further includes a molding body that encapsulates the first carrier stage, the second stage stage, the semiconductor wafer, and the third stage in the first stage. A plurality of pins respectively disposed on the table, the second stage and the third stage are exposed to the outside of the plastic package.

上述第三載片台的底面還設有散熱焊盤，上述散熱焊盤暴露在上述塑封體外。 The bottom surface of the third stage is further provided with a heat dissipation pad, and the heat dissipation pad is exposed to the outside of the plastic package.

一種通過印刷粘接材料封裝的半導體裝置的製造方法，其特徵在於，包含以下步驟：步驟1.1在晶圓頂面上印刷導電的第一印刷粘接材料；步驟1.2高溫固化第一印刷粘接材料；步驟2.1在第三載片台頂面上印刷導電的第二印刷粘接材料；步驟2.2高溫固化第二印刷粘接材料步驟3. 高溫下將半導體晶片頂面通過第一印刷粘接材料，同時粘接到第一載片台和第二載片臺上；步驟4. 高溫下將第三載片台通過第二印刷粘接材料粘接至半導體晶片底面； 步驟5. 高溫下對第一印刷粘接材料、第二印刷粘接材料進行高溫固化；步驟6. 將第一載片台、第二載片台、半導體晶片、第三載片台封裝在塑封體內。 A method of manufacturing a semiconductor device packaged by a printing adhesive material, comprising the steps of: printing a conductive first printing bonding material on a top surface of the wafer in step 1.1; and curing the first printing bonding material in a high temperature step in step 1.2; Step 2.1 printing a conductive second printing bonding material on the top surface of the third stage; step 2.2 high temperature curing the second printing bonding material step 3. Passing the top surface of the semiconductor wafer through the first printing bonding material at a high temperature Simultaneously bonding to the first stage and the second stage; step 4. bonding the third stage to the bottom surface of the semiconductor wafer through the second printing bonding material at a high temperature; Step 5. High temperature curing of the first printing bonding material and the second printing bonding material at a high temperature; Step 6. Packaging the first carrier stage, the second stage, the semiconductor wafer, and the third stage in a plastic package in vivo.

上述步驟1是利用絲網或網板印刷技術對晶圓進行印刷，一次完成一片晶圓的印刷，具體包含以下步驟：步驟1.1.1在絲網或網板上開設若干開口；其中，上述若干開口的數量和位置，分別對應該片晶圓頂面需要設置第一印刷粘接材料的頂部電極的數量和位置；步驟1.1.2在上述各個開口中印刷形成第一粘接材料；其中，上述第一粘接材料的厚度是由上述絲網或網板上開口的厚度決定。 The above step 1 is to print the wafer by using the screen or screen printing technology, and complete the printing of one wafer at a time, and specifically includes the following steps: Step 1.1.1 opening a plurality of openings on the screen or the mesh board; The number and position of the openings respectively correspond to the number and position of the top electrodes of the first printing adhesive material required to be disposed on the top surface of the wafer; and the step 1.1.2 is printed in each of the openings to form a first bonding material; The thickness of the first bonding material is determined by the thickness of the opening on the screen or the screen.

上述步驟1.1.1中若干開口具有與上述頂部電極相同或不同的形狀。 Some of the openings in step 1.1.1 above have the same or different shape as the top electrode described above.

上述步驟1.1.1中若干開口的尺寸等於或小於上述頂部電極的面積。 The size of several openings in the above step 1.1.1 is equal to or smaller than the area of the above top electrode.

上述步驟1還包含對晶圓進行劃分以及切割操作，形成若干獨立的半導體晶片的步驟1.3。 Step 1 above also includes the step of dividing the wafer and cutting operations to form a plurality of individual semiconductor wafers.

上述步驟2.1是利用絲網或網板印刷技術對第二引線框架上的第三載片台頂面進行印刷，一次完成一條第二引線框架的印刷，具體包含以下步驟：步驟2.1.1在絲網或網板上開設若干開口；其中，上述若干開口的數量和位置，分別對應該條第二引線框架上需要設置第二印刷粘接材料的第三載片台的數量和位置；步驟2.1.2在上述各個開口中印刷形成第二粘接材料；其中，上述第二粘接材料的厚度是由上述絲網或網板上開口的 厚度決定。 The above step 2.1 is to use the screen or screen printing technology to print the top surface of the third stage on the second lead frame, and complete the printing of one second lead frame at a time, specifically comprising the following steps: Step 2.1.1 in the wire Opening a plurality of openings on the net or the stencil; wherein the number and position of the plurality of openings respectively correspond to the number and position of the third stage on which the second printed bonding material needs to be disposed on the second lead frame; step 2.1. 2 printing a second bonding material in each of the openings; wherein the thickness of the second bonding material is opened by the wire mesh or the mesh plate The thickness is determined.

上述步驟2.1.1中若干開口的尺寸等於或小於在上述步驟4中第三載片台貼附的上述半導體晶片的面積。 The size of the plurality of openings in the above step 2.1.1 is equal to or smaller than the area of the semiconductor wafer attached to the third stage in the above step 4.

上述步驟1.2及步驟2.2中上述固化溫度為110℃~130℃；上述步驟3中將上述半導體晶片粘接到上述第一載片台和第二載片台、上述步驟4中將上述第三載片台粘接到上述半導體晶片時的溫度在95℃~130℃；上述步驟5中對第一印刷粘接材料和第二印刷粘接材料的固化溫度是175℃。 In the above steps 1.2 and 2.2, the curing temperature is 110 ° C to 130 ° C; in the above step 3, the semiconductor wafer is bonded to the first stage and the second stage, and in the step 4, the third load is performed. The temperature at which the wafer is bonded to the semiconductor wafer is 95 ° C to 130 ° C; and the curing temperature of the first printing adhesive material and the second printing adhesive material in the above step 5 is 175 ° C.

在上述步驟6中封裝前，還包含在整條第二引線框架的第三載片台底面黏貼薄膜的步驟；上述薄膜黏貼在上述散熱焊盤上及上述第一載片台、第二載片台、第三載片台分別設有的若干引腳上。 Before the packaging in the above step 6, the method further includes the step of adhering the film to the bottom surface of the third stage of the entire second lead frame; the film is adhered to the heat dissipation pad and the first stage and the second piece The stage and the third stage are respectively provided with a plurality of pins.

本發明所提供的通過印刷粘接材料封裝的半導體裝置及其製造方法，通過分別在半導體晶片和第三載片臺上印刷粘接材料來連接，該粘接材料的大小、形狀、厚度根據所需晶片表面的電性能和粘接區域來決定；而不需要利用傳統點膠或點焊錫進行連接，故本發明所述的半導體封裝具有以下優點： The semiconductor device packaged by the printing adhesive material and the method of manufacturing the same according to the present invention are connected by printing an adhesive material on the semiconductor wafer and the third stage, respectively, and the size, shape and thickness of the bonding material are The electrical properties of the surface of the wafer and the bonding area are determined; without the need to connect by conventional dispensing or spot soldering, the semiconductor package of the present invention has the following advantages:

1、在相同的封裝尺寸中，由於採用了在載片臺上印刷粘接材料的方法，當晶片貼附並粘接後，不會發生粘接材料在晶片周圍溢出的情況，故可以實現最大面積的晶片(即該晶片的尺寸和載片台相同)的封裝。 1. In the same package size, since the method of printing the bonding material on the stage is adopted, when the wafer is attached and bonded, the bonding material does not overflow around the wafer, so the maximum can be achieved. A package of an area of wafer (ie, the size of the wafer is the same as the stage).

2、通過印刷方式而形成的粘接材料，厚度均勻一致，有效減少晶片貼附後的傾斜，成品率較高。 2. The bonding material formed by the printing method has uniform thickness, which effectively reduces the inclination after the wafer is attached, and the yield is high.

3、採用具有印刷特性的粘接材料，相比于現有技術中採用的焊膏或普通環氧樹脂等粘接材料，在晶片粘接至載片臺上後，所產生的應力也相對較低，減少晶片的裂紋；並且該具有印刷特 性的粘接材料具有良好的導電率和導熱性。 3. Using a bonding material with printing characteristics, compared with the bonding materials such as solder paste or ordinary epoxy resin used in the prior art, the stress generated after the wafer is bonded to the stage is relatively low. , reducing the crack of the wafer; and the printing The adhesive material has good electrical conductivity and thermal conductivity.

4、採用具有印刷特性的粘接材料，在粘接晶片的過程中，相比于現有技術，所需的工藝操作溫度相對低，因此引線框架的氧化過程緩慢。 4. The bonding material having printing characteristics is used. In the process of bonding the wafer, the required processing temperature is relatively low compared to the prior art, and thus the oxidation process of the lead frame is slow.

5、在印刷粘接材料後，可直接線上固化粘接材料，生產連續且快速，有效提高生產效率。 5. After printing the bonding material, the bonding material can be directly cured on the line, and the production is continuous and rapid, and the production efficiency is effectively improved.

綜上，本發明提供的半導體封裝及其製造方法，能有效改善半導體產品的品質和性能，提高生產效率。 In summary, the semiconductor package and the method of manufacturing the same provided by the present invention can effectively improve the quality and performance of a semiconductor product and improve production efficiency.

32‧‧‧第二印刷粘接材料 32‧‧‧Second printing bonding material

13‧‧‧第三載片台 13‧‧‧ Third stage

100‧‧‧引線框架 100‧‧‧ lead frame

110‧‧‧載片台 110‧‧‧Slide

120、130‧‧‧引腳 120, 130‧‧‧ pin

140‧‧‧粘接材料 140‧‧‧ Bonding materials

150‧‧‧晶片 150‧‧‧ wafer

160‧‧‧金屬引線 160‧‧‧Metal lead

40、170‧‧‧塑封體 40, 170‧‧ ‧ plastic body

180‧‧‧金屬連接平板 180‧‧‧Metal connection plate

10‧‧‧第一引線框架 10‧‧‧First lead frame

11‧‧‧第一載片台 11‧‧‧First stage

12‧‧‧第二載片台 12‧‧‧Second stage

20‧‧‧半導體晶片 20‧‧‧Semiconductor wafer

31、311、322、312‧‧‧第一印刷粘接材料 31, 311, 322, 312‧‧‧ first printing bonding materials

22‧‧‧頂部源極 22‧‧‧Top source

21‧‧‧頂部柵極 21‧‧‧ top grid

131‧‧‧散熱焊盤 131‧‧‧ Thermal pad

第1圖至第9圖是現有技術中利用點膠粘接方式封裝半導體裝置的步驟示意圖；第10a圖至第14a圖是本發明提供的通過印刷粘接材料封裝的半導體裝置的製造方法的步驟示意圖；第10b圖至第14b圖是對應第10a圖至第14a圖本發明提供的通過印刷粘接材料封裝的半導體裝置的製造方法的步驟側視圖；第15圖是本發明提供的通過印刷粘接材料封裝的半導體裝置中MOSFET晶片的示意圖；第16圖至第19圖是本發明提供的通過印刷粘接材料封裝的半導體裝置的製造方法中在MOSFET晶片上塗覆第一印刷粘接材料的若干結構示意圖；第20圖是本發明提供的通過印刷粘接材料封裝的半導體裝置的製造方法中在第三載片臺上塗覆第二印刷粘接材料的結構示意圖；第21圖是本發明提供的通過印刷粘接材料封裝的半導體裝置的製造方法的流程示意圖。 1 to 9 are schematic views showing steps of packaging a semiconductor device by means of dispensing bonding in the prior art; FIGS. 10a to 14a are steps of a method of manufacturing a semiconductor device packaged by a printing adhesive material provided by the present invention; FIG. 10b to FIG. 14b are side views showing steps of a method of manufacturing a semiconductor device packaged by a printed adhesive material according to the 10th to 14thth drawings; FIG. 15 is a print-adhesive provided by the present invention. FIG. 16 to FIG. 19 are diagrams showing a method of fabricating a first printed bonding material on a MOSFET wafer in a method of fabricating a semiconductor device packaged by a printed bonding material provided by the present invention; FIG. FIG. 20 is a schematic structural view showing a second printing adhesive material coated on a third stage in a method of manufacturing a semiconductor device packaged by a printing adhesive material according to the present invention; FIG. 21 is a schematic view of the present invention. A schematic flow diagram of a method of fabricating a semiconductor device packaged by a printed adhesive material.

以下結合附圖，通過優選的具體實施例，詳細說明本發明。 The invention will be described in detail below by way of preferred embodiments with reference to the accompanying drawings.

本發明所提供的半導體封裝及製造方法，可適用於所有的半導體晶片，包括功率MOSFET及IC晶片等等。在以下所提供的各具體實施例的詳細描述中，以功率MOSFET晶片為例來詳細說明本發明對功率MOSFET晶片的封裝方法；另外，在所述的實施例中，以具有印刷特性的粘接材料(為與背景技術中所採用的不具備印刷特性的普通粘接材料顯示區別，避免混淆，以下簡稱“印刷粘接材料”)為例，作為本發明封裝方法中所採用的通過印刷形成的粘接材料，從而更好的理解本發明的各項優點及有益效果。但應當注意的是，這些具體描述及實例並非用來限制本發明的範圍。 The semiconductor package and manufacturing method provided by the present invention can be applied to all semiconductor wafers, including power MOSFETs, IC chips, and the like. In the detailed description of the specific embodiments provided below, the method of packaging the power MOSFET wafer of the present invention will be described in detail by taking a power MOSFET wafer as an example; in addition, in the embodiment described, bonding with printing characteristics is provided. The material (which is distinguished from the ordinary bonding material which does not have printing characteristics used in the background art to avoid confusion, hereinafter referred to as "printing bonding material") is taken as an example, which is formed by printing as used in the packaging method of the present invention. The materials are bonded to better understand the advantages and benefits of the present invention. It should be noted, however, that the specific description and examples are not intended to limit the scope of the invention.

如第13圖所示，是本發明提供的一種通過印刷粘接材料封裝的半導體裝置，其包含設置在第一引線框架10上的第一載片台11和第二載片台12，通過設置第一印刷粘接材料31貼附在第一載片台11和第二載片台12上的半導體晶片20，和通過設置的第二印刷粘接材料32貼附在半導體晶片20上的第三載片台13，該第三載片台13設置在第二引線框架上。 As shown in FIG. 13, the present invention provides a semiconductor device packaged by a printed bonding material, comprising a first stage 11 and a second stage 12 disposed on the first lead frame 10, through setting The first print bonding material 31 is attached to the semiconductor wafer 20 on the first stage 11 and the second stage 12, and the third printed on the semiconductor wafer 20 by the second printing bonding material 32 provided. The stage 13 is disposed on the second lead frame.

其中第一載片台11和第二載片台12相互電性隔離用來承載半導體晶片20，還分別設有若干引腳延伸至第一引線框架10外，作為柵極引腳G或源極引腳S用來與外部元裝置連接。如第10圖所示，在本實施例中，設第一載片台11的引腳為柵極引腳G、第二載片台12的若干引腳為源極引腳S，該柵極引腳G和源極引腳S延伸在第一引線框架10下表面的同一側。 The first stage 11 and the second stage 12 are electrically isolated from each other for carrying the semiconductor wafer 20, and are further provided with a plurality of pins extending outside the first lead frame 10 as gate pins G or sources. Pin S is used to connect to an external meta device. As shown in FIG. 10, in the embodiment, the pins of the first stage 11 are the gate pins G, and the pins of the second stage 12 are the source pins S. The pin G and the source pin S extend on the same side of the lower surface of the first lead frame 10.

請配合參見第15圖到第19圖所示，上述半導體晶片20是MOSFET晶片，其包含設置在頂面的頂部柵極21和頂部源極22(第15圖所示)，以及設置在其底面的底部漏極(圖中未示)。半導體晶片20通過分別在頂部柵極21和頂部源極22上印刷形成導電型的第一印刷粘接材料311、322，固定貼附在第一載片台11和第二載片台12上， 使頂部柵極21和頂部源極22能分別通過第一載片台11的柵極引腳G、第二載片台12的源極引腳S與外部元裝置連接。 Referring to FIGS. 15 to 19, the semiconductor wafer 20 is a MOSFET wafer including a top gate 21 and a top source 22 (shown in FIG. 15) disposed on the top surface, and a bottom surface thereof. The bottom drain (not shown). The semiconductor wafer 20 is fixedly attached to the first stage 11 and the second stage 12 by printing a first conductive bonding material 311, 322 of a conductive type on the top gate 21 and the top source 22, respectively. The top gate 21 and the top source 22 can be connected to the external element device through the gate pin G of the first stage 11 and the source pin S of the second stage 12, respectively.

第一印刷粘接材料31的形狀尺寸和厚度均可根據需要確定。半導體晶片20的頂部柵極21和頂部源極22上分別印刷形成的單個區域的第一印刷粘接材料311、312，可以是具有與頂部柵極21和頂部源極22相同形狀和大小尺寸的(圖中未示)，也可以是印刷尺寸小於頂部柵極21或頂部源極22面積的第一印刷粘接材料311、312(如第16圖所示)。 The shape size and thickness of the first printing adhesive material 31 can be determined as needed. The first printed bonding materials 311, 312 of the single region formed on the top gate 21 and the top source 22 of the semiconductor wafer 20, respectively, may have the same shape and size as the top gate 21 and the top source 22. (not shown), it may be a first printing adhesive material 311, 312 having a printed size smaller than the area of the top gate 21 or the top source 22 (as shown in Fig. 16).

在本發明的又一實施例中，在半導體晶片20的頂部柵極21上包含印刷形成的單個區域、相同形狀的，尺寸相同或小於頂部柵極21的第一印刷粘接材料311，而在頂部源極22上印刷形成2個或更多個橫向區域的第一印刷粘接材料312(如第17圖所示)；也可以是在頂部源極22上印刷形成2個或更多個縱向區域的第一印刷粘接材料312(如第18圖所示)。 In still another embodiment of the present invention, a single printed region, a same shape of the first printed bonding material 311 having the same size or smaller than the top gate 21 is formed on the top gate 21 of the semiconductor wafer 20, and A first printed bonding material 312 (shown in FIG. 17) is formed on the top source 22 to form two or more lateral regions; or two or more vertical patterns may be printed on the top source 22 The first printed bond material 312 of the region (as shown in Figure 18).

又或者，在本發明的另一實施例中，如第19圖所示，在半導體晶片20的頂部柵極21上通過印刷形成了單個區域的圓形且尺寸小於頂部柵極21的第一印刷粘接材料311，而在頂部源極22上設有單個區域的圓形或橢圓形、尺寸小於頂部源極22的第一印刷粘接材料312。 Still alternatively, in another embodiment of the present invention, as shown in FIG. 19, a first circle having a circular shape and a size smaller than the top gate 21 is formed by printing on the top gate 21 of the semiconductor wafer 20. The bonding material 311 is bonded to the top source 22 with a single area of circular or elliptical shape and a first printed bonding material 312 that is smaller in size than the top source 22.

如第12圖或第20圖所示，上述第三載片台13的頂面設有導電型的第二印刷粘接材料32，並通過該第二印刷粘接材料32固定貼附在半導體晶片20的底部漏極上。該第二印刷粘接材料32的印刷面積和厚度根據需要確定，具有與半導體晶片20相同或不同的形狀，以及相同、稍小或稍大一點的尺寸，只要該第二印刷粘接材料32的尺寸大小和厚度能保證具有足夠的粘接區域，以將第三載片台13牢固粘接至半導體晶片20上而不發生脫落即可。 As shown in FIG. 12 or FIG. 20, the top surface of the third stage 13 is provided with a second printing bonding material 32 of a conductive type, and is fixedly attached to the semiconductor wafer by the second printing bonding material 32. The bottom of the 20 is on the drain. The printing area and thickness of the second printing adhesive material 32 are determined as needed, having the same or different shape as the semiconductor wafer 20, and the same, slightly smaller or slightly larger size as long as the second printing bonding material 32 is The size and thickness can be ensured to have sufficient bonding areas to firmly bond the third stage 13 to the semiconductor wafer 20 without falling off.

第三載片台13上還設置有若干引腳延伸至第二引線框架外，在 本實施例中，設該若干引腳為漏極引腳D，如第12圖和第13圖所示，上述若干漏極引腳D延伸在第二引線框架下表面、與上述柵極引腳G、源極引腳S相對的一側。半導體晶片20的底部漏極通過第三載片台13的漏極引腳D與外部元裝置連接。 The third stage 13 is further provided with a plurality of pins extending outside the second lead frame, In this embodiment, the plurality of pins are the drain pins D. As shown in FIG. 12 and FIG. 13 , the plurality of drain pins D extend on the lower surface of the second lead frame and the gate pins. G, the opposite side of the source pin S. The bottom drain of the semiconductor wafer 20 is connected to the external element device through the drain pin D of the third stage 13.

上述半導體裝置還包含塑封體40，用於將第一載片台11、第二載片台12、半導體晶片20、第三載片台13封裝在其內部。封裝時使柵極引腳G、源極引腳S暴露在該塑封體40的底面同一側，而漏極引腳D暴露在底面的相對一側；同時還使第三載片台13設有的散熱焊盤131暴露在塑封體40的底部，用於對半導體晶片20進行散熱。 The semiconductor device further includes a molding body 40 for encapsulating the first stage 11, the second stage 12, the semiconductor wafer 20, and the third stage 13 therein. When the package is packaged, the gate pin G and the source pin S are exposed on the same side of the bottom surface of the molding body 40, and the drain pin D is exposed on the opposite side of the bottom surface; and the third stage 13 is also provided. The heat dissipation pad 131 is exposed at the bottom of the molding body 40 for dissipating heat from the semiconductor wafer 20.

如第21圖所示，詳細介紹了上述通過印刷粘接材料封裝的半導體裝置的製造方法，第10a圖到第14a圖是對應上述封裝步驟的半導體裝置的正視圖，第10b圖到第14b圖是對應上述各步驟的半導體裝置的側視圖。 As shown in FIG. 21, the above-described manufacturing method of the semiconductor device packaged by the printing adhesive material is described in detail, and FIGS. 10a to 14a are front views of the semiconductor device corresponding to the above-described packaging step, and FIGS. 10b to 14b. It is a side view of the semiconductor device corresponding to each of the above steps.

如第10圖所示，在第一引線框架10上設置相互電絕緣的第一載片台11和第二載片台12，使第一載片台11的柵極引腳G、第二載片台12的若干源極引腳S分別延伸至第一引線框架10外同一側與外部裝置連接。 As shown in FIG. 10, the first stage 11 and the second stage 12 electrically insulated from each other are disposed on the first lead frame 10 such that the gate pins G and the second stage of the first stage 11 are provided. The plurality of source pins S of the stage 12 extend to the same side of the first lead frame 10 to be connected to an external device.

之後，在半導體晶片20上印刷形成第一印刷粘接材料31，具體通過以下步驟實現：首先在絲網或網板上開設若干對開口，其對應整個晶圓表面上的若干個半導體晶片20。若干對開口的位置與MOSFET頂面需要第一印刷粘接材料31的頂部柵極21和頂部源極22的位置相同，開口可以分別是與頂部柵極21或頂部源極22有相同或不同的形狀，有相同或稍小一些的尺寸。 Thereafter, the first printed bonding material 31 is printed on the semiconductor wafer 20, specifically by the following steps: First, a plurality of pairs of openings are formed on the screen or the mesh, corresponding to a plurality of semiconductor wafers 20 on the entire wafer surface. The positions of the plurality of pairs of openings are the same as the positions of the top gate 21 and the top source 22 of the first printed bonding material 31 on the top surface of the MOSFET, and the openings may be the same or different from the top gate 21 or the top source 22, respectively. Shape, with the same or slightly smaller size.

隨後，印刷整個晶圓的一面，在上述若干對開口中形成第一印刷粘接材料31。所述的第一印刷粘接材料31的厚度是由開口的 厚度決定，也就是由絲網或者網板的厚度決定，其決定了最終製造完成的半導體裝置的電性能和結合強度；當該第一印刷粘接材料31的厚度越薄時，半導體裝置的電阻越小，具有越好的電性能，但當該第一印刷粘接材料31的厚度過於薄時，其也將因結合強度不夠而容易發生碎裂的情況，所以一般情況下，該第一印刷粘接材料31的厚度在25μm左右或略小於25μm，在保證半導體裝置具有相對較好電性能的同時，也保證其具有一定的結合強度(約為2~3kg)。 Subsequently, one side of the entire wafer is printed, and a first printed bonding material 31 is formed in the plurality of pairs of openings. The thickness of the first printing adhesive material 31 is open The thickness is determined, that is, determined by the thickness of the screen or the screen, which determines the electrical properties and bonding strength of the finally fabricated semiconductor device; when the thickness of the first printed bonding material 31 is thinner, the resistance of the semiconductor device The smaller the smaller, the better the electrical properties, but when the thickness of the first printing adhesive material 31 is too thin, it will also be easily broken due to insufficient bonding strength, so in general, the first printing The thickness of the bonding material 31 is about 25 μm or slightly less than 25 μm, and it is ensured that the semiconductor device has a relatively good electrical property while ensuring a certain bonding strength (about 2 to 3 kg).

再對所形成的第一印刷粘接材料31進行1小時左右的高溫固化，固化溫度為110℃~130℃。最後切割整個晶圓以形成若干個獨立的、在其頂部柵極21和頂部源極22上分別設有第一印刷粘接材料31的半導體晶片20。 Further, the formed first printing adhesive material 31 is cured at a high temperature for about 1 hour, and the curing temperature is 110 ° C to 130 ° C. Finally, the entire wafer is diced to form a plurality of individual semiconductor wafers 20 having first printed bonding materials 31 disposed on their top gate 21 and top source 22, respectively.

如第11圖所示，將半導體晶片20的頂部柵極21和頂部源極22向下，同時倒裝到第一載片台11和第二載片台12上，使頂部柵極21與第一載片台11固定連接、頂部源極22和第二載片台12連接。 As shown in FIG. 11, the top gate 21 and the top source 22 of the semiconductor wafer 20 are downwardly flipped onto the first stage 11 and the second stage 12, so that the top gate 21 and the first A stage 11 is fixedly connected, and the top source 22 and the second stage 12 are connected.

在倒裝晶片20的過程中，需要對第一載片台11和第二載片台12進行加熱：在95℃~130℃(最好是120℃)的高溫下將晶片20通過第一印刷粘接材料31同時貼附至第一引線框架10的第一載片台11和第二載片台12上，所需時間大約為200ms，所需壓力與MOSFET晶片20的尺寸大小相關，一般單位面積上的壓力是85g/mm2。 In the process of flipping the wafer 20, the first stage 11 and the second stage 12 need to be heated: the wafer 20 is passed through the first printing at a high temperature of 95 ° C to 130 ° C (preferably 120 ° C). The bonding material 31 is simultaneously attached to the first stage 11 and the second stage 12 of the first lead frame 10, and the time required is about 200 ms, and the required pressure is related to the size of the MOSFET wafer 20, and the general unit The pressure on the area is 85 g/mm 2 .

如第20圖所示，用與上述印刷半導體晶片20相類似的步驟，在第三載片台13上印刷形成第二印刷粘接材料32。即通過在絲網或網板上開設若干開口，與整條第二引線框架上的若干個第三載片台13位置相對應；根據不同需要，將開口設為具有與之後要貼附連接的MOSFET晶片20相同或不同的形狀，相同、稍小或稍大一點的尺寸。 然後印刷整條第二引線框架，在上述若干開口中形成厚度與開口厚度(即絲網或網板上厚度)相同的第二印刷粘接材料32，再進行1小時、110℃~130℃的高溫固化，得到一面塗覆有第二印刷粘接材料32的第三載片台13。 As shown in Fig. 20, a second printing adhesive 32 is formed on the third stage 13 by a procedure similar to that described above for printing the semiconductor wafer 20. That is, by opening a plurality of openings on the screen or the mesh board, corresponding to the positions of the plurality of third stage stations 13 on the entire second lead frame; according to different needs, the openings are set to have a connection with the subsequent attachment. The MOSFET wafers 20 are of the same or different shape, the same size, slightly smaller or slightly larger. Then printing the entire second lead frame, forming a second printing bonding material 32 having the same thickness as the opening thickness (ie, the thickness of the screen or the screen) in the plurality of openings, and then performing 1 hour, 110 ° C to 130 ° C At a high temperature, a third stage 13 coated with a second printing adhesive 32 is obtained.

如第12圖所示，以95℃~130℃(最好是120℃)的高溫加熱第三載片台13，在單位面積85g/mm2的壓力下，時間200ms後，即能將第三載片台13通過第二印刷粘接材料32固定貼附在半導體晶片20的底部漏極上，使第三載片台13上設有的漏極引腳D延伸在第二引線框架外、與第一載片台11的柵極引腳G、第二載片台12的源極引腳S相對的一側。隨後在烤箱中以175℃進行1小時的固化。 As shown in Fig. 12, the third stage 13 is heated at a high temperature of 95 ° C to 130 ° C (preferably 120 ° C), and at a pressure of 85 g/mm 2 per unit area, after a time of 200 ms, the third stage can be used. The stage 13 is fixedly attached to the bottom drain of the semiconductor wafer 20 by the second printing adhesive 32, so that the drain pin D provided on the third stage 13 extends outside the second lead frame, and The gate pin G of one of the stages 11 and the source pin S of the second stage 12 are opposite to each other. It was then cured in an oven at 175 ° C for 1 hour.

如第13圖所示，並通過塑封體40對第一載片台11、第二載片台12、半導體晶片20、第三載片台13進行封裝，使第一載片台11的柵極引腳G、第二載片台12的源極引腳S、暴露在該塑封體40的底面一側，而第三載片台13的漏極引腳D暴露在底面的相對一側。 As shown in FIG. 13, the first stage 11, the second stage 12, the semiconductor wafer 20, and the third stage 13 are packaged by the molding body 40 to make the gate of the first stage 11 The pin G, the source pin S of the second stage 12, are exposed on the bottom side of the molding body 40, and the drain pin D of the third stage 13 is exposed on the opposite side of the bottom surface.

如第14圖所示，由於第三載片台13還需要通過暴露在塑封體40的底部的散熱焊盤131對半導體晶片20進行散熱，該散熱焊盤131設置在第三載片台13的底面，即沒有塗覆第二印刷粘接材料32的一面。因此在封裝前，需要在整條第二引線框架背面相應位置黏貼薄膜，以防止封裝時塑封體40流到暴露的散熱焊盤131和上述暴露的柵極引腳G、源極引腳S、漏極引腳D上。 As shown in FIG. 14, since the third stage 13 further needs to dissipate heat from the semiconductor wafer 20 through the heat dissipation pads 131 exposed at the bottom of the molding body 40, the heat dissipation pads 131 are disposed on the third stage 13 The bottom surface, that is, the side on which the second printing adhesive material 32 is not applied. Therefore, before packaging, the film needs to be adhered to the corresponding position on the back side of the entire second lead frame to prevent the molding body 40 from flowing to the exposed heat dissipation pad 131 and the exposed gate pin G and the source pin S, Drain pin D.

最後對整條的第一、第二引線框架切割，以形成若干個獨立的半導體裝置。由於在通過印刷粘接材料封裝的半導體裝置的製造過程中沒有使用任何點膠或點焊錫進行連接，完全避免了上述現有連接技術所存在的缺陷，使得產品的品質和生產效率得以提高。 Finally, the entire first and second lead frames are cut to form a plurality of individual semiconductor devices. Since the connection is not performed using any dispensing or spot solder in the manufacturing process of the semiconductor device packaged by the printed bonding material, the defects of the above existing connection technology are completely avoided, and the quality and production efficiency of the product are improved.

儘管本發明的內容已經通過上述優選實施例作了詳細介紹，但應當認識到上述的描述不應被認為是對本發明的限制。在本領域技術人 員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。因此，本發明的保護範圍應由所附的申請專利範圍來限定。 Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Technical person in the field Various modifications and alterations of the present invention will become apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

Claims (18)

一種經由印刷粘接材料封裝的半導體裝置，其特徵在於，包含：一第一引線框架(10)，其設有電性隔離的一第一載片台(11)、一第二載片台(12)；一半導體晶片(20)，經由在其頂面的若干頂部電極上印刷形成的、導電的一第一印刷粘接材料(31)固定貼附於該第一載片台(11)和第二載片臺上(12)；該第一印刷粘接材料(31)是對一個晶圓頂面上的多個半導體晶片(20)同時印刷形成的；設置在一第二引線框架上的一第三載片台(13)，經由在其頂面印刷形成的、導電的第二印刷粘接材料(32)固定貼附於該半導體晶片(20)底面的若干底部電極上。 A semiconductor device packaged by a printed adhesive material, comprising: a first lead frame (10) provided with a first carrier stage (11) electrically isolated, and a second stage ( 12); a semiconductor wafer (20) fixedly attached to the first stage (11) by a conductive first printing bonding material (31) formed by printing on a plurality of top electrodes of the top surface thereof a second stage (12); the first printing bonding material (31) is formed by simultaneously printing a plurality of semiconductor wafers (20) on a top surface of a wafer; and disposed on a second lead frame A third stage (13) is fixedly attached to a plurality of bottom electrodes of the bottom surface of the semiconductor wafer (20) via a conductive second printing bonding material (32) formed on the top surface thereof. 如申請專利範圍第1項所述經由印刷粘接材料封裝的半導體裝置，其中該第一載片台(11)、第二載片台(12)上分別設有若干引腳，將粘接固定在該第一載片台(11)、第二載片台(12)上的該半導體晶片(20)的若干頂部電極與一外部元裝置連通。 The semiconductor device packaged by the printing adhesive material according to the first aspect of the invention, wherein the first stage (11) and the second stage (12) are respectively provided with a plurality of pins for bonding and fixing A plurality of top electrodes of the semiconductor wafer (20) on the first stage (11) and the second stage (12) are in communication with an external element device. 如申請專利範圍第1項所述經由印刷粘接材料封裝的半導體裝置，其中該粘接固定在該半導體晶片(20)底面的第三載片台(13)上設有若干引腳，將該半導體晶片(20)的若干底部電極與外部元裝置連通。 The semiconductor device packaged by the printing adhesive material according to the first aspect of the invention, wherein the third stage (13) fixed to the bottom surface of the semiconductor wafer (20) is provided with a plurality of pins, A number of bottom electrodes of the semiconductor wafer (20) are in communication with external element devices. 如申請專利範圍第1項所述經由印刷粘接材料封裝的半導體裝置，其中該半導體晶片(20)的若干頂部電極上分別包含若干區域的、藉由印刷形成的該第一印刷粘接材料(31)。 The semiconductor device packaged by the printing adhesive material according to the first aspect of the invention, wherein the plurality of top electrodes of the semiconductor wafer (20) respectively comprise a plurality of regions of the first printed bonding material formed by printing ( 31). 如申請專利範圍第1項所述經由印刷粘接材料封裝的半導體裝置，其中該在半導體晶片(20)頂面印刷形成的所述第一印刷粘接材料(31)具有與該頂部電極相同或不同的形狀。 The semiconductor device packaged by the printed adhesive material according to claim 1, wherein the first printed adhesive material (31) formed on the top surface of the semiconductor wafer (20) has the same or the top electrode Different shapes. 如申請專利範圍第1項所述經由印刷粘接材料封裝的半導體裝置，其中 在該半導體晶片(20)頂面印刷形成的該第一印刷粘接材料(31)的尺寸等於或小於所述頂部電極的面積。 a semiconductor device packaged by a printed bonding material as described in claim 1 of the patent application, wherein The size of the first printed bonding material (31) formed on the top surface of the semiconductor wafer (20) is equal to or smaller than the area of the top electrode. 如申請專利範圍第1項所述經由印刷粘接材料封裝的半導體裝置，其中該第三載片台(13)頂面印刷形成的該第二印刷粘接材料(32)尺寸與該半導體晶片(20)面積相等。 The semiconductor device packaged by the printing adhesive material according to the first aspect of the invention, wherein the size of the second printing bonding material (32) formed by printing on the top surface of the third stage (13) is the same as the semiconductor wafer ( 20) The area is equal. 如申請專利範圍第1項所述通過印刷粘接材料封裝的半導體裝置，其中該第三載片台(13)頂面印刷形成的該第二印刷粘接材料(32)尺寸與該半導體晶片(20)面積不相等。 The semiconductor device packaged by the printing adhesive material according to the first aspect of the invention, wherein the size of the second printing bonding material (32) formed by printing on the top surface of the third stage (13) is the same as the semiconductor wafer ( 20) The areas are not equal. 如申請專利範圍第1項所述通過印刷粘接材料封裝的半導體裝置，還包含一塑封體(40)，其將該第一載片台(11)、第二載片台(12)、半導體晶片(20)、第三載片台(13)封裝在其內部，使所述第一載片台(11)、第二載片台(12)、第三載片台(13)上分別設有的若干引腳暴露該塑封體(40)外。 The semiconductor device packaged by the printing adhesive material according to claim 1, further comprising a molding body (40) for the first stage (11), the second stage (12), and the semiconductor The wafer (20) and the third stage (13) are packaged therein, and the first stage (11), the second stage (12) and the third stage (13) are respectively disposed. A number of pins are exposed outside the molding body (40). 如申請專利範圍第9項所述經由印刷粘接材料封裝的半導體裝置，其中該第三載片台(13)的底面還設有一散熱焊盤(131)，該散熱焊盤(131)暴露在該塑封體(40)外。 The semiconductor device packaged by the printed adhesive material according to claim 9, wherein the bottom surface of the third stage (13) is further provided with a heat dissipation pad (131), and the heat dissipation pad (131) is exposed. The plastic body (40) is outside. 一種通過印刷粘接材料封裝的半導體裝置的製造方法，其特徵在於，包含以下步驟：步驟1.1在晶圓頂面上對應各個半導體晶片(20)的若干頂部電極位置印刷導電的第一印刷粘接材料(31)；步驟1.2高溫固化第一印刷粘接材料(31)；步驟1.3對晶圓進行劃分以及切割操作，形成若干獨立的半導體晶片(20)；步驟2.1在第三載片台(13)頂面上印刷導電的第二印刷粘接材料(32)；步驟2.2高溫固化第二印刷粘接材料(32) 步驟3. 高溫下將半導體晶片(20)頂面通過第一印刷粘接材料(31)同時粘接到第一載片台(11)和第二載片台(12)上；步驟4. 高溫下將第三載片台(13)通過第二印刷粘接材料(32)粘接至半導體晶片(20)底面；步驟5. 高溫下對第一印刷粘接材料(31)、第二印刷粘接材料(32)進行高溫固化；步驟6. 將第一載片台(11)、第二載片台(12)、半導體晶片(20)、第三載片台(13)封裝在塑封體(40)內。 A method of fabricating a semiconductor device packaged by a printed adhesive material, comprising the steps of: step 1.1 printing a conductive first print bond on a top surface of the wafer corresponding to a plurality of top electrode positions of respective semiconductor wafers (20) Material (31); step 1.2 high temperature curing of the first printing bonding material (31); step 1.3 dividing the wafer and cutting operation to form a plurality of independent semiconductor wafers (20); step 2.1 in the third stage (13) Printing a conductive second printing bonding material (32) on the top surface; step 2.2 high temperature curing second printing bonding material (32) Step 3. The top surface of the semiconductor wafer (20) is simultaneously bonded to the first stage (11) and the second stage (12) through the first printing bonding material (31) at a high temperature; Step 4. High temperature The third stage (13) is bonded to the bottom surface of the semiconductor wafer (20) through the second printing bonding material (32); step 5. The first printing bonding material (31) and the second printing paste are applied at a high temperature. The bonding material (32) is cured at a high temperature; and the first stage (11), the second stage (12), the semiconductor wafer (20), and the third stage (13) are packaged in a plastic package ( 40) inside. 如申請專利範圍第11項所述經由印刷粘接材料封裝的半導體裝置的製造方法，其中該步驟1是利用絲網或網板印刷技術對晶圓進行印刷，一次完成一片晶圓的印刷，具體包含以下步驟：步驟1.1.1在絲網或網板上開設若干開口；其中，該若干開口的數量和位置，分別對應該片晶圓頂面需要設置第一印刷粘接材料(31)的頂部電極的數量和位置；步驟1.1.2在所述各個開口中印刷形成第一粘接材料(31)；其中，所述第一粘接材料(31)的厚度是由所述絲網或網板上開口的厚度決定。 The method for manufacturing a semiconductor device packaged by a printing adhesive material according to claim 11, wherein the step 1 is to print the wafer by using a screen or screen printing technology, and to complete the printing of one wafer at a time. The method includes the following steps: Step 1.1.1 opens a plurality of openings on the screen or the mesh board; wherein the number and positions of the plurality of openings respectively correspond to the top surface of the wafer wafer, and the top of the first printing adhesive material (31) is required The number and position of the electrodes; step 1.1.2 is printed in the respective openings to form a first bonding material (31); wherein the thickness of the first bonding material (31) is determined by the screen or the mesh The thickness of the upper opening is determined. 如申請專利範圍第12項所述經由印刷粘接材料封裝的半導體裝置的製造方法，其中該步驟1.1.1中若干開口具有與所述頂部電極相同或不同的形狀。 A method of fabricating a semiconductor device packaged via a printed bonding material as described in claim 12, wherein a plurality of openings in the step 1.1.1 have the same or different shapes as the top electrode. 如申請專利範圍第12項所述經由印刷粘接材料封裝的半導體裝置的製造方法，其中該步驟1.1.1中若干開口的尺寸等於或小於所述頂部電極的面積。 A method of fabricating a semiconductor device packaged via a printed bonding material as described in claim 12, wherein the size of the plurality of openings in the step 1.1.1 is equal to or smaller than the area of the top electrode. 如申請專利範圍第11項所述經由印刷粘接材料封裝的半導體裝置的製造方法，其中該步驟2.1是利用絲網或網板印刷技術對第二引線框架上的第三載片台(13)頂面進行印刷，一次完成一條第二引線框架的印刷， 具體包含以下步驟：步驟2.1.1在絲網或網板上開設若干開口；其中，所述若干開口的數量和位置，分別對應該條第二引線框架上需要設置第二印刷粘接材料(32)的第三載片台(13)的數量和位置；步驟2.1.2在所述各個開口中印刷形成第二粘接材料(32)；其中，所述第二粘接材料(32)的厚度是由所述絲網或網板上開口的厚度決定。 A method of manufacturing a semiconductor device packaged by a printing adhesive material according to claim 11, wherein the step 2.1 is to use a screen or screen printing technique to the third stage (13) on the second lead frame. The top surface is printed, and one second lead frame is printed at a time. Specifically, the method includes the following steps: Step 2.1.1 opening a plurality of openings on the screen or the grid; wherein the number and position of the plurality of openings respectively correspond to the second printed bonding material on the second lead frame (32) The number and position of the third stage (13); the step 2.1.2 is printed in the respective openings to form a second bonding material (32); wherein the thickness of the second bonding material (32) It is determined by the thickness of the opening on the screen or screen. 範圍第15項所述通過印刷粘接材料封裝的半導體裝置的製造方法，其中該步驟2.1.1中若干開口的尺寸等於或小於在該步驟4中第三載片台(13)貼附的該半導體晶片(20)的面積。 The method of manufacturing a semiconductor device packaged by a printing adhesive material according to Item 15, wherein the size of the plurality of openings in the step 2.1.1 is equal to or smaller than the size of the third stage (13) attached in the step 4. The area of the semiconductor wafer (20). 專利範圍第11項所述通過印刷粘接材料封裝的半導體裝置的製造方法，其中，該步驟1.2及步驟2.2中所述固化溫度為110℃~130℃；該步驟3中將所述半導體晶片(20)粘接到所述第一載片台(11)和第二載片台(12)、所述步驟4中將所述第三載片台(13)粘接到所述半導體晶片時的溫度在95℃~130℃；該步驟5中對第一印刷粘接材料(31)、第二印刷粘接材料(32)的固化溫度是175℃。 The manufacturing method of the semiconductor device packaged by the printing adhesive material according to Item 11, wherein the curing temperature in the steps 1.2 and 2.2 is 110 ° C to 130 ° C; the semiconductor wafer is in the step 3 ( 20) bonding to the first stage (11) and the second stage (12), and bonding the third stage (13) to the semiconductor wafer in the step 4 The temperature is between 95 ° C and 130 ° C; the curing temperature of the first printing adhesive material (31) and the second printing adhesive material (32) in the step 5 is 175 ° C. 如申請專利範圍第11項所述經由印刷粘接材料封裝的半導體裝置的製造方法，其中在該步驟6中封裝前，還包含在整條第二引線框架的第三載片台(13)底面黏貼薄膜的步驟；該薄膜黏貼在該散熱焊盤(131)上及該第一載片台(11)、第二載片台(12)、第三載片台(13)分別設有的若干引腳上。 The method of manufacturing a semiconductor device packaged by a printed adhesive material according to claim 11, wherein before the package in the step 6, the bottom surface of the third stage (13) of the entire second lead frame is further included. a step of adhering the film; the film is adhered to the heat dissipation pad (131) and the first stage (11), the second stage (12), and the third stage (13) are respectively provided On the pin.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW329533B (en) * 1991-02-08 1998-04-11 Toshiba Co Ltd The manufacturing method for semiconductor device
US20050287708A1 (en) * 2004-06-24 2005-12-29 Kim Sang-Young Semiconductor chip package manufacturing method including screen printing process
US20080211070A1 (en) * 2004-11-23 2008-09-04 Ming Sun Flip chip contact (FCC) power package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW329533B (en) * 1991-02-08 1998-04-11 Toshiba Co Ltd The manufacturing method for semiconductor device
US20050287708A1 (en) * 2004-06-24 2005-12-29 Kim Sang-Young Semiconductor chip package manufacturing method including screen printing process
US20080211070A1 (en) * 2004-11-23 2008-09-04 Ming Sun Flip chip contact (FCC) power package

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